JPH02130836A - Manufacture of silicon thin-film transistor - Google Patents

Abstract

PURPOSE:To make it possible to use cheap glass substrates by resist-etching a gate electrode pattern on a gate insulating film, removing the gate insulating film using the gate electrode and resist as masks, laminating a doped layer all over the surface, then removing the resist and the doped layer on the resist together, and annealing them after a lift-off process. CONSTITUTION:A gate insulating layer 3 is patterned by dry etching using SF6/C2ClF5. Then, a doped layer 6 doped with P<+> boron ions is formed using silane gas containing 1% diborane(B2H6). Following that, resist is exfoliated through a lift-off method, and the doped layer 6 attached to the upper surface in a film is removed simultaneously. And, after a film of capping material 7 is attached annealing is performed in vacuum using an XeCl excimer laser. On this occasion, a gate metal functions as a mask and prevents a laser beam from striking the amorphous silicon under the gate electrode 4, and the influence on the channel section can be prevented. This makes possible the formation of source-drain electrodes without implanting ions, in a planar type in addition, and by a self-alignment system, and the formation of polycrystalline silicon under a low temperatures of 400 deg.C or less, as well.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing thin film transistors using polycrystalline silicon, and in particular to a method for manufacturing thin film transistors using polycrystalline silicon, which can be manufactured at a low temperature of 400°C or less and has excellent characteristics. It relates to the manufacture of silicon thin film transistors.

[Conventional technology]

Conventional thin film transistors using amorphous silicon have been announced and are being applied to displays and sensors. However, amorphous silicon cannot operate at high speed due to its low mobility, and can only drive a current of several tens of microamperes, so its applications are limited. In order to compensate for these problems, development of thin film transistors using polycrystalline silicon, which has even higher mobility, has become active.

However, in order to form a polycrystalline silicon layer on a substrate, it is necessary to increase the crystal size in the polycrystalline silicon layer, and in order to grow the crystals, a method of heating to about 100°C to an amorphous state and then recrystallizing is used. Therefore, there is a problem in that an inexpensive glass substrate cannot be used as the substrate, and quartz must be used. Further, there is a problem in that ion implantation is required to form the source/drain regions, and a large-scale device is required.

Therefore, it has recently been reported that polycrystalline silicon can be formed using an excimer laser (Xec4, ArF) (T, Sameshima et al, JEE
E Electr.

n Device Letters 5 (1986)
p, 276), The source and drain electrodes of L-shaped polycrystalline thin film silicon transistors (hereinafter referred to as poly-StTFTs) are generally formed by conventional ion implantation. device announced (Kenji Sera et al., 1986)
Spring Applied Physics, 28p-N-12) However, since the gate electrode is formed by patterning,
In order to maintain matching with the source/drain electrodes, the overlap portion inevitably becomes large, increasing parasitic capacitance, and the characteristics are not very good.

[Problem to be solved by the invention]

In view of these circumstances, the present invention is a planar type without ion implantation, and can form source/drain electrodes using a self-alignment method.
It is an object of the present invention to provide a poly-3t TFT with excellent characteristics that allows the use of an inexpensive glass substrate because polycrystalline silicon can be formed at a low temperature of 00° C. or lower.

[Means to solve the problem]

To this end, in a method for manufacturing a silicon thin film transistor, the present invention includes a resist etching step for forming a gate electrode pattern by resist etching on a gate insulating film on the surface of a polycrystalline silicon layer laminated on a substrate, and a resist etching step for forming a gate electrode pattern on a gate insulating film on the surface of a polycrystalline silicon layer laminated on a substrate. A gate insulating film removal step in which the gate insulating film is removed as a mask, a doped layer stacking step in which a doped layer is stacked on the entire surface after the gate insulating film is removed, and a lift-off method is used to combine the resist and the doped layer on the resist. It consists of a lift-off process to remove
This method is characterized by comprising a source/drain region forming step of forming source/drain regions by annealing after the lift-off step.

When forming the polycrystalline silicon layer and the source/drain regions, an annealing method using an excimer laser may be employed (in this case, a glass substrate can be used as the substrate).

The gate insulating film is 5iO1% SiN, StN.

/ It is recommended to use SiOx etc. Furthermore, although chromium is preferably used as the gate metal, other metal conductors may also be used.

The doped layer may be either a p' layer or an n' layer.

[Effect]

The method for manufacturing poly-St TFT in the present invention is as follows:
First, a resist etching step in which a gate electrode pattern is formed by resist etching on the gate insulating film on the surface of the substrate, then a gate insulating film removal step in which the gate insulating film is removed using the gate electrode and resist as a mask, and then a gate insulating film is removed. By comprising a doped layer stacking step of stacking a doped layer on the entire surface after removal, a lift-off step of removing both the resist and the doped layer on the resist using a lift-off method, and a source-drain region forming step using annealing means. , the source/drain region can be formed with respect to the gate electrode by a self-alignment method, and moreover, it is possible to form a planar type poly-3i TF.
T can be fabricated, and when forming the source/drain region, it is possible to efficiently form an overlap portion between the gate electrode and the source/drain region.
Can prevent the formation of parasitic back channels,
A planar poly-3t TFT with excellent characteristics can be obtained.

Generally, in poly-Si TFTs, it is important to increase the crystal size of polycrystalline silicon.
For this purpose, the crystal size can be increased by heating the polycrystalline silicon layer formed by the CVD method again, temporarily melting it to an amorphous state, and then growing the crystal. In addition, when forming the source/drain regions, the ions doped in the silicon crystal lattice need to be activated not just in a mixed state but in a state bonded to the crystal lattice, and heating is also necessary for this purpose. The present invention uses an excimer laser as the annealing means, so that the annealing can be performed without affecting the substrate.
It is possible to form a polycrystalline silicon layer and source/drain regions at a low temperature of 00° C. or lower, and it is possible to use an inexpensive glass substrate as a substrate.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

〔Example〕

FIG. 1 is a diagram for explaining the manufacturing process of the poly-St TFT of the present invention using a cross-sectional view of a poly-5T TFT, and FIG. 2 is a diagram showing another example of manufacturing a polycrystalline silicon thin film according to the present invention. FIG. 3 is a diagram for explaining the case where a doping concentration gradient is applied to a polycrystalline silicon layer according to the present invention.

In the figure, 1 is a glass substrate, 2 is a polycrystalline silicon layer, 3 is a gate insulating layer, 4 is a gate electrode, 5 is a resist, 6 is a doped layer, 7 is a cap material, 8 is an insulating film between the eyebrows, and 9 is a source/drain region , 10 is an aluminum wiring part, and 11 is an insulating layer.

The method for manufacturing poly-St TPT of the present invention will be explained with reference to FIG.

First, as shown in Fig. 1(a), an amorphous silicon (α-Si:H) film was deposited at 275°C and 0.2 Torr using a Corning glass substrate 1 by the usual PCVD method.
, 200 using 100% silane gas (SiH4)
A polycrystalline silicon layer 2 is formed by depositing the polycrystalline silicon layer 2 to a thickness of 0.

The amorphous silicon layer is polycrystallized by irradiation with a XeCl excimer laser, and then, as shown in FIG.
, 2 Torrs using a mixed gas of silane gas and ammonia to a thickness of approximately 3000 mm.

Next, as shown in Figures (c), (d), and (e), chromium was formed as a gate electrode 4 by sputtering.
A gate pattern is formed using resist 5 by ordinary photolithography, and chromium is etched using a cerium nitrate etchant.

Furthermore, as shown in the same figure (f), SF h/CzCf
The gate insulating layer 3 is patterned by dry etching using Fs. At this time, in order to ensure the lift-off method after the end faces of the pattern, it is preferable to use anisotropic etching in which the end faces are also etched, and it is even more preferable to perform etching so as to form a reverse taper.

Next, in order to form a source/drain region, the process shown in FIG.
), using silane gas containing 1% diborane (BtH&), a doped layer 6 doped with p+ boron ions is formed to a thickness of about 1000 layers. When depositing this film, we took into account the later lift-off method and applied conditions that would worsen the step coverage, i.e., low temperature.
It is preferable to deposit the film under conditions of 50°C and 10.2 Torr.

Subsequently, as shown in FIG. 6(h), the resist is peeled off by a lift-off method, and the doped layer 6 deposited on its upper surface is also removed at the same time.

Furthermore, after removing the doped layer on the gate electrode 4,
As shown in FIG. 3(i), SiOx is formed as the cap material 7. The formation was performed using the same PCVD method using NtO/SiH4 gas at 300°C and 0.27°C.
The film is formed to a thickness of approximately 1000 mm under conditions of rr.

After depositing the cap material 7, as shown in the same figure (j),
Annealing is performed in vacuum using an eCl excimer laser. At this time, the gate metal of the amorphous silicon under the gate electrode 4 acts as a cester, which prevents the laser beam from entering the amorphous silicon, thereby preventing its influence on the channel portion. On the other hand, in the doped layer, the laser beam passes through the transparent cap material, melts the polycrystalline silicon layer 2, and forms activated P+ source/drain regions 9 on the surface layer of the polycrystalline silicon layer.

On the gate electrode 4 and source/drain region 9 formed in this way, as shown in FIG.
(The doped layer is not shown) An interlayer insulating film 8 is formed by coating polyimide, and then a contact portion is opened by patterning as shown in C1) of the same figure, and an aluminum film is deposited by sputtering. Figure (m)
As shown in the figure, the aluminum wiring part 10 is patterned.
The poly-5i TFT of the present invention can be manufactured by forming a poly-5i TFT.

In addition, the excimer as explained in FIGS. 1(a) and (b)
In the annealing process using a laser, an amorphous silicon film was formed directly on the glass substrate 1 and polycrystallized, but as shown in FIG. Then, a gate insulating film 3 such as a silicon nitride film is sequentially laminated, and then excimer film 3 is deposited.
By annealing with a laser, desorption of hydrogen in the amorphous silicon layer can be prevented, and crystal growth can be performed without changing the composition of polycrystalline silicon, making it possible to form a good polycrystalline silicon film. can.

Furthermore, in FIG. 1(a), a single polycrystalline silicon layer made of amorphous silicon was formed, but a slightly doped amorphous silicon layer 21' was first laminated on the glass substrate 1 side, and then a polycrystalline silicon layer made of amorphous silicon was formed. By depositing silicon N22'', it is possible to suppress leakage current caused by parasitic back channel formation by creating a doping concentration gradient in the depth direction of the polycrystalline silicon layer 2. It is necessary to set conditions so that impurities on the substrate side do not come out to the channel surface by optimizing the thickness of the crystalline silicon layer and the laser power used to anneal it.

〔Effect of the invention〕

The present invention provides a method for manufacturing a poly-St TFT by first forming a gate electrode pattern on a gate insulating film on the surface of a substrate by resist etching, and then using the gate electrode and the resist as a mask to remove the gate insulating film. A gate insulating film removal process to remove the gate insulating film, a doped layer stacking process to stack a doped layer on the entire surface after removing the gate insulating film, a lift-off process to remove both the resist and the doped layer on the resist using a lift-off method, and further lift-off. By comprising a source/drain region forming step in which a source/drain region is formed by annealing after the process, the source/drain region can be formed with respect to the gate electrode by a self-alignment method, and moreover, the planar type p.

1y-St TFTs can be manufactured, thereby preventing the formation of parasitic back channels, and manufacturing poly-St TFTs with excellent characteristics without requiring large-scale ion implantation equipment. It is something that can be done.

In addition, by using an excimer laser when forming polycrystalline silicon and source/drain regions, it is possible to
Since polycrystalline silicon can be formed and the source/drain 6!1M can be activated at a low temperature below, an inexpensive glass substrate can be used as the substrate.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the manufacturing process of the poly-Si TFT of the present invention using a cross-sectional view of a poly-5t TFT, and FIG. 2 is a diagram showing another example of manufacturing a polycrystalline silicon thin film according to the present invention. FIG. 3 is a diagram for explaining the case where a doping concentration gradient is applied to a polycrystalline silicon layer according to the present invention. In the figure, 1 is a glass substrate, 2 is a polycrystalline silicon layer, 3 is a gate insulating layer, 4 is a gate electrode, 5 is a resist, 6 is a doped layer, 7 is a cap material, 8 is an insulating film between the eyebrows, and 9 is a source/drain region , 10 is an aluminum wiring part, and 11 is an insulating layer. Applicant Fuji Xerox Co., Ltd. Representative Patent Attorney (1) Nobuhiko (5 others) Figure 1 (b) (C) (d) Figure 1 (h) (i) (j) Figure 1 (e) ) (f) Figure 1 (k)

Claims (2)

[Claims] (1) In a method for manufacturing a silicon thin film transistor,
A resist etching step in which a gate electrode pattern is formed by resist etching on the gate insulating film on the surface of the polycrystalline silicon layer laminated on the substrate, and a gate insulating film in which the gate insulating film is removed using the gate electrode and the resist as a mask. a removal step, a doped layer stacking step of stacking a doped layer on the entire surface after removing the gate insulating film, a lift-off step of removing both the resist and the doped layer on the resist using a lift-off method, and annealing after the lift-off step. 1. A method of manufacturing a silicon thin film transistor, comprising a step of forming a source/drain region. (2) The method of manufacturing a silicon thin film transistor according to claim 1, wherein an annealing method using an excimer laser is used in forming the polycrystalline silicon layer and the source/drain region.