JPH04286339A - Semiconductor device and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device formed on an insulating amorphous material and a method of manufacturing the same.

0002

[Background Art] In recent years, semiconductor devices have become highly integrated, and
Mass production of MDRAM, 1MSRAM, etc., 16M, 64MD
Development and prototyping of RAM, 4MSRAM, etc. is underway. In the future, as the density of these semiconductor devices progresses further, it is expected that expectations for the realization of semiconductor devices with three-dimensional structures will further increase. Taking SRAM as an example, 4M
In the above SRAM, the memory cells are made of high-resistance poly-
4-T type SRAM using Si or n
6 that formed channel and p-channel MOSFETs
-SRA with stacked CMOS structure instead of T-type SRAM
M is being considered and prototyped. In a stacked CMOS structure, an n-channel MOSFET is formed on a silicon substrate,
It has a structure in which p-channel poly-Si TFTs are stacked with an insulating material in between, and has the advantages of 4-T type and 6-T type. That is, the p channel is
-By forming with Si TFT and creating a stacked structure, a CMOS structure can be realized with almost the same cell size as a 4-T type, and SR has excellent high integration, soft error resistance, and low power consumption.
AM can be realized.

0003

[Problem to be solved by the invention] However, the conventional pol
The structure and manufacturing method of y-SiTFT has the following problems. (1) Since it is necessary to perform annealing at about 550° C. to 650° C. for several hours to several tens of hours, the throughput is low. (2) Solid-phase growth annealing at about 550°C to 650°C alone cannot sufficiently improve the crystallinity such as the crystallization rate of polycrystalline silicon, forming a TFT with a sufficient on-off ratio. difficult to do. (3) Since the source/drain region is formed using the gate electrode as a mask using the self-alignment method, off-leakage current occurs due to current generated by electron/hole pairs at the drain end, making it impossible to suppress off-current. There was a problem. Therefore, the present invention uses a simpler and more practical TFT structure and its manufacturing method to form highly crystalline polycrystalline silicon with good reproducibility, and to form poly-Si with high mobility and large on-off ratio.
The present invention provides an element structure for forming a TFT and a manufacturing method thereof.

0004

[Means for Solving the Problems] A semiconductor device of the present invention includes:
1) In a semiconductor device in which the channel region of an insulated gate semiconductor device is formed of a polycrystalline semiconductor mainly composed of silicon, a polycrystalline semiconductor layer containing the channel region mainly composed of silicon doped with impurities such as boron, and gate insulation. The semiconductor device is characterized by having at least a thin film forming a source/drain region formed on at least a part of a polycrystalline semiconductor layer mainly made of silicon including the channel region and a gate electrode having sidewalls.

2) The semiconductor device is characterized in that it is formed as an element of a stacked part of a three-dimensional IC.

3) The channel region is characterized in that the polycrystalline semiconductor layer mainly composed of silicon has a thickness of 50 Å to 250 Å.

4) The crystallization rate of the polycrystalline semiconductor layer is 99
．． It is characterized by being 5% or more. 5) The thin film forming the source/drain region is made of polycrystalline silicon doped with impurities.

6) The polycrystalline silicon layer doped with impurities has a resistivity of 5×10 −4 Ω·cm or less.

The method for manufacturing a semiconductor device of the present invention includes 7) a method for manufacturing a semiconductor device in which a channel region of an insulated gate semiconductor device is formed of a polycrystalline semiconductor mainly composed of silicon, including the channel region mainly composed of silicon; A step of forming a polycrystalline semiconductor layer doped with impurities such as boron, a step of forming a gate insulating film, a step of forming a gate electrode and sidewalls of the gate electrode, and a step of forming a silicon-based layer including the channel region. The method is characterized in that it includes at least a step of selectively forming a thin film forming a source/drain region on at least a part of the polycrystalline semiconductor layer.

8) In the step of forming the thin film constituting the source/drain region, the thin film is selectively formed under the condition that the thin film is not formed on at least the sidewalls.

9) A polycrystalline semiconductor layer mainly composed of silicon including a channel region is prepared by using at least a gas containing at least one of fluorine and chlorine, and further adding a doping gas such as diborane. The method is characterized in that it includes at least a step of excitation decomposition into a plasma state and forming a film.

0012

Embodiment 1 FIG. 1 is an example of a cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 1 shows a simple application example to a three-dimensional transistor (stacked CMOS).
) is shown.

In FIG. 1, 101 is a silicon substrate;
02 is a p-well region, 103 is an element isolation region, 10
4 is a gate insulating film, 105 is a gate electrode, 106 is an n+ diffusion layer forming a source/drain region, 107 is a gate insulating film, 108 is a polycrystalline silicon layer, 109 is a gate insulating film, 110 is an upper gate electrode, 111 is a sidewall, 114 is a contact hole, 112 is a low resistance thin film on polycrystalline silicon (becomes a source/drain region), 11
3 is a low resistance thin film on the gate electrode, and 115 is a wiring. The poly-Si TFT of the present invention is characterized by having a self-aligned structure using sidewalls,
It is characterized by a structure in which films are selectively formed in the source and drain regions. In the present invention, the sidewalls can prevent short circuits between the source/drain region and the gate electrode, and at the same time, the sidewalls can form an offset structure.
The generation current of electron-hole pairs at the drain end and the field-
Off-leakage current caused by enhanced-emission current or the like is suppressed, and a sufficient on-off ratio can be obtained. Further, FIG. 1 shows an example of a double gate structure in which the polycrystalline silicon layer 108 is sandwiched between two upper and lower gate electrodes 105 and 110 with a gate insulating film interposed therebetween. By adopting such a double gate structure and setting the thickness of the polycrystalline silicon layer to 250 Å or less, preferably 150 Å or less, the on-current increases dramatically, and the gate length is 1.2 μm.
The on-current when the drain voltage is 3V and the gate voltage is 3V in a P-channel transistor with a gate width of 0.6μm is:
Approximately 1×10 −6 A was obtained. Furthermore, by adopting the offset gate structure of the present invention, off-state current is also reduced.
With a P-channel transistor having a gate length of 1.2 μm and a gate width of 0.6 μm, the off-state current when the drain voltage is 0 V and the gate voltage is 0 V can be suppressed to 1×10 −14 A or less. As a result, an on-off ratio of 8 digits or more was obtained. In order for the offset structure of the upper electrode to function effectively, it is important that the lower electrode end is located inside the offset region of the upper electrode. Therefore, it is desirable to design the gate length of the lower electrode to be approximately the same as that of the upper electrode, or to be narrower than that of the upper electrode.

FIG. 2 is an example of a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention. Note that FIG. 2 shows a simple example of application to a three-dimensional transistor (stacked CMOS).

In FIG. 2, (a) shows a silicon substrate 2
In this step, a p-well region 202 is formed in 01, and an element isolation region 203 is formed using the LOCOS oxidation method.

(b) shows that after forming the gate insulating film 204,
This is a step of forming a gate electrode 205 using poly-Si or the like as an element material, and then patterning it into a predetermined shape to form an n+ diffusion layer 206 that forms a source/drain region.

(c) forms a gate insulating film 207;
This is a step of forming a polycrystalline silicon layer 208 and patterning it into a predetermined shape. Methods for forming gate insulating films include low-temperature deposition methods such as CVD, plasma CVD, ECR-PCVD, photo-CVD, and sputtering, which reduce the redistribution of impurities in elements formed on silicon substrates. This is desirable for the purpose of prevention. Next, as a method for forming a polycrystalline silicon layer, it is effective to form a polycrystalline silicon film with a thickness of about 50 Å to 1500 Å using a plasma CVD method (PCVD method) at a low substrate temperature of about 300° C. to 450° C. . In addition to SiH4, Si2H6, etc. as a reaction gas,
By mixing an appropriate amount of a reactive gas containing elements such as fluorine (F) and chlorine (Cl), a high-quality polycrystalline silicon film can be formed at a low temperature. An example of film forming conditions is shown below. As reaction gases, SiH4, dichlorosilane (SiH2Cl2), H
2, and the mixing ratio is, for example, SiH4:SiH2Cl2
= about 1:20 to 1:200, SiH4:H2 = 1:1
00 to 1:1000, and the substrate temperature to 300℃.
The temperature is maintained at about 450° C. and RF power is applied to decompose the reaction gas and form a polycrystalline silicon film. Regarding film thickness, it is known that when a polycrystalline silicon layer is made thinner, off-state current decreases and Vth (threshold voltage) decreases. Therefore, the thickness of the polycrystalline silicon layer is preferably 500 Å or less, and particularly preferably about 50 Å to 250 Å. Therefore, it is particularly important to form such a thin film of high quality polycrystalline silicon. When the substrate temperature is below 300°C, the crystallization rate is low and no <220> orientation is observed, but when the substrate temperature is about 400°C to 450°C, the
Even with a thin film of about Å to 250 Å, the crystallization rate is 98% or more.
220>, high quality polycrystalline silicon can be formed into a film. In terms of increasing the crystallization rate, a film formed at a substrate temperature of about 450°C to 600°C is even better, achieving a crystallization rate of 99.5% or more.
This is effective in increasing the on-state current and reducing the off-state current of the TFT. As described above, according to the present invention, a high-quality polycrystalline silicon film can be formed at low temperatures, so high-performance three-dimensional ICs, including the stacked CMOS shown in this example, can be manufactured at low temperatures. . Note that although this example shows the case where SiH2Cl2 is used as the reaction gas, the present invention is not limited to this. For example, SiCl4, SiH2Cl
2, SiHCl3, Cl2, SiF4, SiHF3, S
Si
By mixing appropriate amounts of reactive gases such as H4, Si2H6, Si3H8, etc., high-quality polycrystalline silicon can be formed at low temperatures.

Also, it is extremely effective to control Vth (threshold voltage) by doping impurities into the channel region. Polycrystalline silicon TF formed by solid phase growth method
At T, the N-channel transistor tends to shift Vth in the depletion direction, and the P-channel transistor tends to shift in the enhancement direction. Moreover, when the above-mentioned TFT is hydrogenated, this tendency becomes more pronounced. Therefore, 1015 to 1019/cm3 is applied to the channel area.
By doping a certain amount of impurities, the shift in Vth can be suppressed. Therefore, by mixing a doping gas such as B2H6 in addition to a gas containing chlorine or fluorine such as SiH4 and SiH2Cl2, channel doping can be performed without using ion implantation. An example of film forming conditions is SiH4+SiH2Cl2:B
2H6=1: By mixing about 0.1 ppm to 0.1%, Vth control becomes possible. In particular, by optimizing the doping amount, Vth can be controlled so that the off-state currents of both the P-channel transistor and the N-channel transistor are minimized. Therefore, even when forming a CMOS type TFT element, it is possible to control the Vth of both Pch and Nch by simply forming the polycrystalline silicon that forms the channel part without selectively doping the Pch and Nch channels. It is.

(d) is a step of forming a gate insulating film 209. CVD is the method for forming the gate insulating film.
method, plasma CVD method, ECR-PCVD method, photoCVD
A low-temperature film formation method such as a method or a sputtering method is preferable for the purpose of preventing redistribution of impurities in an element formed on a silicon substrate.

(e) is a step of forming sidewalls 211 after forming the upper gate electrode 210. first,
The gate electrode 210 is formed of polycrystalline silicon doped with impurities and patterned into a predetermined shape. The method for forming the polycrystalline silicon layer is plasma CVD (PCV).
There is a method of forming a polycrystalline silicon film with a thickness of about 500 Å to 4000 Å at a low substrate temperature of about 300° C. to 450° C. (method D). In this embodiment, a TFT having a double gate structure in which a polycrystalline silicon layer is sandwiched between an upper gate electrode and a lower gate electrode with a gate insulating film interposed therebetween is taken as an example. less than,
An example of film forming conditions is shown below. Monosilane (
SiH4), dichlorosilane (SiH2Cl2), H2
using the mixing ratio, for example, SiH4:SiH2Cl2=
About 1:20 to 1:200, SiH4:H2=1:10
diborane (B2H6) or phosphine (PH3) as a doping gas.
Using arsine (AsH3) etc., for example, SiH4:P
Mix at a mixing ratio of about H3=1:0.002 to 1:0.04. Maintain the substrate temperature at around 300°C to 450°C,
RF power is applied to decompose the reactive gas, and a film of low resistance polycrystalline silicon doped with impurities is formed. The sheet resistance of the polycrystalline silicon formed in this way is 30 to 50 Ω/□ at a film thickness of 2000 Å, and a low-resistance polycrystalline silicon can be formed at a low temperature. Note that the method for forming polycrystalline silicon is not limited to this. Next, sidewalls 211 are formed. By atmospheric pressure CVD method, sputtering method, plasma CVD method, ECR-PCVD method, etc.
An insulating film such as iOx or SiNx is formed to a thickness of about 500 Å to 3000 Å, and the insulating film is etched by anisotropic etching to form sidewalls 211.

In (f), a contact hole 214 is opened in the interlayer insulating film 207, and a low resistance thin film is placed on the polycrystalline silicon.
12 (becomes the source/drain region) and 2 above the gate electrode
13 and in the contact hole, and then,
In this step, in order to reduce defects existing at crystal grain boundaries, the wiring 215 is formed by hydrogenation by a method such as exposure to a plasma atmosphere of a gas containing at least hydrogen gas or the like. In this embodiment, an example is taken in which polycrystalline silicon doped with impurities is selectively formed on the source/drain region 212, on the gate electrode 213, and in the contact hole. An effective method for forming the polycrystalline silicon layer is to selectively grow polycrystalline silicon to a thickness of about 500 Å to 3500 Å using a plasma CVD method (PCVD method) at a low substrate temperature of about 300° C. to 450° C. That is, polycrystalline silicon 2
Polycrystalline silicon doped with impurities is selectively grown only on 08 and 210 and in the contact hole 214, and the other regions (interlayer insulating film 207, sidewall 21
1) By using a method that does not deposit polycrystalline silicon, a self-aligned TF with an offset gate structure can be created.
T can be formed at low temperatures. In particular, in the present invention, by providing sidewalls and selectively growing them, short circuits between the gate electrode and the source/drain regions can be completely prevented. As a method for forming the polycrystalline silicon layer, plasma C
Polycrystalline silicon is deposited to a film thickness of 500 Å to 3500 Å using the VD method (PCVD method) at a low substrate temperature of about 300°C to 450°C.
A selective growth method is effective. An example of film forming conditions is shown below. Monosilane (SiH4
), using dichlorosilane (SiH2Cl2), H2,
For example, the mixing ratio is SiH4:SiH2Cl2=1:20
~1:200 or so, SiH4:H2=1:100~1:
For example, SiH4:B2H6=
Mix at a mixing ratio of about 1:0.002 to 1:0.04. The substrate temperature is maintained at approximately 300° C. to 450° C., RF power is applied to decompose the reactive gas, and low resistance polycrystalline silicon doped with impurities is formed. The sheet resistance of the polycrystalline silicon formed in this way is 30 at a film thickness of 2000 Å.
~50Ω/□, and low-resistance polycrystalline silicon can be formed at a low temperature. Note that the method for forming polycrystalline silicon is not limited to this.

The present invention can be applied not only to the TFTs shown in the embodiments of FIGS. 1 and 2 but also to insulated gate semiconductor devices in general.

[0023]

As described above, according to the present invention, it is possible to control the Vth of a poly-Si TFT with a simpler manufacturing process. Furthermore, according to the TFT structure and manufacturing method of the present invention, a self-aligned TFT having an offset structure containing impurities such as B in the channel region can be formed at a low temperature, making it possible to manufacture three-dimensional ICs and the like at low cost. Became. The present invention can also be applied to large, high-resolution liquid crystal display panels and large, high-speed, high-resolution contact image sensors.

[0024] Furthermore, the present invention provides the T
In addition to FT, it can be applied to insulated gate semiconductor devices in general.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device in an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a semiconductor device in an embodiment of the present invention.

[Explanation of symbols]

101... Insulating amorphous material 102,
208... Polycrystalline silicon layer 103, 204,
207, 209... Gate insulating film 104, 20
5,210... Gate electrode 105,211 ・
... Sidewalls 106, 212 ... Source/drain region 108 ... Interlayer insulating film 109 ... Contact hole 110
··· wiring

Claims (9)

[Claims] 1. In a semiconductor device in which a channel region of an insulated gate semiconductor device is formed of a polycrystalline semiconductor mainly composed of silicon, a polycrystalline semiconductor layer including the channel region mainly composed of silicon and doped with an impurity such as boron. , comprising at least a thin film forming a source/drain region formed on at least a part of a polycrystalline semiconductor layer mainly made of silicon, including a gate insulating film, a gate electrode having sidewalls, and the channel region. semiconductor device. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed as an element of a stacked part of a three-dimensional IC. 3. The semiconductor device according to claim 1, wherein the polycrystalline semiconductor layer mainly composed of silicon forming the channel region has a thickness of 50 Å to 250 Å. 4. The crystallization rate of the polycrystalline semiconductor layer is 99.
．． 4. The semiconductor device according to claim 1, wherein the amount is 5% or more. 5. The semiconductor device according to claim 1, wherein the thin film forming the source/drain region is made of polycrystalline silicon doped with impurities. 6. The semiconductor device according to claim 5, wherein the impurity-doped polycrystalline silicon layer has a resistivity of 5×10 −4 Ω·cm or less. 7. In a method of manufacturing a semiconductor device in which a channel region of an insulated gate semiconductor device is formed of a polycrystalline semiconductor mainly composed of silicon, a polycrystalline semiconductor mainly composed of silicon including the channel region and doped with an impurity such as boron is used. A step of forming a crystalline semiconductor layer, a step of forming a gate insulating film, a step of forming a gate electrode and sidewalls of the gate electrode, and a step of forming at least a part of a polycrystalline semiconductor layer mainly made of silicon including the channel region. 1. A method of manufacturing a semiconductor device, comprising at least the step of forming a thin film selectively forming a source/drain region on the region. 8. The semiconductor according to claim 7, wherein in the step of forming the thin film forming the source/drain region, the thin film is selectively formed under the condition that the thin film is not formed on at least the sidewalls. Method of manufacturing the device. 9. A polycrystalline semiconductor layer mainly composed of silicon including a channel region is formed by using at least a gas containing at least one of fluorine and chlorine, further adding a doping gas such as diborane, and adding a doping gas such as diborane. 9. The method of manufacturing a semiconductor device according to claim 7, further comprising at least a step of excitation decomposition into a plasma state and forming a film.