JPH11186552A - Manufacture of thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a thin-film transistor having a polycrystalline silicon layer, which is capable of having less roughened surface without causing deterioration in the crystallization of a zone in which transistor carriers move. SOLUTION: An energy beam is irradiated on an amorphous silicon layer 3 formed on a substrate l to crystallize the layer 3 and to form a crystalline silicon layer 12a. Thereafter, a surface of the crystalline silicon layer 12a is etched to make its crystalline silicon surface smooth. When the etching is carried out through a chemical reaction based on thermal energy in a vapor phase using ClF3 , damages to the silicon layer or the like can be suppressed, dangling bonds on the crystalline silicon layer can be terminated with and F atom, thus enabling suppression of oxidation of the silicon surface due to oxygen atoms present in the atmosphere.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a thin film transistor using an amorphous or crystalline silicon thin film.

[0002]

2. Description of the Related Art As an example of a conventional thin film transistor using a crystalline semiconductor as a semiconductor layer, a polysilicon thin film transistor (hereinafter abbreviated as "poly-SiTFT") being developed for a liquid crystal display device will be described below. This will be described with reference to the drawings.

In recent years, in the field of liquid crystal display devices using thin film transistors, polycrystalline silicon thin film transistors (hereinafter, referred to as “polycrystalline silicon thin film transistors” (hereinafter referred to as “600 ° C. or less”) capable of using an inexpensive glass substrate instead of an expensive quartz substrate can be used. Abbreviated as "low temperature poly-Si TFT"). Therefore, in the following, for example, “IEEE ELEC
TRON DEVICE LETTERS, Vol.
EDL-7, no. 5 (1986), p. p. 2
Low temperature poly-SiT described in "76-378"
An FT will be briefly described with reference to FIG.

In this conventional method of manufacturing a low-temperature poly-Si TFT, first, a buffer layer 2
After depositing an amorphous silicon layer 3 of 500 to 1000 ° on the entire surface through Si ₃ N _{4 of 0} °, the amorphous silicon layer 3 on the substrate is locally heated and melted by irradiating an excimer laser to crystallize. (FIG. 4A). Next, a gate insulating layer 5 is formed on the polycrystalline silicon layer 4 obtained by crystallization.
A 100% Si ₃ N ₄ and a 1500 ° SiO ₂ layer are formed. Then, a gate electrode 6 is formed using Mo of 6000 °, and phosphorus ions are implanted in this state (FIG. 4).
(B)). Then, for activation of the injected phosphorus,
The source region 7 and the drain region 8 are formed by irradiating an excimer laser again (FIG. 4C). Then, a contact hole 9 is formed, and finally, a source electrode 10 and a drain electrode 11 are formed using 3000 ° Al (FIG. 4D), whereby a low-temperature poy-SiTF is formed.
T is made.

[0005]

However, when the conventional low-temperature poly-Si TFT shown in FIG. 4 is manufactured, the following problems occur.

In the example shown in FIG. 4, low-temperature poly-Si
To form a, after depositing a-Si by plasma CVD,
An excimer laser using XeCl is irradiated to locally melt and crystallize, but the melting and solidification (crystallization) change the volume and crystallinity of the silicon and cause the silicon surface to change. Irregularities occur on the surface. As a result, the unevenness adversely affects the mobility of the carrier and the amount of ON current of the TFT. Therefore, a polycrystalline silicon thin film having less surface irregularities is desired.

On the other hand, a method for eliminating irregularities on the silicon surface has been proposed. This is a method in which crystallization is performed by irradiating a laser while the surface of the amorphous silicon layer is covered with SiO ₂ or the like.

However, in such a method, unevenness
However, good TFT characteristics have not been obtained.
The cause is instead of eliminating the unevenness of crystallized silicon
Another problem is that the crystallinity of silicon decreases. Amorphous
Excimer laser irradiation with the surface of the recon exposed
And crystallize the silicon once melted
That crystal grains grow from the glass substrate side
become. The silicon crystallized through such a grain growth process
The crystallinity of the concrete layer is the exposed side opposite to the glass substrate side
Is good. Here, as described above, amorphous silicon
The surface of the layer is SiO _TwoExcimer laser covered with
When the used crystallization is performed, the above-mentioned grain growth occurs on the glass substrate side.
Not only from SiO_TwoIt also occurs from the side,
Transistor carriers pass through a silicon layer with excellent crystallinity.
Can not be formed in the part where it passes.

In view of the above problems, the present invention provides a method of manufacturing a thin film transistor having a polycrystalline silicon layer having less surface irregularities without impairing the crystallinity of a portion of the transistor through which carriers pass. Is the main purpose.

[0010]

In order to achieve the above object, a method for manufacturing a thin film transistor according to the present invention comprises the steps of: irradiating an amorphous silicon layer formed on a substrate with an energy beam; After crystallizing to form a crystalline silicon layer, the surface of the crystalline silicon layer is etched to remove irregularities on the crystalline silicon surface.

[0011] According to the above configuration, it is possible to eliminate irregularities on the surface of the crystalline silicon layer without deteriorating the crystallinity.

In the above structure, when the etching of the surface of the crystalline silicon layer is performed by a chemical reaction in a gas phase through thermal energy, no plasma is used, so that the occurrence of damage to the silicon layer and the like is suppressed. can do.

Further, in the above configuration, the dangling bond on the surface of the etched crystalline silicon layer is
Termination with atoms can suppress oxidation of the silicon surface due to atmospheric oxygen and the like.

In the above structure, the surface of the crystalline silicon layer is etched by at least ClF ₃ , Xe
When the treatment is performed using a gas containing any of F ₂ , BrF _3, or BrF ₅ , unevenness on the surface of the crystalline silicon layer is eliminated without impairing crystallinity, and oxidation of the silicon surface due to oxygen in the atmosphere is suppressed. Can be achieved at the same time.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION In order to achieve the above object, the present inventors have made various studies and found that irregularities generated on the surface of a crystalline silicon layer by crystallization by irradiation with an energy beam such as an excimer laser were removed. As a method of performing the etching, the unevenness on the silicon surface once formed is removed by etching (specifically, a chemical reaction in a gas phase via thermal energy, for example, mainly using a F-based gas to mainly disturb the crystal. It has been found that it is extremely useful to selectively etch a projection portion containing a large amount of In addition,
According to this method, dangling bonds of silicon atoms on the silicon surface can be terminated with F atoms,
Generation of a natural oxide film and impurities when the polycrystalline silicon thin film is exposed to the atmosphere can also be prevented.

(Embodiment 1) Hereinafter, a method of manufacturing a polycrystalline silicon thin film transistor (particularly, a method of manufacturing a polycrystalline silicon thin film having a flat surface) according to an embodiment of the present invention will be described in detail with reference to FIG. The description will be made step by step with reference to the sectional views.

First, diffusion of impurities in a glass substrate is prevented.
As buffer layer 2 for _TwoSubstrate with film
1 (# 1737 glass manufactured by Corning Incorporated)
(SiH_FourCVD using) as source gas
Amorphous silicon 3
(Hereinafter abbreviated as a-Si) (FIG. 1)
(A)).

Next, as an energy beam, for example, X
The amorphous silicon is crystallized by irradiation with an eCl excimer laser to obtain a polycrystalline silicon thin film 12a (FIG. 1B). Irradiation conditions at this time depend on conditions such as a-Si film thickness and film quality.
The irradiation can be performed in the range of 0 to 450 mJ / cm ² and the number of irradiations in the range of 1 to 500 times. Due to this crystallization, irregularities having a height of about 50 nm are generated on the polycrystalline silicon surface (FIG. 1).
(B)).

Thereafter, the substrate is inserted into an etching chamber (made of quartz), and a mixed gas of ClF ₃ and N ₂ is introduced to etch the polycrystalline silicon surface. In this mixed gas, ClF ₃ is an etching gas,
N ₂ is the diluent gas. In the present embodiment, ClF ₃ is set to 0.1.
1 liter / minute, N ₂ gas was introduced into the chamber heated to about 100 ° C. at a flow rate of 2 liter / minute. As a result, the surface irregularities are reduced, and the substantially flat polycrystalline silicon layer 1 is formed.
2b was obtained (FIG. 1 (c)). The temperature is 200 ° C
The following is preferred.

According to the present embodiment as described above, since the grain growth during crystallization of the amorphous silicon layer occurs only from the glass substrate side, the exposed surface side (in other words, the exposed surface side) The crystallinity on the side where the irregularities are generated) is good, and according to the above method, only the very small projections on the surface are removed. A crystallized silicon layer free from defects can be formed.

According to the present embodiment, the irregularities on the surface are removed by etching. At this time, it is also possible to clean the surface of the crystallized silicon layer. Further, when etching is performed using F as described above, dangling bonds existing on the surface of the silicon layer can be terminated, so that reactions such as oxidation of the silicon surface due to oxygen in the atmosphere can be suppressed. .

In this embodiment, etching is performed by using a chemical reaction in a gas layer via thermal energy as described above, and damage to a substrate or the like occurs as compared with etching using plasma. Although not preferred, it is possible in principle to remove irregularities on the crystallized silicon surface by etching using plasma.

In this embodiment, plasma CVD is used.
Although a-Si is used by the method, it may be formed by a low pressure CVD method other than the plasma CVD method, a sputtering method, or the like. Also, a
In addition to -Si, microcrystalline silicon or polycrystalline silicon may be used as a starting material. For example, germanium (G
The compound with e) may be used.

In this embodiment, a XeCl excimer laser is used as an energy beam.
Other excimer lasers such as F and KrF, Ar lasers, and the like may be used, and it is of course possible to use an electron beam or the like.

In this embodiment, ClF ₃ is used as a gas used for etching for removing irregularities on the surface of the crystallized silicon layer. Alternatively, XeF ₂ or BrF
Etching may be performed with a gas containing either ₃ or BrF ₅ .

(Embodiment 2) FIG. 2 is a process sectional view for explaining a method of forming a flattened polycrystalline silicon thin film transistor, which will be described in the following order.

First, diffusion of impurities in the glass substrate is prevented.
As buffer layer 2 for _TwoSubstrate with film
1 on Corning # 1737 glass
Polycrystalline silicon thin film planarized by the method shown in Embodiment 1.
Is formed (FIG. 2A). And this polycrystalline silico
Pattern is formed into islands by normal photolithography and etching.
After performing the polishing, for example, TEOS (Tetraity
lorthosilicate: (C_TwoH_FiveO)_FourSi)
Insulation by plasma CVD method using Pt as source gas
SiO to be layer 5_TwoIs deposited on the entire surface with a thickness of 100 nm.
(FIG. 2B).

Thereafter, the gate electrode 6 is formed using, for example, Al.
To form Then, a plasma of hydrogen-diluted phosphine (PH ₃ ) is generated, and the acceleration voltage is 70 without performing mass separation.
The source region 7 and the drain region 8 are formed by performing ion doping under the condition that the total dose is 1 × 10 ¹⁵ cm ⁻² at kV (FIG. 2C). Regarding the activation of the implanted ions, a step such as annealing can be omitted by self-activation by simultaneously implanted hydrogen. However, in order to achieve more reliable activation, annealing at 400 ° C. or more is performed. Excimer laser irradiation and RTA (Ra
Local heating by pid Thermal Anneal) may be performed.

Thereafter, TEOS (Tetraethyl)
orthosilicate: (C _TwoH_FiveO)_FourSi)
SiO 2 by plasma CVD method used as source gas_TwoThe layer
Is deposited on the entire surface as an insulating layer 14, and then the contact hole
A source electrode 10 and a drain electrode 1
As an example, aluminum (Al) is deposited by sputtering.
And then pattern by photolithography etching.
To complete the poly-Si TFT.
(FIG. 2D).

FIG. 3 shows a low-temperature pol formed in this embodiment.
Excimer laser crystallization is performed on the y-Si TFT and the starting material at exactly the same energy and irradiation frequency, but shows the transfer characteristics of the conventional low-temperature poly-Si TFT except for the step of flattening the polycrystalline silicon thin film. .
As is clear from FIG. 3, the ON current increases and the sub-threshold swing is improved due to the elimination of the unevenness on the silicon surface. The field-effect mobility of the conventional low-temperature poly-Si TFT is about 130 cm ² / Vsec, whereas the low-temperature poly-Si TFT formed by the method of the present embodiment is about 1 cm ² / Vsec.
A high value of 80 cm ² / Vsec was obtained.

In this embodiment, the plasma CVD is used.
Although a-Si is used by the method, it may be formed by a low pressure CVD method other than the plasma CVD method, a sputtering method, or the like. Although a-Si is used as a starting semiconductor material, polycrystalline silicon or microcrystalline silicon is also possible, or other materials, for example, a silicon-germanium alloy (SiGe) which is an alloy with germanium, may be used. good.

In this embodiment, XeCl is used for crystallization.
Although an excimer laser is used, other excimer lasers such as ArF and KrF, an Ar laser, and the like, and other energy beams such as an electron beam may be used.

Further, after the crystallization, it is possible to add a step of increasing crystallinity by exposing to a hydrogen plasma or performing hydrogen annealing to compensate for a trap level in a grain boundary or in a grain of the polycrystalline silicon 3. desirable.

Further, TEOS is used as the interlayer insulating layer 12.
SiO by plasma CVD method _TwoWas used, but other
Methods such as AP-CVD (Atmospheric P
SiO by the pressure CVD method_TwoAnd LTO
(Low Temperature Oxide), E
SiO by CR-CVD_TwoUntil it ’s good to say
Nor. Also, the material is silicon nitride or tantalum oxide.
Metal, aluminum oxide, etc.
A stacked structure of these thin films may be used. Also, the gate electrode
7 and the materials of the source electrode 14 and the drain electrode 15
Although aluminum was used, aluminum (A
l), tantalum (Ta), molybdenum (Mo), chromium
(Cr), metal such as titanium (Ti) or alloys thereof
However, poly-Si or po containing a large amount of impurities may be used.
A transparent conductive layer such as ly-SiGe alloy or ITO may be used.
No.

Although phosphorus is used as an impurity, P-channel and N-channel transistors are selectively formed by selectively using boron or arsenic as an acceptor and aluminum or the like other than phosphorus as a donor. It goes without saying that a CMOS circuit can be formed on a substrate.

[0036]

As described above, according to the method for manufacturing a thin film transistor of the present invention, the unevenness of the surface of the silicon forming the semiconductor layer in the polycrystalline silicon thin film transistor can be eliminated. Thus, a thin film transistor having excellent performance can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a process of planarizing a surface of polycrystalline silicon of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the thin film transistor according to the embodiment of the present invention.

FIG. 3 is a diagram showing transfer characteristics of a thin film transistor formed according to an embodiment of the present invention and a thin film transistor formed by a conventional method.

FIG. 4 is a sectional view of a manufacturing process of a conventional thin film transistor.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 substrate 2 buffer layer 3 a-Si 4 poly-Si 5 gate insulating layer 6 gate electrode 7 source region 8 drain region 9 contact hole 10 source electrode 11 drain electrode 12 a poly-Si 12 b poly-Si 12 c poly-Si 13 oxide Or nitride 14 interlayer insulating layer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masatoshi Kitagawa 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] An amorphous silicon layer formed on a substrate is irradiated with an energy beam to crystallize the amorphous silicon layer to form a crystalline silicon layer, and then a surface of the crystalline silicon layer is formed. Etching of the surface of the crystalline silicon to remove irregularities on the surface of the crystalline silicon. 2. The method according to claim 1, wherein the etching of the surface of the crystalline silicon layer is performed by a chemical reaction in a gas phase via thermal energy. 3. The method according to claim 1, wherein dangling bonds on the surface of the etched crystalline silicon layer are terminated by F atoms. 4. The etching of the surface of the crystalline silicon layer,
At least ClF _3, XeF _2, BrF _3, or method of manufacturing a thin film transistor according to claim 1, characterized in that the gas containing one of BrF _5.