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JPH02117174A - Screening method for nonvolatile memory - Google Patents

Screening method for nonvolatile memory

Info

Publication number
JPH02117174A
JPH02117174A JP63269460A JP26946088A JPH02117174A JP H02117174 A JPH02117174 A JP H02117174A JP 63269460 A JP63269460 A JP 63269460A JP 26946088 A JP26946088 A JP 26946088A JP H02117174 A JPH02117174 A JP H02117174A
Authority
JP
Japan
Prior art keywords
state
rewriting
baking
floating gate
products
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63269460A
Other languages
Japanese (ja)
Inventor
Kazuo Sato
和夫 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP63269460A priority Critical patent/JPH02117174A/en
Publication of JPH02117174A publication Critical patent/JPH02117174A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To make it possible to increase the number of rewriting times for screening more than before, and besides to ship products in a state of hardly having deteriorated, by performing baking after removing inferior products by a constant number of rewriting times. CONSTITUTION:First, floating gate-type nonvolatile memories are separated into good products and inferior products by rewriting 10<4> times in a state that the memories are assembled in a package. Then, nonvolatile memories judged good are put in a baking furnace of 180 deg.C in a state of being assembled in the package as they were, and they are left there for about 10 hours. Afterwards, they are taken out from the baking furnace and undergo the final test before the shipment. As the threshold voltage almost restores their original value by performing baking for 10 hours under 180 deg.C, they show almost the same deterioration characteristics as those from their not having deteriorated state even if rewritten 10<4> times after that.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、フローティングゲート構造を有する不揮発性
メモリのスクリーニング方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of screening a nonvolatile memory having a floating gate structure.

(従来の技術) 従来、電気的に書き込み消去が可能な E E P ROM (E ]、ectrically
 Erasable andP rogramable
 ROM)の1つとして、トンネリング注入により書き
込み・消去を行うフローティングゲート構造を有する不
揮発性メモリがよく知られている。
(Prior Art) Conventionally, electrically programmable and erasable EEPROM (E), electrically
Erasable and programmable
As one type of ROM (ROM), a nonvolatile memory having a floating gate structure in which writing and erasing are performed by tunneling injection is well known.

このフローティングゲート型の不揮発性メモリの代表的
な例を第3図を参照して説明する。これは、P型のシリ
コン基板1の中にN型拡散層からなるソース、ドレイン
2,3が形成され、ソース、ドレイン2,3にまたがっ
て酸化シリコン膜4が形成されるとともに、この酸化シ
リコンlI!I4の一部分のみを開孔し、この開孔部に
トンネリング媒体となりうる薄い酸化シリコン膜5が形
成され、酸化シリコン膜4,5の上にフローティングゲ
ート電極6、酸化シリコン膜7およびコントロールゲー
ト電極8が順次積層された構造である。
A typical example of this floating gate type nonvolatile memory will be explained with reference to FIG. In this process, sources and drains 2 and 3 made of N-type diffusion layers are formed in a P-type silicon substrate 1, and a silicon oxide film 4 is formed spanning the sources and drains 2 and 3. lI! A hole is formed only in a portion of I4, and a thin silicon oxide film 5 that can serve as a tunneling medium is formed in this hole, and a floating gate electrode 6, a silicon oxide film 7, and a control gate electrode 8 are formed on the silicon oxide films 4 and 5. It has a structure in which these are sequentially laminated.

このようなフローティングゲート構造を有する不揮発性
メモリは、ドレイン3上の薄い酸化シリコン膜5に高電
界を印加して電荷のトンネリングを行い、薄い酸化シリ
コン膜5の上のフローティングゲート電極6に電荷を蓄
積させ、トランジスタのしきい値電圧を変化させて情報
を記憶させることを原理としている。従って、第3図の
ごときフローティングゲート型不揮発性メモリにおいて
は、書き換えの際にトンネル酸化[5に高電界が印加さ
れるため、フローティングゲート型不揮発性メモリの信
頼性確保において、最も重要な点はデータ書き換え可能
な回数であり、従来一定回数の書き換えを保証するため
に、保証回数の1/10〜1/1.00程度の回数の書
き換えを全数実施して、トンネル酸化膜の欠陥やトラッ
プによる初期不良をスクリーニングする方法を用いてい
た。
A nonvolatile memory having such a floating gate structure tunnels charges by applying a high electric field to the thin silicon oxide film 5 on the drain 3, and transfers charges to the floating gate electrode 6 on the thin silicon oxide film 5. The principle is to store information by accumulating it and changing the threshold voltage of the transistor. Therefore, in a floating gate non-volatile memory as shown in Figure 3, a high electric field is applied to the tunnel oxidation [5] during rewriting, so the most important point in ensuring the reliability of the floating gate non-volatile memory is This is the number of times data can be rewritten. Conventionally, in order to guarantee a certain number of rewrites, all data must be rewritten approximately 1/10 to 1/1.00 times of the guaranteed number of times. A method was used to screen for early failures.

(発明が解決しようとする課題) しかしながら、上記のごとき従来のスクリーニング方法
は、一種の破壊試験であるために、スクリーニングの書
き換え回数をあまり多くできないと同時に、ある程度劣
化させた状態のままで製品を出荷してしまうといった問
題を有していた。
(Problem to be Solved by the Invention) However, since the conventional screening method as described above is a type of destructive test, it is not possible to rewrite the screening very many times, and at the same time, the product cannot be used in a deteriorated state to some extent. There was a problem with the product being shipped.

本発明の目的は、かかる問題点に鑑み、フローティング
ゲート構造の不揮発性メモリのスクリーニング方法にお
いて、スクリーニングの書き換え回数を従来より多くで
き、しかも、はとんど劣化していない状態で出荷できる
スクリーニング方法を提供する二とにある。
In view of these problems, an object of the present invention is to provide a screening method for non-volatile memory having a floating gate structure, which allows the screening to be rewritten more times than before, and which can be shipped in a state with almost no deterioration. There are two things to offer.

(課題を解決するための手段) 上記目的を達成するために、本発明は一定回数の書き換
えにより不良品を除去した後、ベーキングを施すことを
特徴とするものである。
(Means for Solving the Problems) In order to achieve the above object, the present invention is characterized in that after defective products are removed by rewriting a certain number of times, baking is performed.

(作 用) 本発明者の検討によれば、フローティングゲート構造の
不揮発性メモリに書き込みと消去を繰り返して行うと、
メモリ窓幅ΔVih(書き込み状態と消去状態のしきい
値電圧の差)が、書き換え回数が〜102回までは大き
くなり、102回以上になると小さくなっていき、10
″′〜10′回程度の回数でメモリとしては致命的な破
壊現象が起こることがわかった。この原因として、書き
換え回数が102回程度までは、トンネル酸化膜中にホ
ールが生成し、このホールが実効トンネル電界を増加さ
せるため、メモリ窓幅ΔV < hが増大するものと考
えられ、さらに繰り返し書き換え回数が103回以上に
なると、トンネル酸化膜中に電子がトラップされるよう
になり、このためメモリ窓幅Δv0が減少していき、最
終的にトラップされた電子の電荷により局部的に酸化シ
リコン膜の真性破壊が起こるものと推定される。
(Function) According to the inventor's study, when writing and erasing are repeatedly performed on a nonvolatile memory with a floating gate structure,
The memory window width ΔVih (the difference in threshold voltage between the written state and the erased state) increases until the number of rewrites reaches ~102 times, decreases when the number of rewrites exceeds 102 times, and becomes smaller when the number of rewrites exceeds 102 times.
It was found that fatal damage to the memory occurs after approximately 10 to 10 times.The reason for this is that holes are generated in the tunnel oxide film until the number of rewrites is approximately 102 times. It is thought that the memory window width ΔV < h increases because the effective tunnel electric field increases, and furthermore, when the number of repeated rewrites exceeds 103, electrons become trapped in the tunnel oxide film. It is presumed that the memory window width Δv0 decreases and eventually the trapped electron charges cause local intrinsic destruction of the silicon oxide film.

また、繰り返し書き換えに伴って、トンネル酸化膜中に
トラップされた電子は、第4図に示すように100℃以
上の温度でベークすると容易に放出できることを見い出
した。
It has also been found that electrons trapped in the tunnel oxide film due to repeated rewriting can be easily released by baking at a temperature of 100° C. or higher, as shown in FIG.

本発明は、上記の事実に基づいてなされたもので、一定
回数の書き換えによる不良品選別の際にトンネル酸化膜
中にトラップされた電子を1選別後にベーキングにより
放出せしめ、劣化していない初期の状態まで回復させて
出荷しようとするものである。
The present invention was made based on the above fact, and the electrons trapped in the tunnel oxide film during selection of defective products by a certain number of rewrites are released by baking after one selection, and the initial undegraded We are trying to restore the product to its original condition before shipping it.

(実施例) 本発明の具体的な実施例を図面を用いて説明する。。(Example) Specific embodiments of the present invention will be described with reference to the drawings. .

第1@は1本発明のスクリーニング方法の一実施例を示
した図である。まず、第3図に示すごときフローティン
グゲート型の不揮発性メモリをパッケージに組み立てた
状態で104回の書き換えを行って不良品と良品を選別
する。次いで、良品の不揮発性メモリを180℃のベー
ク炉の中にパッケージの状態のまま入れ、約10時間放
置する。その後、ベーク炉から出し、最終検査に行い出
荷する。
The first @ is a diagram showing an embodiment of the screening method of the present invention. First, a floating gate type non-volatile memory as shown in FIG. 3 is assembled into a package and rewritten 104 times to select defective products from non-defective products. Next, the nonvolatile memory of good quality is placed in a baking oven at 180° C. in its packaged state and left for about 10 hours. After that, it is taken out of the baking oven, subjected to a final inspection, and shipped.

以上のごとき本発明のスクリーニング方法を行。Perform the screening method of the present invention as described above.

った場合のメモリの劣化及び回復特性を第2図に示す、
第2図に示すように、10’回の書き換えによるスクリ
ーニングの後、180℃、10時間のベーキングを行う
ことにより、はぼ初期のしきい値電圧まで回復するため
、その後104回の書き換えを行っても、劣化していな
い状態からの劣化特性とほぼ同じ劣化特性を示す。
Figure 2 shows the memory deterioration and recovery characteristics when
As shown in Figure 2, after screening by rewriting 10' times, baking at 180°C for 10 hours restores the threshold voltage to the initial threshold voltage, and then rewriting 104 times. However, the deterioration characteristics are almost the same as the deterioration characteristics from the undegraded state.

(発明の効果) 以上説明したところから明らかなように9本発明によれ
ば、一定回数の書き換えによる不良品の選別を行っても
、はとんど劣化していない状態で出荷でき、しかもベー
キングにより、はぼ初期状態まで回復できるため、スク
リーニングの書き換え回数を従来より多くすることが可
能となり、フローティングゲート構造の不揮発性メモリ
の信頼性確保に大きく寄与するものである。
(Effects of the Invention) As is clear from the above explanation, according to the present invention, even if defective products are sorted out by rewriting a certain number of times, products can be shipped in a state with almost no deterioration. As a result, it is possible to recover almost to the initial state, making it possible to increase the number of screening rewrites than before, which greatly contributes to ensuring the reliability of nonvolatile memories with a floating gate structure.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例の動作フローを示す図、第
2図は、一定回数の書き換えとベーキングによるしきい
値電圧特性図、第3図は、フローティングゲート構造不
揮発性メモリの断面図、第4図は、ベーキング温度に対
する窓幅変化量を示す図である。 1 ・・・P型シリコン基板、 2,3・・・ソース、
ドレイン、 4 ・・・酸化シリコン膜、5 ・・・ 
トンネル酸化膜、 6 ・・・フローティングゲート電
極、 7・・・酸化シリコン膜、 8 ・・・コントロ
ールゲート電極。 特許aJI願人 松下電子工業株式会社第3図 1°−P型シリコン基1反 2.3−・・ソース、ドヮイッ 4°°°啄化シソコン膜 5・・・トンネジし履化膜 6 ・・・フローティングゲート電湘27・・・沃化シ
ソコン膜 8・・・ツントローIレブ’=トを極 ス7リーニンク捩 べ−り抜 善ξ訣え復 入゛−挾ングAL斐 (0C〕
Fig. 1 is a diagram showing the operation flow of an embodiment of the present invention, Fig. 2 is a threshold voltage characteristic diagram due to a certain number of rewrites and baking, and Fig. 3 is a cross section of a floating gate structure nonvolatile memory. FIG. 4 is a diagram showing the amount of change in window width with respect to baking temperature. 1...P-type silicon substrate, 2,3...source,
Drain, 4... silicon oxide film, 5...
tunnel oxide film, 6... floating gate electrode, 7... silicon oxide film, 8... control gate electrode. Patent aJI applicant Matsushita Electronics Co., Ltd. Fig. 3 1°-P-type silicon base 1 anti-2.3-... Source, Doi 4°°° Tempered Siscon film 5... Tonsei-sealed film 6...・Floating gate electric current 27...Iodized Siscon film 8...Zuntro I rev'=T to extremely low speed 7 linear link torsion excellence ξ and return ゛-Pinching AL(0C)

Claims (1)

【特許請求の範囲】[Claims] フローティングゲート構造を有する不揮発性メモリのス
クリーニング方法において、一定回数の書き換えにより
不良品を除去した後、ベーキングを施すことを特徴とす
る不揮発性メモリのスクリーニング方法。
A method for screening a non-volatile memory having a floating gate structure, the method comprising: removing defective products by rewriting a certain number of times, and then baking the memory.
JP63269460A 1988-10-27 1988-10-27 Screening method for nonvolatile memory Pending JPH02117174A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63269460A JPH02117174A (en) 1988-10-27 1988-10-27 Screening method for nonvolatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63269460A JPH02117174A (en) 1988-10-27 1988-10-27 Screening method for nonvolatile memory

Publications (1)

Publication Number Publication Date
JPH02117174A true JPH02117174A (en) 1990-05-01

Family

ID=17472745

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63269460A Pending JPH02117174A (en) 1988-10-27 1988-10-27 Screening method for nonvolatile memory

Country Status (1)

Country Link
JP (1) JPH02117174A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007184490A (en) * 2006-01-10 2007-07-19 Renesas Technology Corp Manufacturing method of semiconductor device
US7817477B2 (en) * 2007-03-30 2010-10-19 Oki Semiconductor Co., Ltd. Manufacturing method, remanufacturing method and reshipping method for a semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007184490A (en) * 2006-01-10 2007-07-19 Renesas Technology Corp Manufacturing method of semiconductor device
US7817477B2 (en) * 2007-03-30 2010-10-19 Oki Semiconductor Co., Ltd. Manufacturing method, remanufacturing method and reshipping method for a semiconductor memory device

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