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JPH023981A - Method of rewriting nonvolatile memory - Google Patents

Method of rewriting nonvolatile memory

Info

Publication number
JPH023981A
JPH023981A JP63152389A JP15238988A JPH023981A JP H023981 A JPH023981 A JP H023981A JP 63152389 A JP63152389 A JP 63152389A JP 15238988 A JP15238988 A JP 15238988A JP H023981 A JPH023981 A JP H023981A
Authority
JP
Japan
Prior art keywords
rewriting
eeprom
nonvolatile memory
baking
floating gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63152389A
Other languages
Japanese (ja)
Other versions
JP2745131B2 (en
Inventor
Kazuo Sato
和夫 佐藤
Yoshiki Fukuzaki
義樹 福崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP15238988A priority Critical patent/JP2745131B2/en
Publication of JPH023981A publication Critical patent/JPH023981A/en
Application granted granted Critical
Publication of JP2745131B2 publication Critical patent/JP2745131B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To substantially increase a number of possible rewriting operations in an EEPROM having floating gate structure, by baking the EEPROM always after repeating a certain number of rewriting operations. CONSTITUTION:A floating-gate-type EEPROM assembled into a package is subjected to up to 10<5> rewriting operations by a conventional rewriting process. The EEPROM in the packaged state is then introduced into a baking furnace at a temperature higher than 200 deg.C and left therein for about 5 hours. The EEPROM is taken out of the furnace and subjected to 10<5> rewriting operations by an ordinary rewriting process. Then, the EEPROM is baked again. By repeating this cycle, a number of possible rewriting operations can be increased substantially.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はフローティングゲート構造を有する不揮発性メ
モリの繰り返しの書き換え方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for repeatedly rewriting a nonvolatile memory having a floating gate structure.

(従来の技術) 従来、電気的に書き込み消去が可能な読取専用メモリ(
Electrically Erasable and
 ProgramableROM)(以下、EE F 
ROMという)の1つとして、トンネリング注入により
書き込み消去を行うフローティングゲート構造を有する
不揮発性メモリがよく知られている。
(Prior art) Conventionally, electrically programmable and erasable read-only memory (
Electrically Erasable and
Programmable ROM) (hereinafter referred to as EE F
As one type of ROM (ROM), a nonvolatile memory having a floating gate structure in which writing and erasing are performed by tunneling injection is well known.

第3図は代表的なフローティングゲート構造の不揮発性
メモリを説明する構造断面図である。第3図において、
P型のシリコン基板1の中にN型拡散層からなるソース
2及びドレイン3が形成され、ソース2、ドレイン3に
またがって酸化シリコン膜4が形成されるとともに、こ
の酸化シリコン膜4の一部分のみを開孔し、この間孔部
にトネリング媒体となる薄い酸化シリコン膜5が形成さ
れ、酸化シリコン膜4,5の上にフローティングゲート
電極6、酸化シリコン膜7及びコントロールゲート電極
8が順次積層された構造である。この′ようなフローテ
ィングゲート構造を有する不揮発性メモリは、ドレイン
3の上の薄い酸化シリコン膜5を介して電荷のトネンリ
ングを行い、薄い酸化シリンコン膜5の−Lのフローテ
ィングゲート電極6に電荷を蓄積させ、トランジスタの
閾値電圧を変化させて情報を記憶させることを原理とし
ている。したがって、第3図に示すごとき不揮発性メモ
リの書き換え方法として、まずデータを消去する場合は
コントロールゲート電極8及びP型シリコン基板1の電
位をOv、ソース2をオープンにし、ドレイン3に高電
圧(通常15V〜25v)のパルスを印加して行ない、
一方データを書き込む場合はP型シリコン基板1及びド
レイン3をOv、ソース2をオープンとし、コントロー
ルゲート電極8に高電圧(通常15V〜25v)のパル
スを印加することにより行い1通常、上記の消去と書き
込みを交互に繰り返すことにより書き換えを行っている
FIG. 3 is a structural cross-sectional view illustrating a typical floating gate structure nonvolatile memory. In Figure 3,
A source 2 and a drain 3 made of N-type diffusion layers are formed in a P-type silicon substrate 1, and a silicon oxide film 4 is formed spanning the source 2 and drain 3, and only a portion of this silicon oxide film 4 is formed. A hole was opened, a thin silicon oxide film 5 serving as a tunneling medium was formed in the hole, and a floating gate electrode 6, a silicon oxide film 7, and a control gate electrode 8 were sequentially laminated on the silicon oxide films 4 and 5. It is a structure. A nonvolatile memory having such a floating gate structure performs charge tunneling through the thin silicon oxide film 5 on the drain 3, and stores charges in the -L floating gate electrode 6 of the thin silicon oxide film 5. The principle is to store information by changing the threshold voltage of the transistor. Therefore, as a method for rewriting a non-volatile memory as shown in FIG. This is done by applying a pulse (usually 15V to 25V),
On the other hand, when writing data, the P-type silicon substrate 1 and drain 3 are set to Ov, the source 2 is opened, and a pulse of high voltage (usually 15 V to 25 V) is applied to the control gate electrode 8. Rewriting is performed by alternately repeating and writing.

第4図は、上記従来の書き換え方法はよるメモリ特性の
劣化を示す特性図である。フローティングゲート構造の
半導体メモリは、消去と書き込みを繰り返して行った場
合、第4図に示す如く、通常メモリの窓幅(消去状態と
書き込み状態の閾値電圧の差ΔV th)が、書き換え
回数が〜10”回まで大きくなり、102回以1−にな
ると小さくなるといった現象を有する。また、繰り返し
の書き換え回数を増加させると10’〜10’回程度の
回数で破壊現象が起る。
FIG. 4 is a characteristic diagram showing the deterioration of memory characteristics caused by the conventional rewriting method. When a semiconductor memory with a floating gate structure is repeatedly erased and written, as shown in FIG. There is a phenomenon in which it increases up to 10'' times and decreases when it becomes 1- after 102 times.Furthermore, when the number of repeated rewrites is increased, a destructive phenomenon occurs at about 10' to 10' times.

(発明が解決しようとする課題) 」1記にのべた如く、フローティングゲート構造の半導
体メモリにおいては、上記従来の書き換え方法では繰り
返しの書き換え回数を増加させると劣化現象を有し、繰
り返しの書き換え回数が104〜lOs回程度になると
致命的な破壊現象が起こり、信頼性の問題を有していた
(Problems to be Solved by the Invention) As stated in Section 1, in the semiconductor memory with a floating gate structure, the conventional rewriting method described above has a deterioration phenomenon when the number of repeated rewrites is increased, and the number of repeated rewrites increases. When the number of times reaches approximately 104 to 1Os, a fatal destructive phenomenon occurs, which causes reliability problems.

本発明上記従来の問題を解決するものであり、フローテ
ィングゲート構造の半導体メモリの書き換え方法におい
て、書き換え回数の増加を容易に実現できる書き換え方
法を提供することを目的とするものである。
The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a rewriting method for a semiconductor memory having a floating gate structure that can easily increase the number of rewrites.

′(課題を解決するための手段) 本発明は上記目的を達成するために、フローティングゲ
ー1−構造を有する不揮発性メモリの書き換え方法にお
いて、一定回数の繰り返し書き換えを行った後に必ずベ
ーキングを施すものである。
(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for rewriting a non-volatile memory having a floating game structure, in which baking is always performed after repeatedly rewriting a certain number of times. It is.

(作 用) 検討によれば、繰り返し書き換え回数が102回程1ま
ではトンネル酸化膜中にホールが生成し、このホールが
実効トンネル電界を増加させるため、メモリ窓幅(ΔV
 th)が増大するものと考えられ、さらに繰り返し書
き換え回数が102回以−トになると、トンネル酸化膜
中に電子がトラップされるようになり、このためメモリ
窓幅が減少してゆき、最終的にトラップされた電子の電
荷により局部的に酸化シリコン膜の真性破壊が起こるも
のと推定される。また、トンネル酸化膜中にトラップさ
れた電子は、100℃以上の温度でベークすると容易に
放出できることがわかった。したがって、電子のトラッ
ピングによりトンネル酸化膜の真性破壊が起る前にベー
キングを行うことにより、トラップされた電子を放出す
る作用を有し繰り返し書き換え回数を増大させる効果を
有する。
(Function) According to the study, holes are generated in the tunnel oxide film until the number of repeated rewrites is about 102, and these holes increase the effective tunnel electric field, so the memory window width (ΔV
th) is thought to increase, and when the number of repeated rewrites exceeds 102, electrons will become trapped in the tunnel oxide film, which will reduce the memory window width and eventually It is presumed that intrinsic destruction of the silicon oxide film occurs locally due to the charge of the trapped electrons. It was also found that electrons trapped in the tunnel oxide film can be easily released by baking at a temperature of 100° C. or higher. Therefore, by performing baking before the tunnel oxide film undergoes intrinsic destruction due to electron trapping, it has the effect of releasing the trapped electrons and increasing the number of repeated rewrites.

(実施例) 第1図は本発明の一実施例の不揮発性メモリの書き換え
方法を示す図である。第1図により書き換え方法を説明
する。第3図に示したごときフローティングゲート型の
不揮発性メモリをパッケージに組み立てた状態で、通常
の書き換え方法(上記従来の書き換え方法)による10
″′回まで書き換えを行う。次いで、200℃のベーク
炉の中にパッケージ状態のままで約5時間放置する。そ
の後べ一り炉から出し通常の書き換え方法により10’
回の書き換えを行い、その後再度ベーキングを行うとい
った繰り返しにより書き換えを行う。
(Embodiment) FIG. 1 is a diagram showing a method for rewriting a nonvolatile memory according to an embodiment of the present invention. The rewriting method will be explained with reference to FIG. With the floating gate type non-volatile memory as shown in Figure 3 assembled into a package, the normal rewriting method (the conventional rewriting method described above) is performed.
Rewriting is performed up to ``'' times.Next, the package is left in a baking oven at 200°C for about 5 hours.Then, it is removed from the baking oven and rewritten in the usual way for 10'.
Rewriting is performed repeatedly, such as rewriting once and then baking again.

第2図は、上記第1図の示す書き換え方法によるメモリ
の劣化特性を示したものである。第2図において、縦軸
は閾値電圧、横軸は繰り返し書き換え回数を示しており
、10’回書き換えごとにベーキングを行うことにより
、はぼ初期の閾値電圧まで回復するため、10’回書き
換えを行ってもメモリの破壊は起こらず、書き換え回数
の著しい増加を実現できることがわかる。
FIG. 2 shows the deterioration characteristics of the memory according to the rewriting method shown in FIG. 1 above. In Figure 2, the vertical axis shows the threshold voltage, and the horizontal axis shows the number of repeated rewrites. By performing baking every 10' rewrites, the voltage is restored to the initial threshold voltage, so the 10' rewrites are performed. It can be seen that even if this is done, the memory will not be destroyed and the number of rewrites can be significantly increased.

また、本発明の効果が十分得られるベーク温度について
は、100℃以上の温度で顕著な効果が得られ、ベーク
時間については、200℃程度の温度だと3〜5時間で
十分な効果が得られる。一方、ベーキングとベーキング
の間の書き換え回数については、真性破壊が起こらない
程度の回数にする必要から10s回以下の回数が望まし
い。
Regarding the baking temperature at which the effects of the present invention can be sufficiently obtained, a remarkable effect can be obtained at a temperature of 100°C or higher, and regarding the baking time, a sufficient effect can be obtained in 3 to 5 hours at a temperature of about 200°C. It will be done. On the other hand, the number of times of rewriting between baking is desirably 10 seconds or less because it is necessary to keep the number of times to a level that does not cause true destruction.

なお、本実施例ではベーク方法として通常のベーク炉を
用いる方法を示したが、パッケージの中にヒータを埋め
込みそれで加熱する方法など、メモリチップが加熱でき
る方法であればどんな方法でもよいことは言うまでもな
い。
In this example, a method using a normal baking oven was shown as the baking method, but it goes without saying that any method that can heat the memory chip may be used, such as a method of embedding a heater in the package to heat it. stomach.

(発明の効果) 本発明は上記の実施例から明らかなように、書き換え回
数の大幅な増加が容易に実現でき、フローティングゲー
ト構造の半導体メモリの信頼性の向」―に大きな効果を
有する6
(Effects of the Invention) As is clear from the above embodiments, the present invention can easily realize a significant increase in the number of rewrites and has a great effect on improving the reliability of floating gate structure semiconductor memories.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の処理方法を示す図、第2図
は本発明の一実施例の効果を示す劣化特性図、第3図は
フローティングゲ−1・構造の不揮発性メモリの概略的
な構造断面図、第4図は従来の書き換え方法によるメモ
リの劣化特性図である。 1 ・・ P型シリコン基板、 2 ・・・ソース、3
 ・・・ ドレイン、 4,7 ・・・酸化シリコン膜
、 5 ・・・ トネンリング媒体となる薄い酸化シリ
コン膜、 6 ・・・ フローティングゲート電極、 
8 ・・コントロールゲート電極。 特許出願人 松下電子工業株式会社 第 図 第3図 第2図 ° P型−/1ノフン差4反 2  ソース       3・・・ドシにン飯化シリ
コン臘 トンキ゛ルク゛棒系もしなる簿(゛醸化シ・)つ替良フ
リー角ンク゛デートψJ女 つントυ−lレケ゛−トギ」岳
Fig. 1 is a diagram showing a processing method according to an embodiment of the present invention, Fig. 2 is a deterioration characteristic diagram showing the effect of an embodiment of the present invention, and Fig. 3 is a diagram showing a nonvolatile memory having a floating gate 1 structure. FIG. 4, which is a schematic cross-sectional view of the structure, is a diagram showing the deterioration characteristics of a memory according to a conventional rewriting method. 1...P-type silicon substrate, 2...source, 3
... Drain, 4, 7 ... Silicon oxide film, 5 ... Thin silicon oxide film serving as a tunneling medium, 6 ... Floating gate electrode,
8...Control gate electrode. Patent applicant: Matsushita Electronics Co., Ltd. Figure 3 Figure 2 ° P type - / 1 nofun difference 4 anti 2 Source 3... A list of doshin hyalurized silicon tonkis and rods. shi・)tsugae good free angle date

Claims (3)

【特許請求の範囲】[Claims] (1)フローティングゲート構造を有する不揮発性メモ
リの書き換え方法において、一定回数の繰り返し書き換
えを行った後に必ずベーキングを施すことを特徴とする
不揮発性メモリの書き換え方法。
(1) A method for rewriting a nonvolatile memory having a floating gate structure, which comprises always performing baking after repeatedly rewriting a certain number of times.
(2)ベーキングの温度が100℃以上であることを特
徴とする請求項(1)記載の不揮発性メモリの書き換え
方法。
(2) The nonvolatile memory rewriting method according to claim (1), wherein the baking temperature is 100° C. or higher.
(3)一定回数の書き換え回数が10^S回以下である
ことを特徴とする請求項(1)または(2)記載の不揮
発性メモリの書き換え方法。
(3) The method of rewriting a nonvolatile memory according to claim 1 or 2, wherein the number of times of rewriting the fixed number of times is 10^S times or less.
JP15238988A 1988-06-22 1988-06-22 Rewriting method of tunnel injection type nonvolatile memory Expired - Lifetime JP2745131B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15238988A JP2745131B2 (en) 1988-06-22 1988-06-22 Rewriting method of tunnel injection type nonvolatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15238988A JP2745131B2 (en) 1988-06-22 1988-06-22 Rewriting method of tunnel injection type nonvolatile memory

Publications (2)

Publication Number Publication Date
JPH023981A true JPH023981A (en) 1990-01-09
JP2745131B2 JP2745131B2 (en) 1998-04-28

Family

ID=15539447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15238988A Expired - Lifetime JP2745131B2 (en) 1988-06-22 1988-06-22 Rewriting method of tunnel injection type nonvolatile memory

Country Status (1)

Country Link
JP (1) JP2745131B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04315476A (en) * 1991-04-15 1992-11-06 Nippondenso Co Ltd Method for reducing trap density in oxide film and method for manufacturing semiconductor device
US7817477B2 (en) 2007-03-30 2010-10-19 Oki Semiconductor Co., Ltd. Manufacturing method, remanufacturing method and reshipping method for a semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04315476A (en) * 1991-04-15 1992-11-06 Nippondenso Co Ltd Method for reducing trap density in oxide film and method for manufacturing semiconductor device
US7817477B2 (en) 2007-03-30 2010-10-19 Oki Semiconductor Co., Ltd. Manufacturing method, remanufacturing method and reshipping method for a semiconductor memory device

Also Published As

Publication number Publication date
JP2745131B2 (en) 1998-04-28

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