JP5422886B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semi-conductor device rewritable in cell structure of the first layer polysilicon which can be produced by standard CMOS (complementary metal-oxide semiconductor) process.

  Nonvolatile semiconductor memories represented by EEPROM (Electrically Erasable Programmable Read Only Memory) have been used in many applications because information is not lost even when the power is turned off. For example, a typical application of an EEPROM is an IC card. Also, EEPROM and flash memory are used as a replacement for the mask ROM in the microcomputer because it can be rewritten at any time according to the application. Furthermore, in recent years, there has been a need for a so-called embedded logic memory (embedded type) in which a nonvolatile semiconductor memory is incorporated in a part of a system LSI or logic IC. Furthermore, a small-sized non-volatile semiconductor memory of about several hundred bits to several K bits is also required as an adjustment switch that is incorporated in an analog circuit and performs tuning and the like of a high-precision analog circuit.

  However, a non-volatile semiconductor memory generally has a cell structure using two-layer polysilicon or three-layer polysilicon, and the manufacturing process is more complicated and requires more manufacturing processes than the standard CMOS logic process. Attempting to embed them in the chip at the same time has caused many problems in the manufacturing process, yield decreases, and the product price (cost) increases.

As one means for solving this problem, an EEPROM using one-layer polysilicon has been proposed. (Patent Document 1). If this one-layer polysilicon EEPROM is used, the number of manufacturing steps can be reduced as compared with the conventional two-layer polysilicon process.
JP-A-10-289959

  However, in the above technique, since the second-layer polysilicon used as the control gate is omitted, it is necessary to embed a control gate made of a diffusion layer under the floating gate, which is more complicated than the standard CMOS process used in logic. It becomes a difficult manufacturing process. Furthermore, if the diffusion layer embedded at a high concentration is oxidized, an oxide film of poor quality is formed, and the probability of occurrence of a defect is high, and reliability is also a problem. In addition, writing and erasing are complicated, such as requiring a high voltage for writing.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semi-conductor device of the cell structure of the first layer polysilicon which can be produced in a standard CMOS process.

In order to solve the above-mentioned problem, the invention described in claim 1 is characterized in that a first transistor comprising a floating gate, a drain and a source formed on a semiconductor substrate is connected in series with the first transistor and is turned on or off. A non-volatile semiconductor memory element comprising a second transistor that controls selection or non-selection of the first transistor, wherein the second transistor is turned on and the source / drain of the first transistor is turned on A voltage is applied between them to inject and accumulate charges in the floating gate, and at the time of erasing the charges accumulated in the floating gate of the first transistor, the semiconductor substrate and the drain or source of the first transistor A voltage is applied between them to create hot holes between the bands. A plurality of non-volatile semiconductor memory devices configured to erase charges accumulated in the floating gate by the hot holes, and a plurality of the first array arranged in a row and column direction; A plurality of source lines for connecting the sources of the transistors for each row, a plurality of row lines for connecting the gates of the plurality of second transistors for each row, and a drain for the plurality of second transistors for each column A plurality of bit lines, a plurality of transistors connected to each bit line by selecting a plurality of column lines by selecting a plurality of column lines, and a row line selection for selecting the row lines Means, a voltage applying means for applying a predetermined voltage to the bit line selected by the column line selecting means, and the column line selecting means and the row line selecting means. And a reading means for reading the state of charge accumulated in the floating gate of the nonvolatile semiconductor memory device, wherein the same at the time of erasing the time of writing the voltage to be applied to the source line, first of the nonvolatile semiconductor memory element during writing A voltage is applied between the bit line connected to the drain of the second transistor and the source line connected to the source of the first transistor, and connected to the drain of the second transistor of the nonvolatile semiconductor memory element at the time of erasing A voltage is applied between the semiconductor substrate and the source line connected to the source of the first transistor with the bit line opened .
According to a second aspect of the present invention, in the first transistor configuration of the nonvolatile semiconductor memory element, a ratio between the capacitance between the floating gate and the source or the drain and the capacitance between the floating gate and the channel is 1: 8 is a feature.

According to a third aspect of the present invention, a first transistor comprising a floating gate, a drain and a source formed on a semiconductor substrate is connected in series with the first transistor, and the first transistor is turned on or off. And a second transistor that controls selection or non-selection of the first transistor, wherein the second transistor is turned on and a voltage is applied between the source and drain of the first transistor. Injecting charge into the floating gate and storing it, and at the time of erasing the charge stored in the floating gate of the first transistor, applying a voltage between the semiconductor substrate and the drain or source of the first transistor, Hot holes between bands are generated in the semiconductor substrate, and the hot holes A matrix array in which a plurality of nonvolatile semiconductor memory elements configured to erase charges accumulated in the floating gate are arranged in a row and column direction, and a source of the plurality of first transistors for each column. A plurality of source lines connected to each other; a plurality of row lines connecting the gates of the plurality of second transistors for each row; a plurality of bit lines connecting the drains of the plurality of second transistors for each column; Selecting a plurality of transistors connected to each source line and each bit line by a plurality of column lines to select each source line and each bit line; and selecting the row line Row line selection means for applying a voltage to a source line and a bit line selected by the column line selection means, and the column line selection means and the row line selection. And a reading means for reading the state of charge accumulated in the floating gate of the nonvolatile semiconductor memory device selected by means at the time of write, the second connected bit to the drain of the transistor of the nonvolatile semiconductor memory device A predetermined write voltage is applied to the line, a source line connected to the source of the first transistor is grounded, and a voltage is applied between the drain of the second transistor and the source of the first transistor And applying a predetermined erasing voltage to the bit line connected to the drain of the second transistor of the nonvolatile semiconductor memory element during erasing, and opening the source line connected to the source of the first transistor, A voltage is applied between the drain of the first transistor and the semiconductor substrate .
According to a fourth aspect of the present invention, in the first transistor configuration of the nonvolatile semiconductor memory element, a ratio between a capacitance between the floating gate and the source or the drain and a capacitance between the floating gate and the channel is 1: 8 is a feature.

According to the present invention, a semiconductor device including a nonvolatile semiconductor memory element in the standard logic CMOS process can be realized, the logic embedded memory easily, also can be realized inexpensively.

Embodiments of the present invention will be described below with reference to the drawings.
[Embodiment 1]
FIG. 1A is a plan view of one transistor constituting a nonvolatile semiconductor memory element according to an embodiment of the present invention, FIG. 1B is a sectional view, and FIG. 1C is an equivalent circuit diagram. Show. 1A to 1C includes a floating gate FG, a drain D, and a source S formed on a semiconductor substrate SUB (potential Vsub) using a single-layer polysilicon cell structure. Composed. This floating gate FG serves as a charge holding region, no electrode is provided, and a floating gate FG made of polysilicon is formed on a gate insulating layer formed on the substrate SUB. The drain D and the source S are diffusion regions formed on the substrate SUB, and electrodes are provided through contacts.

  FIG. 2 shows an equivalent circuit of the coupling system of the nonvolatile semiconductor memory element shown in FIG. If there is a charge Q in the floating gate FG, the total charge of this system is Q.

It becomes. However, VFG, VD, VS, and Vch are the potential of the floating gate FG, the potential of the drain D, the potential of the source S, and the potential of the channel CH, respectively. C (FB) is a capacitance between the floating gate FG and the substrate SUB, C (FD) is a capacitance between the floating gate FG and the drain D, C (FS) is a capacitance between the floating gate FG and the source S, and C (FC ) Is a capacitance between the floating gate FG and the channel CH. Here, when C (FB) + C (FD) + C (FS) + C (FC) = CT (total),

It becomes. However, Q / CT represents a potential when charge is injected into the floating gate. Here, when Vsub = 0V (reference potential, the same applies hereinafter),

It becomes. Here, the ratio of the capacities varies somewhat depending on the process, but is roughly about C (FD): C (FS): C (FC) = 0.1: 0.1: 0.8. Here, if the charge amount in the floating gate FG is Q · CT = −ΔVFG, CT = 1

It becomes.

  Here, erasing of the nonvolatile semiconductor memory device of FIG. 1 will be described. The threshold value of the channel CH of the transistor constituting this nonvolatile semiconductor memory element is 0.5V. Erasing is performed with VD = 8V and VS = open (open). Since the source is open, a depletion layer spreads in the channel CH portion of this transistor, and the capacitance between the floating gate FG and the substrate SUB becomes very small. If neglected, the floating gate potential VGF (Erase) at the time of erasing is ΔVFG = 0,

It becomes. When a voltage is applied to the drain D, as shown in FIG. 4, first, an electric field concentration in the depletion layer occurs in the vicinity of the drain D, and a so-called high energy band-to-band (BtoB) current flows, so that holes and electrons The pair occurs. When some holes with high energy (hot holes) are taken into the floating gate FG and the voltage is further increased, if the oxide film is relatively thick, the Fowler-Nordheim tunnel current flows before A junction breakdown occurs and a large current flows through the substrate SUB. This breakdown voltage is assumed to be VBD.

  For details of the band-to-band (BtoB) current, refer to “Reference:“ Flash Memory Technology Handbook ”, Editor: Fujio Takaoka, Publisher: Science Forum, Inc., August 15, 1993, first edition, first edition issued. See Chapter 5, Section 2, Analysis of Band-to-Band Tunneling in Non-volatile Memory Cells, P206-215. FIG. 4 schematically shows the change in the drain current ID when the drain potential VD is changed with the drain potential VD and the vertical axis as the drain potential VD, with the floating gate potential VFG as a parameter. .

  Here, since BtoB and breakdown occur in a certain electric field, it depends on the potential of the floating gate FG. As shown in FIG. 4, when VFG is low, VBD is also low, and when VFG is high, VBD is high.

  Consider erasure. If the limit potential of the potential difference between the gate and drain where BtoB occurs is 5V, when VD = 8V, the floating gate potential VFG is erased until it reaches 3V, in other words, hot holes are injected. At the time of erasing, since the source S is opened, VS is almost 0V and the channel is also turned off. Therefore, if the channel potential Vch is also almost 0V, ΔVFG = 0V in the initial state. 2) is derived. Since the initial VFG is 0.8V, when it becomes 3V after erasure, the change amount ΔVFG (E) at the time of erasure becomes + 2.2V.

  On the other hand, writing is performed with VD = 5V and VS = 0V. At this time, if the state before writing is a normal erasing state and a hole is in the floating gate FG, this transistor is in an on state, so that the channel operates in the saturation region. Accordingly, since the actual coupling area between the channel and the gate is usually about half, the floating gate potential VGF (Program) at the time of writing is calculated from (Equation 1):

Since the gate voltage is about 2.5 V, the channel is turned on, an excessive current flows, hot electrons are generated, and writing is performed. Here, since the threshold value of this transistor is 0.5V, when the potential VFG of the floating gate FG becomes 0.5V, no current flows and writing is completed. At this time, since the gate voltage changes from 2.5V to 0.5V, the change amount ΔVFG (P) at the time of writing becomes −2.0V.

  FIG. 3 shows the transistor characteristics in the erased and written states. FIG. 3 schematically shows changes in the gate current ID when the floating gate potential VFG is changed in three states of erasure, neutrality, and writing, where the horizontal axis is the floating gate potential VFG and the vertical axis is the current ID of the drain D. It is a representation.

  Next, reading will be described. Reading is performed with VD = 1V and VS = 0V. At this time, if the charge of ΔVFG is in the floating gate FG, the floating gate potential VGF (Read) at the time of reading is

It becomes. In the case of “0” reading, electrons are injected by −Δ2.0 V into the floating gate FG at the time of writing. Therefore, from (Equation 3), the floating gate potential VFG (“0”) at the time of “0” reading is ,

It becomes. On the other hand, in the case of “1” reading, since a hole is included in the floating gate FG by Δ2.2V at the time of erasing, the floating gate potential VFG (“1”) at the time of “1” reading is ,

It becomes. FIG. 5 summarizes the operation of this nonvolatile semiconductor memory element. Note that the operations of the drain and the source can be reversed.

[Embodiment 2]
FIG. 6 shows an application example of the first embodiment described with reference to FIG. FIG. 6A is a plan view of a nonvolatile semiconductor memory element (hereinafter also referred to as a memory cell) of this embodiment, and FIG. 6B shows an equivalent circuit. A floating gate transistor 1 having the same floating gate as the transistor shown in FIG. 1 and a select transistor 2 for selecting or deselecting the floating gate transistor 1 are connected in series. By controlling the potential of the gate (referred to as a select gate) SG of the select transistor 2, the selection or non-selection of the floating gate transistor 1 constituting this nonvolatile semiconductor memory element is determined. The drain of the select transistor 2 is the D terminal, the source of the floating gate transistor 1 is the S terminal, the gate potential of the select transistor 2 is VSG, the potential of the D terminal is VD, and the potential of the S terminal is VS. FIG. 7 shows operations when “0” reading, “1” reading, and transistor 1 are not selected. When selected, for example, 10 V is applied to the select gate SG at the time of writing and erasing, and 3 V is applied at the time of reading to sufficiently turn on the transistor 2. The basic operation is the same as in FIG. If not selected, SG is set to 0V.

[Embodiment 3]
FIG. 8 shows an embodiment in which the nonvolatile semiconductor memory element of FIG. 6 is configured in a memory array. M11 is one nonvolatile semiconductor memory element configured by connecting the floating gate transistor 1 and the select transistor 2 of FIG. 6 in series. Reference numeral 100 denotes a matrix array composed of m × n nonvolatile semiconductor memory elements similar to M11. The drains of the select transistors 2 of the nonvolatile semiconductor memory elements M11 to Mmn are connected to the bit lines Bit1 to Bitn, and the sources of all the floating gate transistors 1 are connected to the common source S. The select gate of each select transistor 2 is connected to the outputs WL1 to WLm of the row decoder 300. 200 is a column gate that selects Bit1 to Bitn by transistors 201 to 20n, 300 is a row decoder that selects row lines WL1 to WLm, and 400 is a column decoder that selects each transistor 201 to 20n of the column gate 200 by column lines C1 to Cn. A column decoder 500 is a write / erase control circuit that writes data to the data line Data according to the input data Din and applies an erase voltage, and 600 is for reading data from the nonvolatile semiconductor memory elements M11 to Mmn appearing on the data line Data. And outputs data Dout of each memory cell of the nonvolatile semiconductor memory elements M11 to Mmn.

  The operation is shown in FIG. FIG. 9 shows the operation state of the selected cell (here, M11). Row line WL1 and column line C1 are selected and 7V is applied. When 5V is applied to the Data line, 5V is also applied to the bit line Bit1 and therefore 5V is also applied to the drain D of the memory cell M11, and the source S is 0V, so that M11 is in a writing state and writing is performed.

  On the other hand, at the time of erasing, if 10V is applied to WL1 and C1 and 8V is applied to Data, Bit1 is 8V, 8V is applied to the drain D of the memory cell of M11, and the source S is open. Then, erasure is performed. At this time, when a row or a column is not selected, no voltage is applied to the floating gate transistor 1, and thus writing and erasing do not occur.

  As a merit of this method, bit writing and page writing are possible for writing, and bit erasing, page erasing and batch erasing are possible for erasing. In the case of page erase, the column lines C1 to Cn are simultaneously selected. In the case of batch erasure of the entire matrix array 100, all the column lines C1 to Cn and the row lines WL1 to WLm are simultaneously selected.

  FIG. 10 shows another method of operating the memory array shown in FIG. This is an example in which a voltage is applied to the common source S side. For writing, 3 V is applied to the selected WL1 and C1, and 0 V is applied to the Data line. At this time, when 5 V is applied to S, a current flows through M11, and hot electron writing occurs in the memory cell. In the non-selected cells (M12 to Mmn), the row lines WL (WL2 to WLm) and the column lines C (C2 to Cn) are turned off at 0 V, so that no current flows to the memory cells (M12 to Mmn) and writing is performed. Does not happen.

  As for erasing, since the source S is common, all the memory cells M11 to Mmn are simultaneously erased, so-called batch erasing of the flash memory is performed. Of course, if the memory array 100 is divided into a plurality of blocks, block erasing is possible. In this way, erasing is only block erasing or batch erasing, but the configuration of the row decoder 300 and the column decoder 400 can be configured with low voltage transistors, so that the area can be reduced. The writing can be bit writing or page writing.

[Embodiment 4]
FIG. 11 shows still another embodiment. The source S of the embodiment of FIG. 8 is separated in the row direction into source lines S1 to Sm. That is, in this embodiment, a matrix array 100a is used in which the sources of the memory cells M11 to Mmn are separated into the source lines S1 to Sm for each row with respect to the matrix array 100 of FIG. FIG. 12 shows the operation.

  In this configuration, in the configuration of FIG. 8, in the case of the operation of FIG. 10, only block erase or batch erase can be performed, and page erase is possible. For example, for each of the memory cells M11 to M1n connected to the same source line S1, if the source voltage S1 at the time of writing and the source voltage S1 at the time of erasing are set to the same 8V, the writing operation and the erasing operation of FIG. Can be done. That is, for example, when writing to the memory cell M11, erasing the memory cell M12, writing to the memory cell M13 (not shown)... Simultaneously, C1 = 3V, C2 = 0V, C3 = 3V,. Thus, if the output of the column decoder 400 is selected according to the input information of Din, writing and erasing can be performed simultaneously.

[Embodiment 5]
FIG. 13 shows another embodiment in which writing and erasing can be performed simultaneously by modifying the embodiment 3 shown in FIG. In this embodiment, a matrix array 100b is used in which the sources of the memory cells M11 to Mmn are separated into columns to form source lines S1 to Sn with respect to the matrix array 100 of FIG. In addition, the column gate 200b of this embodiment includes transistors 711, 712,... 71n for connecting / disconnecting the source lines S1, S2,..., Sn and VS lines, and bit lines Bit1, Bit2,. , 72n for connecting / disconnecting Bitn and VE line, and transistors 731, 732, for connecting / disconnecting Bitn and VW / R line to each bit line Bit1, Bit2,. 73n.

  Further, in order to give different voltages to the bit lines (Bit1 to Bitn) by writing and erasing, the transistor decoders 731, 732,... 73n, transistors 721, 722, .., 72n, write column selection lines CW / R1 to CW / Rn selected at the time of write control and reading, and erase column selection lines CE1 to CEn selected at the time of erasure in order to control the transistors 711, 712,. Source column selection lines CS1 to CSn for selecting source lines S1 to Sn are provided. The column voltage control circuit 500b outputs VW / R for applying a write voltage and a read bias voltage, VE for applying an erase voltage, and VS for applying a source voltage. In the above configuration, the column decoder 400b and the column voltage control circuit 500b operate by determining whether to write or erase in response to the Din signal.

  FIG. 14 shows the operation. For example, when the memory cell M11 is set to the write mode, Din = “0”, CS1 becomes 3V, CE1 becomes 0V, CW / R1 becomes 7V, Bit1 becomes VW / R = 5V, and source S1 becomes VS = 0V. Since WL1 becomes 10V, M11 is written.

  On the other hand, when the memory cell M11 enters the erase mode, Din = “1”, CS1 = 0V, CE1 = 10V, CW / R1 = 0V, VE = 8V, Bit1 = 8V, S1 = open, and M11 is erased. The In this way, writing and erasing of each memory cell selected by the same row line WL are performed simultaneously.

  The difference from the fourth embodiment is that the voltage of the Bit line can be set to an optimum voltage for writing (5 V) and erasing (8 V).

  As described above, according to each embodiment of the present invention, a nonvolatile semiconductor memory (that is, a nonvolatile semiconductor memory element and a semiconductor device using the same) can be realized by a standard logic CMOS process. Therefore, by mounting the nonvolatile semiconductor memory of the present invention on the standard logic, a logic embedded memory can be realized easily and inexpensively.

It is a figure which shows the structure of embodiment (Embodiment 1) of the non-volatile semiconductor memory element by this invention. It is a figure which shows the equalization circuit of embodiment of FIG. It is a figure for demonstrating the characteristic of embodiment of FIG. It is a figure for demonstrating the other characteristic of embodiment of FIG. It is a figure for demonstrating the operation | movement of embodiment of FIG. It is a figure which shows the structure of embodiment (Embodiment 2) as an application example of the non-volatile semiconductor memory element of FIG. It is a figure for demonstrating the operation | movement of embodiment of FIG. It is a figure which shows embodiment (Embodiment 3) at the time of comprising a matrix array using embodiment of FIG. It is a figure for demonstrating the operation | movement of embodiment of FIG. It is a figure for demonstrating the other operation | movement of embodiment of FIG. It is a figure which shows the structure of embodiment (Embodiment 4) as a modification of embodiment of FIG. It is a figure for demonstrating the operation | movement of embodiment of FIG. It is a figure which shows the structure of embodiment (Embodiment 5) as another modification of embodiment of FIG. It is a figure for demonstrating the operation | movement of embodiment of FIG.

Explanation of symbols

D ... Drain S ... Source FG ... Floating gate SG ... Select gates M11-Mmn ... Non-volatile semiconductor memory elements (memory cells)
DESCRIPTION OF SYMBOLS 1 ... Floating gate transistor 2 ... Select transistor 100, 100a, 100b ... Matrix array 200, 200b ... Column gate 300 ... Row decoder 400, 400b ... Column decoder 500 ... Write / erase control circuit 500b ... Column voltage control circuit

Claims (4)

A first transistor including a floating gate, a drain, and a source formed on a semiconductor substrate and connected in series with the first transistor, and controls selection or non-selection of the first transistor by turning on or off. A non-volatile semiconductor memory device comprising a second transistor,
With the second transistor turned on, a voltage is applied between the source and drain of the first transistor to inject charges into the floating gate and accumulate,
When erasing charges accumulated in the floating gate of the first transistor, a voltage is applied between the semiconductor substrate and the drain or source of the first transistor, and hot holes due to band-to-band are formed in the semiconductor substrate. A matrix array in which a plurality of nonvolatile semiconductor memory elements configured to generate and erase charges accumulated in the floating gate by the hot holes are arranged in a row and column direction;
A plurality of source lines connecting the sources of the plurality of first transistors for each row;
A plurality of row lines connecting the gates of the plurality of second transistors for each row;
A plurality of bit lines connecting the drains of the plurality of second transistors for each column;
Column line selection means for selecting each bit line by selecting a plurality of transistors connected to each bit line by a plurality of column lines;
A row line selection means for selecting the row line;
Voltage applying means for applying a predetermined voltage to the bit line selected by the column line selecting means;
Read means for reading out the state of the charge accumulated in the floating gate of the nonvolatile semiconductor memory element selected by the column line selection means and the row line selection means,
The voltage applied to the source line is the same during writing and erasing, and the bit line connected to the drain of the second transistor of the nonvolatile semiconductor memory element and the source connected to the source of the first transistor during writing The semiconductor substrate and the source line connected to the source of the first transistor by applying a voltage between the line and opening the bit line connected to the drain of the second transistor of the nonvolatile semiconductor memory element at the time of erasing A semiconductor device characterized by applying a voltage between them. In the first transistor configuration of the nonvolatile semiconductor memory element, a ratio of a capacitance between the floating gate and the source or the drain and a capacitance between the floating gate and the channel is 1 : 8. The semiconductor device according to claim 1. A first transistor including a floating gate, a drain, and a source formed on a semiconductor substrate and connected in series with the first transistor, and controls selection or non-selection of the first transistor by turning on or off. A non-volatile semiconductor memory device comprising a second transistor,
With the second transistor turned on, a voltage is applied between the source and drain of the first transistor to inject charges into the floating gate and accumulate,
When erasing charges accumulated in the floating gate of the first transistor, a voltage is applied between the semiconductor substrate and the drain or source of the first transistor, and hot holes due to band-to-band are formed in the semiconductor substrate. A matrix array in which a plurality of nonvolatile semiconductor memory elements configured to generate and erase charges accumulated in the floating gate by the hot holes are arranged in a row and column direction;
A plurality of source lines connecting the sources of the plurality of first transistors for each column;
A plurality of row lines connecting the gates of the plurality of second transistors for each row;
A plurality of bit lines connecting the drains of the plurality of second transistors for each column;
Column line selection means for selecting each source line and each bit line by selecting a plurality of transistors connected to each source line and each bit line by a plurality of column lines;
A row line selection means for selecting the row line;
Voltage applying means for applying a predetermined voltage to the source line and the bit line selected by the column line selecting means;
Read means for reading out the state of the charge accumulated in the floating gate of the nonvolatile semiconductor memory element selected by the column line selection means and the row line selection means,
At the time of writing, a predetermined write voltage is applied to the bit line connected to the drain of the second transistor of the nonvolatile semiconductor memory element, the source line connected to the source of the first transistor is grounded, A voltage is applied between the drain of the second transistor and the source of the first transistor, and a predetermined erase is applied to the bit line connected to the drain of the second transistor of the nonvolatile semiconductor memory element at the time of erasing. A voltage is applied, a source line connected to the source of the first transistor is opened, and a voltage is applied between the drain of the first transistor and the semiconductor substrate.
Semiconductor device comprising a call. In the first transistor configuration of the nonvolatile semiconductor memory element, a ratio of a capacitance between the floating gate and the source or the drain and a capacitance between the floating gate and the channel is 1 : 8. The semiconductor device according to claim 3.

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