JPH0194470A - Digital processing system - Google Patents

Abstract

PURPOSE: To process lots of data to process a video image efficiently by allowing a master control means to send a control signal along a control bus so as to control operations of plural modules and allowing each module to connect its communication means to one or more data buses in response thereto. CONSTITUTION: Plural digital modules 34, 36, 38a, 38b, 38c, 40 are communicated with each other via plural data buses 42, a master controller 30 gives a control signal along a control bus 32 to control the operation of any of the plural digital modules 34, 36, 38a, 38b, 38c, 40. Each of the digital modules 34, 36, 38a, 38b, 38c, 40 is provided with a communication means and a logic device means and each communication means is connected to one or more data buses 42 in response to a control signal of the control bus 32. Thus, lots of data relating to image processing are processed.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a digital processing system having multiple data buses, and more specifically, to a digital processing system having multiple data buses, and more specifically, to a digital processing system having multiple processor modules, multiple memory modules, and multiple memory modules. The present invention relates to a video image processing apparatus for processing video images having a plurality of data buses interconnecting memory modules and processor modules.

Prior art digital processing devices are well known. This can be used for various purposes. One purpose is to process video images. Typically, video images are provided from an analog source such as a video camera. Digitizes an analog video signal from a video source. The digitized video images are stored in digital memory and processed by a digital processing device.

Since the video image that the invention seeks to understand consists of a large number of pixels or video image points, the amount of data that the video processing device must process is large. To date, there is no video processing device that addresses the problem of handling large amounts of data related to image processing.

U.S. Patent No. 4.542.455, U.S. Patent No. 4,503,5
No. 11, No. 4.594.655, No. 4,327,
355, 4, 346.438 and 4.46
No. 7,409 generally describes digital processing V;ti. Although U.S. Pat. No. 4,467.409 describes a flexible computer φ architecture, it does not address the specific problem of efficiently processing fat data, especially when processing video images. It is not mentioned.

to solve problems This invention describes a digital processing system.

The system has multiple digital electronic modules. Each module has a means of communication. Modules process and store data.

Multiple data buses interconnect the multiple modules. Each data bus has multiple communication paths. A master control means is connected to a control bus, which control bus has a plurality of communication paths. A control bus interconnects the master control means with one module each. A master control means controls the operation of the plurality of modules by sending Ill III signals along the control bus.

Each module has means for connecting its communication means to one or more data buses in response to control signals from the control bus.

Embodiment FIG. 1 shows an image forming device (8) using the video image processing device (10) of the present invention. The image forming device (8) is
It has a video image processing unit M (1G) which receives an analog video signal from a color camera (12).

The color camera (12) is optically attached to a fluorescent illuminator I (14), which illuminates the microscope (16).
) and facing the stage (18). An illumination source (20) provides the necessary electromagnetic radiation. A video image processing device f (1G) communicates with a host computer (22). In addition, the host command computer (
22) includes software (24) to operate it.
) is memorized. Finally, a full-color monitor display [(2
B) receives the output of video processing device f(1G).

There are many uses for video image processing equipment W (1G). In the embodiment shown in FIG. 1, an imaging device f(8) is used to analyze a physiological specimen, such as the components of blood. The physiological specimen is mounted on a slide and placed on the stage (18). A video image of the slide viewed by a color camera (12) through a microscope 1 (16) is processed by the video image processing device (12) of the present invention.
10).

In the preferred embodiment, the host computer (22) is a Motlow 2.68000 microprocessor, Q
Video image processing device of this invention via bus! (1G)
contact. QBus is a standard communication protocol developed by Digital Equipment Corporation.

As shown in FIG. 2, a video image processing device (10) includes a master controller (30) and a plurality of electronic digital modules. FIG. 2 shows a plurality of processor modules, namely a video processor (34), a graphics control processor (36), and a format processor (40).
, a plurality of image memory modules (38a), (38b), (38c) are shown. An image memory module stores data representing video images. A processor module processes the data or video images. Master controller (30) connects multiple digital modules (34, 36, 38, 40)
via a control bus (32).

Furthermore, a plurality of digital modules (34, 36,
38, 40) communicate with each other via a plurality of data buses (42).

In the video image processing device (10) of the present invention, a master controller (30) controls a plurality of digital modules (34, 36, 38, 40). The bus (32) has multiple lines. Bus (32)
has 8 bit lines for address, 16 bit lines for data, 4 bit lines for control, one line for vertical synchronization, and one line for horizontal synchronization. Additionally, there are numerous power lines and ground lines. 4 bits of control are clock, 80A
V, C) 10 and RT (the function of these control signals will be explained later).

The plurality of data buses (42) interconnecting the modules (34, 36, 38, 40) with each other consists of nine 8-bit wide data buses (42). Nine data buses (42) are respectively (42A), (42B), (
42C), (420).

(42E), (42F), (42G), (42+
1), (421).

Within each module (34, 36, 38, 40) there is a communication means (54). Additionally, there is logic device means (52) within each module, as described below, which in response to control signals on the control bus (32) causes each module's communication means (54) to communicate with one or more communication means (54). Connect to data bus (42).

FIG. 3 shows that in response to control signals on the control bus (32),
A block diagram of the portions of each module are shown interconnecting one or more data buses (42) to communication means (54) within each module. Third
An address decoding circuit (50) is shown in the figure. An address decoding circuit (50) is connected to eight address lines of the control bus (32). The address decoding circuit (50) outputs a signal (56) which activates the logic device (52) associated with it. Since each logic device (52) has a unique address, if the address line entering the address decoding circuit (50) matches the address for a particular logic device (52), the address decoding circuit (50) Bag @ (
Sends a signal (56) that activates 52). Each module has multiple logic bags F? (52) is good,
Each has an associated address decoder [50].

Each of the plurality of logical devices (52) can perform different tasks.

The logic device (52) is one of the data portions of the control bus (32).
From 6 bits, 16 data Φ bits are received.

Furthermore, the logic device (52) connects the control bus (32) to the four lines (DtJ1a line, i.e.,
V, C) 10.

Can be connected to WRT, vertical sync and horizontal sync. At this time, the logic bag M (52) includes a plurality of three-state transceivers (54A), (54B), (54C),
(540), (54E).

Controls the operations of (54F), (54G), and (541). It is understood that there are 8 individual 3-state transceivers (54) for a group of 3-state transceivers (54A) and 8 WJ individual 3-state transceivers for a group of 3-state transceivers (54B). I want to be The function of the three-state transceiver (54) is to connect one or more data buses (42A) with functions within the module of which the logic device (52) and address decoding circuitry (50) are a part. be. Furthermore, within the module, the cross-point switch (58) is connected to the three-state transceiver (54).
), multiple three-state transceivers (54) can be multiplexed onto one 8-bit wide bus (60).

FIG. 4 shows an address decoder (50), a logic bag ffi (
52) and a group of transceivers (54A) interconnecting with the bus (42A).

As mentioned above, eight address signal lines of the control bus (32) are supplied to the address decoder (50). When the address applied to the address lines of the control bus (32) is correctly decoded into the address of the logic device (52), the address decoder (50) sends out a signal (56) that goes high, which A device (52) is supplied. Address decoding circuit (
50) may be of ordinary design.

Logic unit I (52) has two AND gates (62a)
.

(62b), whose outputs are respectively J- type flip 7
Connected to O-tubes (64a) and (64b). The AND gates (62a), (62b) receive at one of their inputs a control signal (56) from the address decoder (50). The other input to the AND gates (62a), (62b) feeds into the data lines of the control bus (32). When the address decoder (50) determines that 52) should be activated, a control signal (56) that goes high causes the data present on the data lines of the 4 control bus (32) to be activated in the flip-flops (64a), (
64b). J-type flip-flop (6
4a) and (64b) are used to control eight 3-state transceivers (54A0...54A, ) 1tlJ. Each of the eight three-state transceivers is connected at one terminal to one 8-bit communication path of the bus (42^). The other terminal of each tri-state transceiver (54A) is connected to electronic components within the module.

The 3-state transceiver (54^), as its name suggests,
It has three states. A transceiver (54A) can transmit to the data bus (42A).

A tri-state transceiver (54A) connects the data bus (42^
) can receive data communications. Additionally, the three-state transceiver (54A) may be in an open position;
In that case, no communication with the data bus (42A) takes place. - As an example, the three-state transceiver is part 74A362 manufactured by Texas Instruments.
It is G. There are two such three-state transceivers (54^)
Receive human power. If the input is a combination of 0's and 1's, it represents one-way communication.

If a three-state transceiver receives inputs of 1 and O, it indicates communication in the opposite direction. 3-state transceiver (54A
) receives 00 on both input lines, then the three-state transceiver (54A) is in the open position. Since all three-state transceivers (54^...54A, ) are switched in the same way, i.e. all eight lines are connected to the data bus (42
A) or not connected, use the outputs of the flip 70 tubes (64a) and (64b) to
tJJ till all eight transceivers to interconnect to one data bus. Logical vit placement (52)
It also has other seven lip and control gates that control other three-state transceivers in groups of eight and one or more other data buses (42).
The connection selection can be switched in conjunction with the connection.

one or more data files for one or more of the plurality of modules (34, 36, 38, 40);
Since the bus (42) interconnection is controlled by the 11111m bus (32), the data path for the connection to the data number bus (42A-1) can be dynamically reconfigured.

FIG. 5a shows a dynamically reconfigurable data bus (42
) shows one possible format. Since each data bus (42) is 8 bits wide, the modules (34, 36, 38, 40) carry two data busses.
They can be connected to simultaneously receive data from buses (eg, 42A and 428).

This is a parallel mode of data processing, in which the data
Sixteen data bits are processed simultaneously along the bus. In this way, the data bus (42) can be coupled to increase the bandwidth of data transmission.

Figure 5b shows another possible format for the data bus (42). In this mode of operation, module (34) can transmit data to module (36) via data bus (42^).

Module (36) may communicate data with module (38) via data bus (42B).

Finally, the module (38) connects the data bus (42C)
can communicate with the module (4G) via.

This mode is called pipeline processing, and at this time,
Because the data passes through separate and unique data buses, data can pass from one module to another sequentially or simultaneously.

FIG. 5C shows yet another possible format for the data bus (42). The operation of this mode is
This is called interleaving. For example, module (34
) can process or transmit the data faster than module (36) or (38) can receive it, then module (34) transfers all odd data bytes to data. While being sent to module (36) via bus (42A), every even number of data bytes may be sent to module (38) via bus (42B). In this way, data can be stored or processed at the speed of the fastest module. This is different from the conventional method, in which multiple modules had to be operated at the speed of the slowest module.

Accordingly, as can be seen from the examples shown in FIGS. 4a-4C, by using a dynamically reconfigurable data bus structure, data bus structures including but not limited to those shown in FIGS. It is possible to dynamically and electronically reconfigure various data transmission paths that do not exist.

FIG. 6 shows a video image processing apparatus (110) according to yet another embodiment of the invention. Video image processing device (11
0) is similar to the video image processing device (10) and includes a master controller (130) and a plurality of digital modules (134), (13B) (this is not shown in the drawing), ( 138a), (138b) and (1
40). These modules are modules (34).

It is similar to (36), (3g), and (40) and performs the respective tasks of image processing and image storage. A master controller (130) communicates with one module each via a control bus (132). One module (134) to (140) each connects multiple data buses (4
2A-, 421). As with the video image processing device (10), there are nine data buses, each bus being eight bits wide.

Video image processing device (110) and video image processing device (10)
) the only difference is that along each data bus (42), a logic device (152) is activated by an address decoding circuit (150)! There is a switch means (154) that is illuminated. This is shown in detail in FIGS. 7 and 9. As seen in Figure 6, switch means (154A) to (1541) are provided between the image memory module (138a) and the image memory module (138b). That is, the switch means (154A) to (154I) connect the data bus (42
A) to (421) are divided into two parts. The first part consists of a video processor module (134) and an image memory module (138a), and the second part consists of a video processor module (140) and a second image memory module (138b). ). Switch means (15
4) can connect one part of the data bus (42A) to the other part or leave the data bus open, ie the data bus disconnected.

8a to 8C, switch means (154A)
The various forms of data bus M4 construction that can be considered by using (154I) are shown. Figure 8a shows nine data buses (42A) to (421), switch means (154A), (154B), (154
C) is the data bus (42A), (42B), (4
2C) into one continuous data bus. However, the switch means (1540)-(154r) are in the open position, thus cutting the data bus (420)-(421) into two parts. In this mode of operation, data buses (420) to (42I) are connected to modules (134), (138) and modules (138),
By using (140), parallel processing can be performed simultaneously. Furthermore, the data bus (42A) to (
42C), serial or vibline processing can be performed. As before, switch means (154^)
By using (154I), dynamically selectable fully parallel processing as shown in FIG. 8b or full vibe line processing as shown in FIG. 8C is possible. Additionally, other formats are possible, including, but not limited to, the macro-interleaved format of FIG. 5C.

FIG. 7 shows a block diagram of the electronic circuitry used to control the data buses (42A)-(42I) of the video image processing device (110). As mentioned before,
Switch means (154) are included between the two halves of each data bus (42). Figure 7 shows the data bus (
42A) and the switch means (154^) inserted in the middle of the data bus (421).
541) is shown. one switch means (1
54) is controlled by a logic device (152) operated by an address decoding circuit (150). Similarly to the address decoding circuit (50), the address decoding circuit (15G
) are connected to eight address lines of the control bus (132). When the correct address is detected, the control signal (1
5G) is sent to the logical device (152). Control signal (1
56) actuates the logic device (152), which actuates one or more switch means (154).

FIG. 9 shows a logic device (152) and a switch means (15).
4A) is shown. As can be seen from this figure, logic device (152) is identical to logic device (52). Switch means (154) (tri-state transceivers) interconnect half of one bus to the other half of the bus (42). In all other respects, the switch means (15
4) , logic device (152) and address decoding circuit (1
The operation of the address decoding circuit (50), the logic device (52) and the switch means (54) is the same as shown and described in the drawings.

A reconfigurable data bus (42) as previously described.
interconnects a plurality of modules (34, 3B, 38.40) with each other. The modules include multiple processor modules and multiple memory instruction modules. Apart from the communication means, logic and address decoding circuitry, the remaining electronic circuitry of each module for processing or storing data can be of conventional design. One processor module (34) is a video processor module.

A block diagram of the video processor module (34) is shown in FIG. Video bunt? A Tsusa module (34) receives three analog video signals from a color camera (12). Three analog video signals consisting of signals representing red, green and blue images are processed by a DC regeneration analog circuit (60).

Each of the resulting signals is sent to a quantizer (62).
Digitized by.

Each of the three digitized video signals is an analog video signal from a color camera (12) and is divided into segments to form a plurality of image pixels, each image pixel being divided into segments to form a plurality of image pixels. is digitized to form an 8-bit grayscale value. Digitized video signal 6x6 intersection matrix switch (64)
which converts the three digitized video signals into six
outputs to three of the three data buses (42A to 42F).

Digitized video signals are routed from data buses (42A) through (42F) to image memory modules (38A) through (42F).
38C) or more. The selection of a particular image memory instruction module (38A)-(38C) for storing a digitized video signal is determined by the address decoding circuit (52) connected to the logic unit (52).
50) and that this logic operates a particular tri-state transceiver (54), all as previously described. The data selection of which data bus (42) to send the digitized video image to is via the control bus (32).
Based on the registers in the logic unit (52) that are set by.

Each memory instruction module (38) has 3 megabytes of memory. The 3 megabytes of memory is divided into three memory planes: an upper plane, a middle plane, and a lower plane. Each plane of memory has 512 x 2048 bytes of memory. Therefore, there is approximately 1 megabyte of memory per memory plane.

Since each digitized video image is stored in 256 x 256 bytes of memory space, each memory plane has 1
It has locations for 6 video images. In total, the memory module has room to store 48 video images. Addresses are provided from the control bus (32) that select particular video images from particular memory planes within each memory module. When providing or receiving data to or from each memory module (38) via the data bus (42), data is provided to or from the location specified by the address set on the control bus (32). Receive from location. Typically, three digitized video images from the video processor (34) are stored at the same address location within a respective memory plane of each memory module.

Therefore, the digital video signal representing the red video image is X=2se, y=in the upper memory plane.

The digitized signal representing the blue video image can be stored at the first address location in the middle memory plane x
=256.5j=O, and the digital video signal representing the green video image can be stored at x=256, y=o in the lower memory plane.

- one or more memory modules (38) with digital video signals representing H-digitized video images;
Once stored in the memory plane of , the digitized video image is subjected to the action of a morphology processor (40).

A configuration processor (40) receives data from data buses (428) through (420) and
) to (42G). In addition, the morphology processor (40) has a data bus (4211) and (42
1) can receive input data from or output data thereto. A simplified block diagram of the morphology processor (40) is shown in FIG. The configuration processor (40) connects the data bus (42A), (42B)
, and this data is provided to a multiplexer/logarithm unit (70). The output (16 bits) of the multiplexer/logarithm unit (10) is connected to the data bus (4
2^) and (42B), or the logarithm thereof. The output of the multiplexer/logarithm unit (70) is provided as an input to the ALU (72) on an input port labeled b. ALII (72) has two input ports a and b.

The form block υ(40) is the multiplier accumulator (74
). Multiplier-accumulators (74) receive data from data conflict buses (42C) and (42D) and data conflict buses (4211) and (42I), respectively, and perform multiplication and accumulation n thereon. The multiplier accumulator (14) is connected to the 1) data (from the data bus (42C) or the data bus (420))
2) multiply data (from data bus (42C) or data bus (42D)) by a constant supplied by the master controller. can perform an action. This calculation result is output to the data bus (4211° (4211) and (42G). Multiplier accumulator (7
The result of 4) is to measure the kernel of the green function in real time. The core of the green function is the addition of all pixel values from the beginning of horizontal synchronization to the current pixel. This is then used to calculate other properties of the image.

A portion (16 bits) of the result of the multiplier accumulator (12) is also input to the input port a of the ALU (72). The multiplier accumulator (74) is capable of multiplication and accumulation with 32 bit precision. The result of the multiplier accumulator (14) can be switched to be the most significant 16 bits or the least significant 16 bits, and the AL
It is supplied to the a input of II (72).

The output of the ALU (72) is fed to the barrel shifter (76). It is then fed into the lookup table (78) and back onto the data buses (42E) and (42F).

The output of the ALU (72) is also fed to the prime generator (80), which also connects to the data buses (42E) and (42F).
can be returned to. The function of the prime generator (80) is to determine the border pixels as described in US Pat. No. 4,538,299.

ALU (72) can also perform the function of subtracting the data of input port a from the data of input port b. The result of the subtraction is an overflow or under70-condition, which determines a≧b or a≦b. Therefore, the maximum and minimum values for each pixel for the two images can be calculated.

Finally, the ALU (72) can calculate the histogram. There are two types of histogram calculations.

In the first type, a pixel value (a pixel value is 8 bits, ie from 0 to 255) selects an address in memory (13). Increments the memory location at the selected address by one. The second format uses two pixel values. The value of the first pixel is the current pixel position,
The value of the second pixel is the position of the previous row pixel to the immediate left or right (ie, the diagonal neighbor). The value of the paired pixel is used to address 64 memories (256 x 256) and increment the memory location of the selected pixel. Therefore, this histogram is related to the fabric.

In summary, the morphology processor (40) performs addition, multiplication,
The following operations can be performed: multiplying by a constant, adding a row, finding the minimum and maximum values for each pixel for two images, generating primes, and calculating histograms. The results of the morphology processor (40) are sent along the data bus (42) and stored in the image memory module (38). ^LU(72) may be a standard type 181, such as Texas Instruments part number ALS181. The sieve accumulator (74) may be of conventional design, such as the Wytetsuku TL2245.

Figure 13 shows the graphic! A simplified block diagram of the II till processor (36) is shown. The action of the graphics control (36) is controlled by the memory module (3).
8) receiving and combining and outputting the processed digitized video images, graphics data, and alphanumeric data from 8). Data from the control bus (32) is provided to the advanced CRT controller (84). CRT
The controller is part number 1106 manufactured by Hikuchi.
It is 3484. The output of the advanced CRT controller (84) controls the frame buffer p (80). Graphic φ data and alphanumeric data are stored in the frame buffer (80). Video images from data buses (42A) through (42F) are also provided to the graphics control processor (36). 1 data bus (42
) is selected, and its combination with the output of frame buffer y (80) is used to create the lookup table (a2
). After this, lookup table (8
The output of 2) is one data bus (42G), (4
211) or (421). The action of the graphics control processor (36) is to overlay video, alphanumeric and graphics information and then
It is to feed the monitor (86) via the converter (86). Furthermore, it is also possible to store superimposed digital images in one image memory module (38).

Images received by the graphics control processor (36) from one image memory module (38) are passed onto one data bus (42^) through (42F).

The control signal of the 111 control bus (32) is the starting address,
The image memory module (36) is provided with an Identify. Therefore, a divided screen image can be displayed on the display monitor (46).

As previously mentioned, the master controller (30) communicates with the host computer (22) via the Q bus. A master controller (30) receives address and data information from a host computer (22) and generates 64-bit microcode. The 64-bit microcode may be from a hostable control storage location in the host computer (22) (stored in WC3 (90), or
Or proxy PRON (ProxyProgm) (9
2). Since PROC3 (90) contains volatile RAM, it is used when the control program in proxy PROH (92) turns on the Ti source. 6
The 4-bit microcode is used for master i and II controllers (3G
)ノ29116＾Lu(94)! , − are processed with v. The master controller (30) is of Barbard architecture in that there are separate memories for instructions and data. Therefore, the processor (94
) can take commands and data at the same time. Furthermore,
v Star tIIJIIl (3G) is back m scene'7 #
(96) and a foreground sequencer (98),
writable control storage (90) or proxy PRO
Determines the order of a series of program instructions stored in M (92).

The Q bus from where the master controller (30) receives its programmable control storage and its program memory.
The memory map is as follows.

Address (hexadecimal) Usage 3FFFFF)
887 (Block 7, normal...
...Digital equipment...
・・・・・・Mento Corporation 3FE
OOG) symbol) 3FDFFF) Scratch pad 3F^000
) 387FFF) writable control storage 37
FFFF) Image memory window IFrFFF) Host computer, BU0
) Program memory update, control signals @ADAV, CHD and HWRT have the following uses.

Control signal Go to application 〇 V CHD WRT OX × Pause Bus 1
1 0 Read register 1 1 1 Write register 1 0 0 Read image memory 1 0 1 Write image memory Master controllers (30) each have one module (34)
.

(36), (38), (40) and asynchronously with the host computer (22). A clock signal is generated by a master controller (30) and clocks one module (34), (36), (
38), sent to (40). In addition, the master controller (
30) starts the entire sequence of video image processing and video image storage when vertical synchronization begins. Therefore,
One signal for each logic device (52) is the vertical synchronization signal.

Furthermore, a horizontal synchronization signal can be provided to each one logic device.

The logic device may also have a logic memory element that switches each three-state transceiver at predetermined times relative to the horizontal and vertical synchronization signals. FIG. 15 shows a circuit diagram of another embodiment of the logic device (252). A logic device (252) is connected to the first address decoding circuit (250) and the second address decoding circuit (251).

The logic device (252) includes a first AND gate (254).
), second AND gate (256), counter (
258) and a vertical synchronization register (260).

Before the logic device (252) operates, the first address decoding circuit (250) is activated and loads the counter (258) with data from the data lines of the control bus (32).

Then, when the second address decoding circuit (251) is activated and receives the vertical synchronization signal, the counter (258) counts down for each received clock pulse. When the counter (258) reaches 0, the 3-state register (64)
a), (64b) are activated.

Master control if! 1t (30), and respective processing modules (34).

It should be emphasized that (3G), (38), (40) and the respective image memory module (38) are of conventional design.

A master controller (30) controls the operation of one module each along separate control buses (32). Furthermore,
Each module communicates with each other via multiple data buses (42). One module each (34-4
0) with one or more data buses (42) within the module (34-40),
This is done by means controlled by the ii control signal of the Jt11 bus (32). a data bus (42);
The interconnections with electronic functionality within each module are as previously described. However, the electronic functionality within each module, such as memory storage or processing, may be of conventional architecture and design.

The video image processing device (10), (112) of the present invention has a number of advantages. The first is that the architecture can be changed dynamically because the interconnects are dynamically reconfigurable. In particular, when executing the same program, data can flow in pipelined or parallel fashion or a combination thereof. Furthermore, since the addresses are not provided via the data bus (42), but on a separate control bus, higher transmission speeds can be achieved. Finally, concurrent processing capabilities are provided because multiple processing modules and multiple memory modules can be attached to multiple buses and the interconnections of the buses can be dynamically reconfigured.

[Brief explanation of the drawing]

FIG. 1 is a simplified block diagram of an imaging apparatus using the video image processing apparatus of the present invention, and FIG. 2 is a block diagram showing the video image processing apparatus of the present invention with multiple 7 joules and multiple data buses. , FIG. 3 is a simplified block diagram illustrating a portion of each module of the video image processing apparatus of the present invention, along with communication means and logic control means interconnecting one or more data buses to the module. The figure is the third
Figures 5a-5c are simplified block diagrams showing various possible forms of connecting the modules to the data bus; Figure 6 is an electronic FIG. 7 is a simplified block diagram of a portion of the video image processing apparatus shown in FIG. 6; FIG. , logic device, address decoding circuit, and switching means for electronically switching the data bus of the video image processing device shown in FIG. 6. 8a to 8c are diagrams showing various possible configurations as a result of data bus switching of the video image processing device shown in FIG. 6, and FIG. 9 is a diagram showing various configurations of the video image processing device shown in FIG. Detailed circuit diagram of a portion of a switch and logic device, 1st
0 is a simplified block diagram of the video processor □ module of the video image processing device shown in FIG. 2 or 6, and FIG. 11 is an image memory of the video image processing device shown in FIG. 2 or 6.・Simplified block diagram of the module; FIG. 12 is a simplified block diagram of the video image processing device shown in FIG. 2 or 6; FIG. 13 is a simplified block diagram of the video image processing device shown in FIG. 2 or 6; A block diagram of the graphic control module of the m processing device, FIG. 14 is similar to FIG. 2 or 6.
A simplified block diagram of the master controller of the video image processing apparatus shown in FIG. 15 is a circuit diagram of an alternative form of logic. x Kuno U 0LLI L (Rikoichi

Claims (16)

[Claims] (1) Each data bus has a plurality of digital electronic modules that have a communication means and processes and stores data, and each data bus has a plurality of communication paths and interconnects the plurality of modules. a plurality of data buses connected to each other, a master control means, and a control bus having a plurality of communication paths each interconnecting the master control means with one module; controlling the operation of said plurality of modules by sending control signals along said control bus, with means in each module responsive to control signals from said control bus to transmit said communication means to one or more of said communication means; A digital processing system that connects to a data bus. (2) The digital processing system according to claim 1, wherein the plurality of modules are composed of a plurality of processor modules. (3) The digital processing system according to claim 2, wherein the plurality of modules include a plurality of memory modules. (4) In the digital processing system according to claim 1, a plurality of switches are arranged on one communication path of the plurality of data buses and interconnect the communication paths. means and in response to said control signal 1
means for activating one or more switch means to connect said communication paths. (5) A video image processing device for processing analog video images, each of which has a plurality of digital electronic modules having communication means, and the modules are connected to the analog video image.
a plurality of units that receive a video image, digitize the analog video image to form a digitized video image, process the digitized video image to form a processed digitized image, and output the digitized video image; a processor module, and a plurality of memories for storing the digitized video image and the processed digitized image;
a plurality of data buses interconnecting the plurality of modules, each data bus having a plurality of communication paths, and a master control means;
a control bus having a plurality of communication paths interconnecting the master control means with one module, the master control means controlling the plurality of modules by sending control signals along the control bus; and means in each module connecting communication means to one or more data buses in response to control signals from said control bus. (6) In the video image processing device according to claim 5, a plurality of switch means are arranged on one communication path of the plurality of data buses, and a plurality of switch means are arranged on one communication path of the plurality of data buses; means for responsively actuating one or more switch means. (7) In the video image processing device according to claim 5, the plurality of processor modules include:
a first processor module having means for receiving an analog video image and means for digitizing the analog video image to form a digitized video image; and processing the digitized video image to form a processed digitized image. a second processor module having means for outputting said digitized video image; and a third processor module having means for outputting said digitized video image.
A video image processing apparatus having a processor module. (8) In the video image processing device according to claim 7, the first processor module comprises:
A video image processing apparatus having means for simultaneously receiving three analog video images representing color components of one video image, and means for simultaneously digitizing the three analog video images to form three digitized video images. (9) The video image processing device according to claim 5, wherein one control signal is a clock signal. (10) A video image processing apparatus according to claim 9, in which each module operates in synchronization with the clock signal. (11) The video image processing device according to claim 10, wherein the analog video image is characterized by a vertical synchronization signal. (12) In the video image processing device according to claim 11, the vertical synchronization signal is one of the control buses.
a video image processing device transmitted to said module along two communication paths; (13) In the video image processing apparatus according to claim 7, the third processor module comprises a digital-to-analog conversion means for converting the digitized video image into an analog video image. Image processing equipment. (14) A video image processing apparatus according to claim 13, wherein the third processor module is a video image processing apparatus having means for simultaneously displaying graphic data, alphanumeric data and digitized video images. Image processing equipment. (15) In the video image processing apparatus according to claim 6, the responding means includes memory means for storing timing data, means for operating the memory means, and a means for activating the memory means. means for receiving the output and actuating one or more switch means. (16) In a digital processing system with a dynamically reconfigurable data path, a plurality of digital modules each having communication means and storing and processing data, and any data bus a plurality of data buses having a plurality of communication paths interconnecting the plurality of modules and dynamically reconfiguring connections between each module and one or more data buses; 1. A digital processing system comprising: master control means for generating control signals for controlling a signal; and means for connecting said communication means to one or more data buses in response to said control signals for each module.