JPH0131313B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrically erasable and rewritable semiconductor memory device, and more particularly to a semiconductor memory device having a function to prevent erroneous writing and erasing.

Conventionally, semiconductor memory devices, such as programmable read-only memory (PROM), include ultraviolet erasable type (UVEPROM) and electrically erased type (EEPROM), but when UVEPROM is erased, all bits are erased at the same time. Furthermore, erasing takes some time. Furthermore, during erasing and writing, it is necessary to stop the device. Furthermore, it is necessary to use a separately prepared eraser and writer, which is often a waste of cost and time. On the other hand, since EEPROM can be written and erased electrically, it is relatively easy to write and erase the EEPROM while it is still installed in the device. However, while this is convenient, there is a risk that a slight erroneous operation may cause other information to be written to the information contained in the PROM, or partial or complete information may be lost. There is.

It is an object of the present invention to provide a semiconductor memory device which eliminates the above-mentioned drawbacks and can prevent erroneous writing and erasing.

A feature of the present invention is that in an electrically erasable and rewritable semiconductor memory device, by disabling the erase and rewrite function, the semiconductor memory device can be converted into a read-only memory that cannot be erased or rewritten. It is a semiconductor memory device that can be converted into a device. Another feature of the present invention is to disable the erasing and rewriting functions of an electrically erasable and rewritable semiconductor memory device, thereby rendering the semiconductor memory device readable and non-erasable. There is a method to convert to only storage device.

According to the present invention, for example, the conventional method of using separate semiconductor memory devices for program development and product use can be reduced to just one type, thereby reducing costs. Also, since conventional EEPROMs can be used for products, costs can be reduced. It is possible to prevent defects from occurring due to erroneous erasure.

Next, embodiments (hereinafter referred to as N-ch) of the present invention will be described with reference to the drawings. FIG. 1 shows an Nch-PROM consisting of a gate 3, a drain 2, a source 1, and a floating gate 4. In the initial state or after erasing, floating gate 4 is in a grounded state. At this time, when a high level is applied to the gate 3, the source 1 and the drain 2 become conductive. When a high positive voltage is applied to the gate 3 and the drain 2 or the source 1 for a certain period of time, electrons enter the floating gate 4. Here, even if a high level is applied to the gate 3, the source 1 and the drain 2 are not electrically connected. If this state is defined as a data-written state "1", the former becomes "0". The operation up to this point can be considered to be the same for both UVEPROM and EEPROM. EEPROM is erased by applying a negative high voltage to the gate 3 and a positive high voltage to the source 1 or drain 2 for a certain period of time. Holes enter the floating gate 4, and the floating gate 4 is effectively erased to its initial state. This becomes the same as the grounded state later, and when a high level is applied to the gate 3, the source 1 and drain 2 become conductive again.

FIG. 2 is a partial circuit diagram of a semiconductor memory device according to an embodiment of the present invention. By applying a higher level to the power supply terminal 5, a higher level is applied to the gate 12 of the switch 10 through the fuse 8 and the resistor 9, making the switch 10 conductive. At that time, current flows from the power supply 6 through the resistor 11, and the terminal 13 becomes low level. As a result, the switch 15 becomes conductive, the switch 14 is cut off, and the application of voltage from the power source 6 is prohibited. Therefore, a positive high voltage or a negative high voltage applied from the terminal 16 to the gate, source, or drain of a storage element, such as an EEPROM cell (not shown), is output as is to the terminal 17, and this storage device is normal
It can be written and erased as many times as EEPROM. Next, when a high voltage is applied to the power supply terminal 5 to cause an overcurrent to flow through the fuse 8, the fuse 8 is blown and a low level continues to be applied to the gate 12 of the switch 10. Therefore, the terminal 13 becomes high level, the switch 15 is cut off, and the switch 14 becomes conductive. Therefore, the voltage applied from the terminal 16 is cut off at the switch 15 against both negative high voltages and positive high voltages. Therefore, the voltage applied from the terminal 17 to the gate, source, or drain of the EEPROM cell (not shown) is only the normal read voltage from the power supply 6, and the EEPROM cell (not shown) is fixed in the read state. In this way, by connecting the above-mentioned circuit, the information in the memory element in the EEPROM actually retains the previous information as it is even if a writing or erasing operation is performed.

FIG. 3 is another embodiment of the invention. Switch 27 and switch 28 operate in the same manner as in FIG. Resistor 19 and capacitor 24 constitute a delay circuit. In FIG. 3, the fuse 8 of FIG. 2 is replaced by an EEPROM or UVEPROM storage element. In operation, when the floating gate 22 is written, the switch 28 is cut off and the switch 27 is turned on. In particular, according to the example of FIG.
UVEPROM is effective only for writing,
Not valid for erasure.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of an EEPROM or UVEPROM storage element, FIG. 2 is a partial circuit diagram of one embodiment of the present invention, and FIG. 3 is a partial circuit diagram of another embodiment of the present invention. In the figure, 1... source, 2... drain, 3... gate, 4... floating gate, 5... power supply terminal, 6... power supply, 7... power supply,
8... Fuse, 9... Resistor, 10... Switch, 11... Resistor, 12... Gate, 13... Terminal, 14... Switch, 15... Switch, 16
...Terminal, 17...Terminal, 18...Resistor, 19...
...Resistance, 20...Terminal, 21...Gate, 22...
...Floating gate, 23...Drain, 2
4...Capacitor, 25...Terminal, 26...Inverter, 27...Switch, 28...Switch, 29...Terminal, 30...Power supply, 31...Terminal.

Claims (1)

[Claims] 1 A PROM cell, a first switch that applies a write voltage to the PROM, a second switch that applies a read voltage, a state setting means, and when the state setting means is in the first state, A write voltage can be applied to the PROM cell by setting the first switch in a conductive state and the second switch in a non-conducting state, and when the state setting means is in the second state, the first switch is in a non-conducting state. . A semiconductor memory device comprising: control means for turning on a second switch and applying only a read voltage to the PROM cell.