JP3510780B2 - Microcomputer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a built-in non-volatile memory (such as a flash memory) having characteristics capable of electrically erasing data and writing / reading data. 2. Description of the Related Art FIG. 3 is a block diagram showing a main part of a conventional microcomputer. In FIG. 3, (1) is a flash memory (non-volatile memory), which has a characteristic that data can be electrically erased collectively or partially (for example, in units of pages (128 words)) and data can be repeatedly written and read. The flash memory (1) functions as a program memory of the microcomputer. The memory cells in the address area A store program instructions for executing various logical operations, and the memory cells in the address area B store the program of the address area A. A rewrite command for rewriting the command is stored. The flash memory (1) normally jumps from the address area A so that the address area A is designated and the address area B is designated only when an interrupt request for rewriting the program contents of the address area A is generated. The microcomputer executes various logical operation operations according to the result of decoding the program instruction read from the address area A of the flash memory (1), while the microcomputer executes the rewrite instruction read from the address area B of the flash memory (1). The rewriting operation of the contents of the address area A is executed in accordance with the result of decryption. The rewrite data in the address area A of the flash memory (1) is prepared in advance in the microcomputer (eg, a mask ROM is separately provided and stored as table data) or supplied from outside the microcomputer. Any method (such as a method of supplying from a PROM writer) may be used. (2) A page buffer (static R)
Volatile memory such as AM), and has a storage capacity of 128 words for rewriting the program instruction in the address area A of the flash memory (1) in units of one page.
The page buffer (2) has an increment function for addressing itself. The rewrite data is temporarily stored in the page buffer (2) and then written to a designated page in the address area A of the flash memory (1).
Details will be described later. [0004] (3) is a flag circuit, which has 128 flags corresponding to each address of the page buffer (2) on a one-to-one basis. The page buffer (2) is for rewriting the address area A of the flash memory (1) in units of 128 words. However, there are cases where the user wants to rewrite all of the 128 words with different program instructions, and sometimes does not want to rewrite some of the 128 words with different program instructions and the rest of the word remains the same program instruction. In the latter case, when a 128-word unit program instruction is directly stored in the page buffer (2) from the mask ROM or the PROM writer, the same program instruction in the designated page of the flash memory (1) is stored in the page buffer (2). Must also be stored. In view of this, the flag circuit (3) only needs to store different program instructions in the designated page of the flash memory (1) in the page buffer (2). That is, the flag circuit (3) stores the mask ROM in the page buffer (2).
Alternatively, when a program instruction is stored from the PROM writer, a flag corresponding to the storage address of the page buffer (2) is set (logical value "1"). Accordingly, the 128 flags of the flag circuit (3) all have logical values "1" when all of the 128 words are rewritten with different program instructions, but when only part of the 128 words are rewritten with different program instructions. This is a combination of the logical value “1” and the logical value “0”. When reading the value of the designated page (128 words) of the flash memory (1) into the page buffer (2), the address of the page buffer (2) corresponding to the flag (logical value "1") of the flag circuit (3) is read. And reading of the address of the page buffer (2) corresponding to the flag (logical value “0”) of the flag circuit (3) is permitted. That is, the mask ROM or the PR is stored in a partial address of the page buffer (2).
When a different program instruction is stored from the OM writer, the program instruction of the designated page of the flash memory (1) is stored in the remaining address in the subsequent processing. The value of the address area A of the flash memory (1) is rewritten in units of one page, but by using the flag circuit (3), it can be rewritten in units of at least one word as in the case of the EEPROM. Flag circuit (3)
Is a state switching signal WR for setting a memory cell of the flash memory (1) to a write enable state or a write disable state.
Reset at the falling edge of T. As a method of rewriting a program instruction in the address area A of the flash memory (1), a method using the PROM writer and a method of rewriting the program instruction in the address area B of the flash memory (1) are used. There are two types of methods for executing the rewrite instruction. The PR
When the OM writer is used, it is not necessary to read out the rewrite instruction in the address area B of the flash memory (1). Therefore, during the period in which the program instruction in the address area A of the flash memory (1) is rewritten, the state switching signal WRT is constantly rewritten. The permission level (logical value “1”) may be used. In this case, the PROM writer sends an operation enable signal * CE, a write enable signal * WE, a write end signal EOW, an erase signal ERASE, a read signal RECALL, and a write enable signal * CE to the identification circuit (9) of the flash memory (1). A signal PROGRAM, address data ADATA, and program data PDATA are supplied. FIG. 4 is a time chart showing how the state switching signal WRT changes. Once the operation permission signal * CE and the write permission signal * WE once fall, the state switching signal WRT rises, and the memory cell of the flash memory (1) enters a writable state. When a series of write processing is completed, a write end signal EOW is generated, and the state switching signal WRT falls.
FIG. 5 is a time chart showing the operation when the state switching signal WRT is at the high level. When the state switching signal WRT rises, a predetermined number of program data PDATA within the range of 1 to 128 words is stored in the page buffer (2), and the flag of the flag circuit (3) corresponding to the storage address of the page buffer (2). Is set. After the storage in the page buffer (2) is completed, a predetermined time (for example, 30
After the elapse of 0 μsec), a read signal RECALL is generated, and the information of the designated page in the address area A of the flash memory (1) is read into the page buffer (2). However, the flag of the flag circuit (3) (logical value “1”)
The reading of the page buffer (2) corresponding to. As a result, when 128 words including different program data PDATA are prepared in the page buffer (2), an erase signal ERASE is generated and the designated page in the address area A of the flash memory (1) is electrically erased.
A write signal PROGRAM is generated and the value of the page buffer (2) is changed to the address area A of the flash memory (1).
To the specified page (the address specified by the address data ADATA). When the write operation to the flash memory (1) is completed, a write end signal EO
W is generated, and the state switching signal WRT falls. On the other hand, when executing a rewrite instruction for the address area B of the flash memory (1), it is necessary to read the rewrite instruction for the address area B of the flash memory (1).
The state switching signal W
It is necessary to periodically change RT to a rewrite permission level (logical value “1”) and a rewrite inhibition level (logical value “0”). In this case, the microcomputer supplies an operation enable signal * CE, a write enable signal * WE, a read enable signal * OE, and a write inhibit signal WI to the flash memory (1). FIG. 6 is a time chart showing a change state of the state switching signal WRT. When the operation permission signal * CE and the write permission signal * WE fall, the state switch signal WRT rises, and when the write inhibit signal WI occurs, the state switch signal WRT falls. During the high level period of the state switching signal WRT, the flash memory (1)
Becomes a writable state. After that, the operation permission signal * C
When E and the read enable signal * OE fall, the state switching signal WRT remains at the low level and does not change, so that the flash memory (1) is in a readable state. That is, when the state switching signal WRT is at a low level, a rewrite instruction for the address area B of the flash memory (1) is read,
When the state switching signal WRT is at a high level, a predetermined number of words of program data PDATA are stored in the page buffer (2) one word at a time in accordance with the result of decoding the rewrite instruction. However, the state switch signal WRT is transmitted to the page buffer (2) by the program data PDA of one word unit.
It falls every time TA is stored. That is, the flag of the flag circuit (3) is set each time the page buffer (2) stores the program data PDATA in units of one word, but is immediately reset by the falling edge of the state switching signal WRT immediately after. Therefore, the page buffer (2)
Is completed, the read signal
According to the LL, all information of the designated page in the address area A of the flash memory (1) is stored in the page buffer (2).
And the program change of the address area A of the flash memory (1) cannot be executed. The microcomputer shown in FIG. 3 can cope only with data rewriting using an external device. Accordingly, an object of the present invention is to provide a microcomputer which does not reset the flag circuit until the writing of the value of the buffer circuit to the nonvolatile memory is completed when the own program instruction is rewritten according to the rewriting instruction of the nonvolatile memory. And SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and enables electrical erasure and rewriting of data in units of a fixed storage capacity in all storage areas. A nonvolatile memory, an operation enable signal for controlling the operation of the nonvolatile memory, a state of a write enable signal and a state of a read enable signal are identified, and a storage cell of the nonvolatile memory is switched between a write enable state and a write disable state at a fixed cycle. An identification circuit for generating a state switching signal for performing the operation, a buffer circuit having the same number of addresses as the fixed storage capacity area of the nonvolatile memory, and storing rewrite data of the nonvolatile memory; and an address of the buffer circuit. A flag that is set only on a one-to-one basis and that corresponds to a rewrite data storage address of the buffer circuit; A flag circuit that, when transferring the value of the fixed storage capacity area of the memory to the buffer circuit, prohibits a transfer operation only at a corresponding address of the buffer circuit in which the flag is set, and is reset by the state switching signal; In the microcomputer including, after transferring the value of the fixed storage capacity area of the nonvolatile memory to the buffer circuit,
A prohibition circuit is provided for prohibiting resetting of the flag circuit until writing of the value of the buffer circuit into the fixed storage capacity area of the nonvolatile memory is completed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a circuit block diagram showing a microcomputer of the present invention. In FIG. 1, the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, reference numeral (4) denotes a latch circuit which holds the state switching signal WRT in synchronization with the clock CLK. (5) is a register, a flash memory (1)
When rewriting the information of a specific page in the address area A of
It holds the logical value "1" transferred from the internal bus (6), and holds the output signal OUT1 of the latch circuit (4).
Is reset in response to the change from the logical value “0” to the logical value “1”. The output signal OUT2 of the register (5) and the state switching signal WRT are supplied to the reset terminal of the flag circuit (3) via the OR gate (7). The operation of FIG. 1 will be described with reference to the time chart of FIG. First, when the power is turned on and all the functional blocks inside the microcomputer become operable, the program counter (8) addresses the address area A of the flash memory (1), and the microcomputer operates the flash memory (1). Performs various logical operations in accordance with the result of decoding the program instruction read from the address area A. Thereafter, when an interrupt request is generated to rewrite the program instruction in the address area A of the flash memory (1) in page units, the value of the program counter (8) jumps from the address area A to the address area B, and the microcomputer reads the address. The rewriting operation of the program instruction in the address area A is started according to the decoding result of the rewriting instruction read from the area B. Since the program instruction in the address area A is rewritten by using the rewrite instruction in the address area B, the state switching signal WRT rises when the operation enable signal * CE and the write enable signal * WE fall and the write inhibit signal WI. Is a signal that repeats a so-called intermittent high level that falls when the signal occurs. The relationship between the state switching signal WRT and the clock CLK is such that when the state switching signal WRT intermittently repeats the high level and the low level, the clock CLK is generated in synchronization with the low level of the state switching signal WRT. That is, during a period in which the state switching signal WRT repeatedly changes periodically under the influence of the write inhibit signal WI, the output signal OUT1 of the latch circuit (4) is always at the low level, and accordingly, the output signal of the register (5) is changed. OUT2 is always at a high level without being reset, and the output of the OR gate (7) becomes equal to the output signal OUT2. At this time, the flag circuit (3) is not reset. Therefore, the program data PDAT of a predetermined number of words (range of 1 to 128) is stored in the page buffer (2).
Even if A is stored, the corresponding flag of the flag circuit (3) is not reset while being set. After the storing operation of the page buffer (2) is completed,
After a lapse of a predetermined time (for example, 300 μsec), a read signal RECALL is generated, and a program instruction of a designated page in the address area A is read into the page buffer (2). However, since the flag circuit (3) acts as a gate between the address area A and the page buffer (2),
Only the program instruction of the address corresponding to the flag (logical value “0”) of the flag circuit (3) among the program instructions of the designated page of the address area A is read into the page buffer (2). Therefore, the page buffer (2) stores 128 words including the new program instruction from the mask ROM or the PROM writer and the previous program instruction from the address area A. Thereafter, when the erase signal ERASE is generated and the entire contents of the designated page in the address area A are erased, the write signal PROGRAM is generated, and during that time, the write inhibit signal WI is not generated. That is, the state switching signal W
RT remains at the rising high level in response to the first fall of the operation enable signal * CE and the write enable signal * WE after the generation of the write signal PROGRAM. Therefore, the output signal OUT1 of the latch circuit (4) changes to high level in synchronization with the first clock CLK after the generation of the write signal PROGRAM, and the output signal OUT2 of the register (5) is reset and changes to low level. . However, since the output of the OR gate (7) is equal to the state of the state switching signal WRT (always high level), the flag circuit (3) is not reset. Then, the state switching signal WR
During the high level period of T, the value of the page buffer (2) is written to the specified page in the address area A while being automatically incremented. When the rewriting operation of the designated page in the address area A is completed, the write signal PROGRAM goes low, and accordingly, the state switching signal WRT also goes low. Accordingly, since the output of the OR gate (7) becomes low level, the flag circuit (3) is reset for the first time in a series of rewriting operations of the flash memory (1). According to the embodiment of the present invention, when the program instruction of the address area A is rewritten according to the rewrite instruction of the address area B (in the case of on-board rewrite), the following operation and effect can be obtained. That is, the address area A
Since the flag circuit (3) is not reset until the rewriting of the address is completed, even if a part of the designated page of the address area A is changed, only the new program instruction to be changed is stored in the page buffer (2). Thus, even if the program instruction of the specified page in the address area A is read into the page buffer (2), the disappearance of the new program instruction can be prevented. According to the present invention, a program instruction for executing various logical operations is stored in a part of the address area, and a rewrite instruction for rewriting the program instruction is stored in the remaining address areas. When a program instruction is rewritten in accordance with a rewrite instruction in a microcomputer having a built-in nonvolatile memory, the following effects are obtained. That is, since the flag circuit is not reset until the rewriting of a part of the address area is completed, even if a part of the designated page of the part of the address area is changed, a new program instruction to be changed is sent to the buffer circuit. It is only necessary to store the program instruction, and the advantage is obtained that even if the program instruction of the specified page in a part of the address area is read into the buffer circuit, the disappearance of the new program instruction can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a microcomputer of the present invention. FIG. 2 is a time chart showing the operation of FIG. FIG. 3 is a block diagram showing a conventional microcomputer. FIG. 4 is a time chart showing how a state switching signal changes when a PROM writer is used. FIG. 5 is a time chart showing how various signals change when a PROM writer is used. FIG. 6 is a time chart showing how a state switching signal changes when an internal rewrite is performed. [Description of References] (1) Flash memory (2) Page buffer (3) Flag circuit (4) Latch circuit (5) Register (7) OR gate

Claims (1)

(57) [Claim 1] A non-volatile memory capable of electrically erasing and rewriting data in a fixed storage capacity unit of an entire storage area, and an operation permission signal for controlling the operation of the non-volatile memory An identification circuit for identifying a state of a write enable signal and a read enable signal, and generating a state switching signal for setting a storage cell of the nonvolatile memory to a write enable state or a write inhibit state at a fixed period; and A buffer circuit having the same number of addresses as the fixed storage capacity area, and storing rewrite data of the nonvolatile memory, and having a one-to-one correspondence with the address of the buffer circuit and corresponding to the rewrite data storage address of the buffer circuit. A flag that is set only at the position where the data is to be transferred, and transfers the value of the fixed storage capacity area of the nonvolatile memory to the buffer circuit. A flag circuit that prohibits a transfer operation only at a corresponding address of the buffer circuit in which the flag is set and is reset by the state switching signal, wherein the value of the fixed storage capacity area of the nonvolatile memory is A microcomputer comprising a prohibition circuit for prohibiting resetting of the flag circuit until the value of the buffer circuit is transferred to the buffer circuit and is written to a fixed storage area of the nonvolatile memory.