JPH01305453A - ROM card control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding the ROM card control method in a system in which ROM cards are added to the device body as necessary, CPU! J)
The purpose of this system is to prevent abnormal operations such as runaway in the CPU even if the ROM card is removed during a game, and the storage capacity is increased by connecting the device body including the CPU and the ROM card installed externally via a bus. In a system for adding a ROM card, a pseudo operation code generation circuit is provided to set a predetermined operation code on the bus when the ROM card is pulled out between the bus and the ROM card.

[Industrial Application Field] The present invention relates to a ROM card control method in a system in which ROM cards are added to a device main body as necessary.

It is not possible to configure a system such as a portable word processor in which the Niprogram is converted to ROM, or a system in which the program is loaded and executed by using a floppy disk into the internal RAM of the device (because the required amount of RAM cannot be obtained, or if the program is frequently used). For devices that cannot access Flotsbee disks, RO is available that can expand functionality at the element level.
The M card is also effective in terms of processing speed for access and the like. However, the reality is that sufficient measures have not been taken in the event that the main unit is pulled out during operation.

[Prior Art] FIG. 4 is a diagram showing the configuration of a conventional ROM card control system. In the figure, 1 is the main body of the device, and there is a CP inside it.
It includes U1a and memory 1b for main storage. The bus 3 pulled out from the main body of the device is equipped with ROM as necessary.
Card 2 is connected. The ROM card connected to the bus 3 in this manner can be treated in the same way as an internal element from the perspective of the CPU 1a, and the storage capacity can be easily increased or decreased.

[Problems to be Solved by the Invention] In this type of device, if the 80M card is removed while the CPU 1a is operating, the device will malfunction. Particularly if the ROM card is used to store data, there will not be much damage, but if the card is used to store programs, the CPU may run out of control or stop. . As a countermeasure in such a case, either do not take any measures at all, or, in order to prevent the occurrence of a malfunction, open the lid of the part where the card is inserted (at this time, the card is electrically connected). )
The system was supposed to shut off the power to the device.

The present invention was made in view of these problems, and even if the ROM card is removed while the CPU is operating, the CPU
The purpose of this invention is to provide a ROM card control system that does not cause abnormal operations such as runaway.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. Components that are the same as those in FIG. 4 are designated by the same reference numerals. In the figure, 4 indicates a ROM between the bus 3 and the ROM card 2.
This is a pseudo operation code generation circuit that sets a predetermined operation code on the bus when the card 2 is pulled out.

[Operation] Assuming that the ROM card 2 is removed while the CPU 1 is operating, the pseudo operation code (operation code) generation circuit 4 sets a pseudo operation code on the bus 3. Here, the condition is that the opcode to be set is completely different from the normally used opcode (undefined code). CPLJla reads this opcode using the mine cycle, and when it confirms that the read opcode is different from the normal opcode, it reads it from the ROM.
It is determined that the card has been withdrawn, and processing proceeds accordingly. As a result, even if the ROM card is removed,
It is possible to prevent the CPU 1a from malfunctioning or running out of control.

[Embodiment] FIG. 2 is a block diagram of main parts showing an embodiment of the present invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals. The pseudo-opcode generation circuit 3 includes eight resistors R, one end of which is connected to the bus, and the other end connected to a power supply voltage of 5V. This resistance circuit is
Although 8 bits are used to correspond to the fact that the bus has 8 bits, it is sufficient to provide them according to the number of pits of the bus.

Generally, such a resistance circuit can be realized using a resistance module in which a plurality of resistances having the same resistance value are packaged. 10a and 10b are bus and R, respectively.
This is a connector attached to the OM card. I! 1-I
18 are lines of bus 3, respectively.

In the device configured in this way, g) the lid 10a;
10b is connected and the CPU 1a is connected to the ROM card 2.
Assume that it is operating while accessing the inside. At this time, the resistor circuit connected to the bus does not affect the data on the bus. In other words, if the value on the bus is 1'', it remains at "1", and if the value on the bus is at "0", it remains at 0. For example, line l! When 1 is 1'', both ends of the resistor R have almost the same potential, and no current flows through the resistor R.On the other hand, when the line l!1 becomes 0'', there is approximately 5V across the resistor R. A voltage is applied and a current flows through the resistor R to maintain the line 11 at 11011.

Here, if we assume that ROM card 2 has been pulled out, it will be line! 1 to I18, the potential is not determined. The reason is as follows. That is, when the ROM card 2 is selected, no other elements are connected to the bus 3. The other elements have their outputs set to high impedance and are separated from the bus 3.

Therefore, the only selected ROM card is cut 1.
11, nothing is connected.

Therefore, line! Therefore, the potentials of 1 to 18 are not determined. However, according to the present invention, the line! 1~
18 is connected to 5V via the resistor R, so CP
U1a takes in code data 'FF F' in hexadecimal. Assuming that this code 'FF' is a code that is not normally used (undefined code), CPU1a
By reading this code, the user can recognize that the ROM card 2 has been removed. Once it is recognized that the ROM card has been removed, alarm processing can be performed accordingly.

In the above explanation, all lines are treated as undefined code ′
The case where it is set to 1" has been explained.

However, the present invention is not limited to this, and any opcode can be used. In that case, there will be some lines that are connected to the 5V power supply line via a resistor and others that are grounded via a resistor. An example of such code settings is shown in FIG. Here, a case is shown in which the undefined code is set to "' F F OO".

Further, the number of bus pits is not limited to 8 bits, and a bus with a smaller or larger number of bits can be used.

Furthermore, in the above description, an example is given in which a resistor circuit is used to set a pseudo opcode on the bus, but the present invention is not limited to this, and other pseudo opcode creation circuits may be used. can. For example, by using a date switch or the like in combination with a resistor, it is possible to realize a pseudo opcode generation circuit that can freely change the pseudo code.

[Effects of the Invention] As explained in detail above, according to the present invention, by providing a pseudo-opcode creation circuit that can set a pseudo-opcode in the ROM card and the bus, CPL
It is possible to provide a ROM card control method that can prevent abnormal operations such as runaway in the CPU even when the ROM card is pulled out during IvJ work.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of main parts showing one embodiment of the invention, Fig. 3 is a block diagram of main parts showing another embodiment of the invention, and Fig. 4 is a block diagram of main parts showing an embodiment of the invention. FIG. 2 is a diagram showing the configuration of a conventional method. In Fig. 1, 1 is the main body of the device, and 1a is the CPLJ. 1b is a memory, 2 is a ROM card, 3 is a bus, and 4 is a pseudo-opcode generation circuit. Patent applicant: Fujitsu Limited
Ceremony Attorney Patent Attorney Ijima
Fuji Jigai 1 person 1st figure corner ■ 2 Ward 3rd figure corner answer 4 Huge

Claims (2)

[Claims] (1) In a system in which the storage capacity is increased by connecting the device body (1) including the CPU (1a) and the ROM card (2) installed from the outside via the bus (3), the bus (3) and the ROM ROM card control characterized in that a pseudo operation code creation circuit (4) is provided between the bus connecting the card (2) and the bus when the ROM card (2) is pulled out, and sets a predetermined operation code on the bus. method. (2) The ROM card control system according to claim 1, characterized in that a resistor circuit connecting a resistor to a power supply voltage or a ground potential is used as the pseudo operation code generating circuit (4).