JP3138932B2 - Memory card - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card used as an external memory device of information equipment such as an electronic still camera, a personal computer, and a word processor.
More particularly, the present invention relates to a memory card capable of storing still image data and a large amount of data.

[0002]

2. Description of the Related Art Recently, IC memory cards have been widely used in various technical fields, for example, in information devices such as electronic still cameras, personal computers, and word processors. Used as an external memory device. Regarding this IC memory card, for example, from the "Japan Electronics Industry Development Association", "IC Memory Card Guidelines (standard specification of memory card / pin connector for personal computer)", version 3 (May 1989) Mon) is proposed as the latest one. Conventionally, an IC memory card has a direct connection bus system in which input / output pins of an internal IC memory chip can be directly specified as interface signals.
An I / O bus system that can be easily connected to the input / output bus of the microcomputer is adopted. However, the former has a large number of pins and is difficult to connect to the input / output bus.
The bus system is often used.

The I / O bus type memory card has a built-in address register for indicating an arbitrary address of the internal memory chip. In the I / O bus system shown in version 3 of the above-mentioned guideline, this register has three bytes, and two bits are assigned to specify the three-byte register. This 2
Regarding the bits, address 0 (“0” “0”) is the lower address register, address 1 (“0” “1”) is the middle address register, and address 2 (“ 1 "" 0 ") are used to specify the upper address register. In addition, the third address (“1”
"1") is a memory access register, which is designated as "read" or "write" to read and write to the memory at the address specified by the address register. It can be performed.

However, since the conventional address register is 3 bytes (1 byte = 8 bits) as described above, the maximum address that can be represented is "2" to the 24th power, and 1
You can only specify up to addresses 6,777,216. In other words, this memory card can only have a storage capacity of 16 megabytes. As described above, in order to specify the 3-byte register, only two lines are required as the address lines.

[0005]

As described above, the conventional I / O bus type memory card according to the above guideline is used.
In the case of the flash memory, there is only a storage capacity of a maximum of 16 megabytes, and there is a disadvantage that the capacity becomes insufficient when used as a medium for storing a large amount of data such as an electronic still camera. In order to secure a storage capacity of 16 megabytes or more, it is conceivable to add an address register in the IC memory card. For example, if the address register is 4 bytes, the maximum address that can be handled is 2 32 = 4,294,967,29
Up to address 6, a large memory capacity can be handled. However, in this case, the number of control registers is required five, and eventually the number of pins is required three.
There is a disadvantage that the number of pins of the IC memory card increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory card which solves the above-mentioned drawbacks and can greatly increase the storage capacity without increasing the number of pins.

[0007]

In order to achieve the above-mentioned object, according to the present invention, an attribute for storing physical information of a card in a memory card used by being connected to a certain information device. And a plurality of address registers having the same bit width as the data bus of the memory, and the address registers are set by associating these address registers with bits. An address control register which can be specified and which can specify whether to access the attribute memory or the common memory. After writing the memory control data to the address control register, the address can be written to the specified address register. control to Rutotomoni, registration for the plurality of addresses as
The address is expressed using the
And a memory card provided with access means .

[0008]

In the present invention, the combination of control signals is changed, each bit of the address control register is made to correspond to the address register on a one-to-one basis, and the address register is designated by the address control register, and then the address register is designated. The address can be set.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the internal structure of a memory card according to the present invention. FIG. 2 is a diagram showing the correspondence of signals to the pins of the memory card, and basically follows the above guidelines.

The memory card 1 shown in FIG. 1 comprises an attribute memory 2, a common memory 3, a control circuit 4 for controlling these, a power supply control circuit 5, and a backup battery 6. The attribute memory 2 is a memory for storing physical information of a card.
They are connected by address lines and data bus lines.

The common memory 3 is a memory for storing data, and is connected to the control circuit 4 by control lines, address lines, and data bus lines as described above. The control circuit 4 provides an external circuit (for example, a card controller) with a card enable CE, control signals C0 and C1, a read signal RD, a write signal WR, and a ready signal RDY / BS.
Y, write inhibit signal WP, data address bus D0
To D7 are connected so as to be able to input and output.

Here, as shown in FIG. 2, the memory card has a pin number "1, 20" with a GND and a number "2.
Data address bus D0 to D7, number "10" at "9"
To power supply Vcc and number “11” to program supply Vp
p, ready signal RDY / BSY at number "12", card enable CE at number "13", numbers "14, 15"
Control signals C0 and C1, and the read signal R
D, a write signal WR is assigned to the number “17”, a write inhibit signal WP is assigned to the number “18”, and a battery check Vbat is assigned to the number “19”. Also, in FIG.
The control signals C0 and C1 of numbers "14 and 15" are control signals used in the embodiment of the present invention, and the details of the control contents will be described in the following description of FIG. The power supply control circuit 5 is connected to an external power supply via a power supply line Vcc and GND.
Further, a signal Vbat indicating the state of the battery is supplied to an external circuit, and further connected internally to a backup battery 6 to supply power to the attribute memory 2, the common memory 3, and the control circuit 4. I do.

FIG. 3 is an explanatory view schematically showing an embodiment of the present invention. The circuit shown in this figure is configured inside the control circuit 4, and includes an address control register 40 and seven address registers 41 to 47. The address registers 41 to 47 correspond to the address control registers 40.
Each of the bits corresponds to the address registers 41 to 47, and when the corresponding bit of the address control register 40 is set to “1”, the corresponding address register is selected. That is, the first bit of the address control register 40 is the address register 41, the second bit is the address register 42, the third bit is the address register 43, and the fourth bit is the address register 44. ,
The fifth bit is the address register 45, the sixth bit is the address register 46, the seventh bit is the address register 47, and the eighth bit is either the attribute memory 2 or the common memory 3. This is for specifying whether or not to access.

[0014] FIG. 4 is an explanatory diagram for explaining the function allotment of control signals C0, C1 of the present invention. When the control signals C0, C1, R / W are "" 0 "" 0 "" R "",
No control is performed when the signals become "0""0""W" , "0""1""R", and "1""0""R", but the control signals C0 and C1 are "0". When “1” “W” is reached, write control of the address control register 40 is performed. Control signal C
When 0, C1, and R / W become “1”, “0”, and “W”, address write control is performed. Control signals C0, C1, R /
When W becomes "" 1 "" 1 "" R "", the reading control of the memory data is performed. When W becomes "" 1 "" 1 "" W "", the writing control of the memory data is performed. Becomes

The operation of the embodiment will be described. FIG.
FIG. 6 is a time chart for explaining the read timing of the memory card, and FIG. 6 is a time chart for explaining the write timing of the memory card.

{Read Operation of Common Memory 3 of Memory Card} First, a read operation of the common memory 3 of the memory card 1 will be described with reference to FIG. Mosquitoes - Dokontoro - La (not shown), Memorika - mosquitoes to de 1 - Doine - to enter the Bull CE "1" (time t _0).

Subsequently, the card controller is shown in FIG.
As shown in the figure, the control signals C0, C1, and R / W are changed to "1".
"0""W" (see also FIG. 4, hereinafter the same) by a "(time t ₁ ~t _2), and writable address control register 40, a predetermined address register in the address control register 40 Write the specified data (time t
₁ ~t _2). At this time, the address control register 40
The bit is set to “0”. As a result, one of the address registers 41 to 47 is designated.

Subsequently, FIG.
As shown in FIG. 7, the control signals C0, C1, and R / W are "0".
"1""W" becomes the "((time t ₃ ~t _4), the address for either the address register 41 to 47 is set to the address control register 40 is written (time t ₃ ~t ₄ ).

Subsequently, the card controller changes the control signals C0, C1, and R / W to "1" and "1" as shown in FIG.
With "R""(time t ₅ ~), common memory 3 Karade to Setsujo address - can be read data (time t ₅ ~). At this time, the address of the set address is automatically updated in the address control register 40 and the address registers 41 to 47 every time data is read out.
Once reading is started, there is no need to specify the address again, and data of consecutive addresses is read. If the eighth bit of the address control register 40 is set to "1", the same operation as described above can be performed to read data in the attribute memory 2.

{Write Operation of Common Memory 3 of Memory Card} Next, a write operation of the common memory 3 of the memory card 1 will be described with reference to FIG. Mosquitoes - Dokontoro - La (not shown), Memorika - mosquitoes to de 1 - Doine - to enter the Bull CE "1" (time t _0).

Subsequently, the card controller is shown in FIG.
As shown in the figure, the control signals C0, C1, and R / W are changed to "1".
By setting “0” and “W” (see also FIG. 4, the same applies hereinafter), the address control register 40 becomes writable (time t _{1 to} t ₂ ), and a predetermined address register is stored in the address control register 40. Write the specified data (time t
₁ ~t _2). At this time, the address control register 40
The bit is set to “0”. As a result, one of the address registers 41 to 47 is designated.

Subsequently, FIG.
As shown in FIG. 7, the control signals C0, C1, and R / W are "0".
When it becomes “1” “W” (time points t _{3 to} t ₄ ), the address register 4 set in the address control register 40
Addresses are written toward 1 to 47. (Time t
₃ ~t _4).

Subsequently, the card controller changes the control signals C0, C1, and R / W to "1" and "1" as shown in FIG.
With "W""(time t _5), de the common memory 3 to the address set - you can write data (time t ₅ ~). At this time, the address control register 4 is written every time data is written to the set address.
By automatically updating the addresses of 0 and the address registers 41 to 47, once writing starts, it is not necessary to specify again. The eighth bit of the address control register 40 is set to “1”.
Thus, data can be written into the attribute memory 2 by operating in the same manner as described above.

As described above, the present embodiment operates, and the memory capacity can be expanded up to a maximum of 2 56 bytes without increasing the number of pins and without any problem electrically.

[0025]

As described above, according to the present invention, the combinations of the control signals are changed, and each bit of the address control register is made to correspond one-to-one to the address register.
Further, since the address can be set in the address register after designating the address register in the address control register, the memory capacity can be increased without increasing the number of pins of the memory card. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a memory card according to the present invention.

FIG. 2 is an explanatory diagram for explaining the correspondence of signals to pins of a memory card according to the present invention.

FIG. 3 is a diagram for explaining a main part of an embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a configuration example of a control signal used in the embodiment of the present invention.

FIG. 5 is a time chart for explaining a read operation of a memory card;

FIG. 6 is a time chart for explaining a write operation of a memory card.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory card 2 attribute memory 3 common memory 4 control circuit 5 power supply control circuit 6 backup battery 40 address control register 41 to 47 address register

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-328384 (JP, A) JP-A-4-1377084 (JP, A) JP-A-4-52891 (JP, A) JP-A 64-64 7287 (JP, A) Takehiro Yoshihiro, "Dissecting an IC Memory Card from the Hard Surface", Electronics, Ohmsha, May 1, 1991, Vol. 36, No. 5, p. 44-48 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 3/08 G06F 12/00-12/06 G06F 13/16-13/18 G11C 7/00 G06K 17 / 00,19 / 07

Claims (1)

(57) [Claims] In a memory card used by being connected to a certain information device, an address of an attribute memory for storing physical information of the card or a common memory for storing data can be set. In addition, a plurality of address registers having the same bit width as the data bus of these memories can be assigned to the address registers in a bit-corresponding manner, and the address registers can be designated, and either the attribute memory or the common memory is accessed. Address control register that can specify
Address control register in the memory controller de - After writing the data, The rewritable control to write the address into the address register, register for the plurality of address
Address to the common memory using the
De - Memorika, characterized in that a section for the scan.