JPH0126195B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a field effect transistor.

The present invention is not limited in any way to materials, and can be applied to a wide range of general semiconductor materials such as single-element semiconductors such as Si or compound semiconductors. The explanation will be given using GaAs among semiconductors as an example.

Conventional shot barrier gate field effect transistors (hereinafter abbreviated as MESFET) use a shot junction formed by contact between a metal and a semiconductor as a gate, and because of their excellent characteristics, they have been used as low-noise amplification elements in the microwave region. It is commonly used as a high output amplification or oscillation device. Figure 1
1 is a cross-sectional structural diagram of a MESFET according to a conventional general manufacturing method. An active layer 2 is formed on a semi-insulating semiconductor substrate 1 by epitaxial growth or ion implantation (FIG. 1a). Au―Ge―Ni
A source electrode 3 and a drain electrode 4 made of a base alloy were formed using ordinary vacuum evaporation and lithography techniques, and then an alloy treatment was performed at about 470° C. for several minutes. (Figure b) After that, the gate electrode 5 is formed using the same usual vacuum deposition and lithography techniques.
Active layer 2 between source electrode 3 and drain electrode 4
(c in the same figure).

By the way, in order to improve the high frequency characteristics of MESFET, it is necessary to make the gate length l as small as possible, which requires extremely fine precision machining in device fabrication. However, in the conventional manufacturing method, when forming the pattern of the gate electrode 5 in the resist, there is a step caused by the source electrode 3 and the drain electrode 4 in the very vicinity of the gate pattern in addition to the step of the mesa region 2. Therefore, the resolution of the photoresist pattern is lower than that on a flat surface, making it difficult to reliably form a gate pattern as short as about 1 μm. In particular, with compound semiconductors such as GaAs, it is common practice to perform alloy treatment on the source electrode 3 and drain electrode 4 before forming the gate electrode 5 in order to reduce their contact resistance. If alloying is performed at a sufficiently high temperature and for a long time in order to make the gate sufficiently small, agglomeration of the source and drain electrode metals will occur, which tends to cause extremely large steps, which is also a cause of deterioration of the resolution of the gate photoresist pattern. It's getting old.

Further, the gate electrode 5 needs to be formed between the already formed source electrode 3 and drain electrode 4 with a positional accuracy of ±0.2 μm or less. Furthermore, the distance between the source electrode 3 and the gate electrode 5 directly affects the parasitic resistance and parasitic capacitance between the source and gate in terms of the electrical characteristics of the MESFET, so the distance between the two electrodes should be kept as small as possible and controlled with high precision. The above-mentioned positional accuracy is also required in terms of the distance between the electrodes. However, it is extremely difficult to form such fine patterns with high precision using conventional techniques, and therefore there is a problem in that the manufacturing yield is extremely low.

As one method to solve these technical problems, a method has been announced in which a gate pattern with a length of 1 μm or less is directly drawn on a semiconductor material using electron beam exposure technology (for example, N. KATO
etal IEEE on ED 27-6 (80) P1098). In this case, the alignment accuracy is determined by the accuracy and stability of the electron beam exposure system, and is possible up to about ±0.5 μm, but on the other hand, it takes a long time to write, and the equipment is difficult to write a pattern of 1 μm or less. Since it requires complex processes such as maintaining the stability of the image and optimizing the drawing conditions, there is a problem of low productivity. Further, although submicron patterns have been transferred using deep ultraviolet exposure technology, although this improves productivity, it is insufficient in terms of alignment accuracy.

On the other hand, there is a method called self-alignment as one means for solving the problem of high-precision alignment. FIGS. 2A and 2B are diagrams illustrating main examples thereof. In FIG. 2A, the source electrode 3 is
After forming a drain electrode 4 (a in the same figure) and etching the active layer 2 in the depth and lateral directions using this as a mask (b in the same figure), a gate electrode 5 is formed in the recessed part of the active layer (b in the same figure). c) The thickness of the active layer 2 between the source electrode 3 and the gate electrode 5 is reduced, and a so-called recessed structure is adopted in consideration of reducing the electrical resistance between both electrodes. In FIG. 2B, a gate electrode 5 is first formed with a multilayer film (a in the same figure), and the lowermost metal layer is laterally etched (b in the same figure), and ohmic electrodes 3 and 4 are formed using the upper layer of this electrode as a mask. (Figure c) method. However, in these self-alignment methods, it is common that steps or voids necessary for the mask pattern are obtained by chemical etching. Among chemical etching methods, wet etching using a chemical solution has a thickness of 1 μm.
Microfabrication of the following patterns is impossible, and plasma etching (dry etching) using gas plasma has poor etching reproducibility.
High-precision processing around 1 μm is difficult. Furthermore, with these chemical etching methods, it is impossible to control lateral etching with an accuracy of 1/10 μm.

As described above, with conventional methods, it is extremely difficult to manufacture gate lengths of 1 μm or less and source-to-gate distances with an accuracy of 1/10 μm with good yield.

The present invention aims to improve these drawbacks of the conventional method, and its purpose is to provide a device with excellent high-frequency characteristics having a gate length of 1 μm or less and a distance between the source and gate.
The purpose of the present invention is to provide a method for manufacturing MESFETs with high precision and high yield.

In the present invention, an insulating compound is formed on the surface of the gate metal, which was originally formed to a length of about 1 μm, with a high precision of about 1/10 μm, and this is applied to the self-alignment method that determines the distance between the source and gate. The aim is to achieve the above goals by utilizing the system.

In the following description of the present invention, GaAs is a compound semiconductor that has the advantage of high operating speed as a semiconductor material.
Let's take this as an example. However, this does not limit the materials used in the present invention, and the present invention can be applied to a wide range of general semiconductor materials such as single-element semiconductors such as Si or compound semiconductors.

Hereinafter, the present invention will be explained in detail based on Examples.

FIG. 4 is a process explanatory diagram of an embodiment of the present invention, and FIG. 3 is a sectional view showing the structure of a field effect transistor manufactured according to this embodiment.

First, the structure of the field effect transistor shown in FIG. 3 will be briefly explained. The semiconductor device has a structure in which a gate electrode is provided directly on the semiconductor material active layer 2 on the substrate 1, and a source electrode 3 and a drain electrode 4 are further provided on the semiconductor material active layer 2 in close contact with the gate electrode 5. A gate electrode metal compound film 5' is provided around the gate electrode 5.

In this structure, the distance between the source electrode and the gate electrode, the distance between the drain electrode and the gate electrode,
The structure allows extremely fine control of the width of the gate electrode in the submicron range. Further, since an ohmic metal film made of the same material as the ohmic electrode is formed on the gate electrode 5, the cross-sectional area of the gate electrode is large and the resistance of the gate electrode is extremely low.

Next, a method for manufacturing a field effect transistor, which is an embodiment of the present invention, will be described with reference to FIG.

As a semiconductor material, 1×
Doped with Te at a carrier concentration of 10 ¹⁷ pieces/ ^cm3
A device provided with a GaAs epitaxial layer 2 was used. After mesa etching and leaving only the required area of 2, spacers 6 are formed on this surface for forming a thick metal pattern. In this case, the aspect ratio is increased with a fine pattern,
In addition, reactive sputter etching will be used to obtain a nearly vertical wall pattern. A CVDSiO ₂ film with a thickness of 2000 Å is formed as a spacer on the lower layer 6', and an organic polymer film such as a photoresist is placed on top of it.
Coat it as a spacer 6 to a thickness of 1.5 μm (see figure a). After the prescribed baking process, the spacer 6 is formed by photolithography and lift-off using normal ultraviolet light.
Al pattern 7 with a thickness of 1000 Å is placed on top (pattern dimensions
1 μm) (Figure b).

Then, using Al pattern 7 as a mask,
Spacers 6 and 6' are etched in a high frequency discharge of O ₂ gas and 5% CF ₄ -O ₂ mixed gas at 10 ^-1 Torr, respectively. The time required at this time is approximately 25 minutes with a discharge power of 100W. As a result, in spacers 6 and 6' the width surrounded by the vertical walls of the spacers is
A 1 μm void is formed (Figure c). In this state, Al metal 5 for the shot electrode is deposited to a thickness of 0.5 μm, and then SiO ₂ is deposited to a thickness of 0.2 μm as an insulating film 8 by, for example, vacuum evaporation (FIG. d), and the Al 7/spacer 6 and When the Al film/SiO ₂ film thereon is removed with a solvent, an Al shot electrode 5 is formed (e in the same figure). Next, both sides of the electrode 5 are oxidized by, for example, an anodic oxidation method, so that the surface of the electrode 5 is covered with alumina oxide (Al ₂ O ₃ ) 5'. (Figure f) Al ₂ O ₃ is an excellent insulating material. In this example, oxidation was performed at a rate of 200 Å/min in order to accurately control the oxide film thickness. Anodic oxidation was performed in a tartaric acid/ethylene glycol mixed aqueous solution at room temperature for 10 minutes. The sample current density was 3 mA/cm ² , and since the anodic oxidation rate based on this current value does not decrease even if the oxide film becomes thicker, the film thickness can be easily controlled.

At this time, the GaAs surface other than the gate portion is protected by the spacer lower layer 6' and does not change at all during the anodization process of the gate electrode. After anodizing, when the spacer lower layer 6' and the insulating film 8 on the shot electrode are removed, the gate electrode remains unanodized by an amount corresponding to the thickness of the spacer lower layer, creating a space between it and the anodic oxide film. (Figure g). Taking advantage of this, we formed an Au-Ge-Ni based alloy only in the mesa region with a thickness less than the thickness of the spacer lower layer using a vacuum evaporation method to ensure separation between the electrodes. At this time,
The thickness of the ohmic source and drain electrodes 3 and 4 shown in FIG.
In this way, a predetermined space will be present between the upper ends of the source and drain electrodes 3 and 4 on the gate side and the lower end of the compound film 5' of the gate electrode 5 itself. Even if the ohmic metal is deposited on the side surface of the compound film 5' during vacuum deposition (at the edge of the wafer, the vacuum deposition is performed from a direction slightly tilted from the vertical upward direction), metal adhesion to the side surfaces is likely to occur), source and drain electrodes 3, 4
However, there is no chance of any contact with the ohmic metal on the upper surface of the compound film 5'. Finally, alloying was performed at 400° C. for 2 minutes in N ₂ gas (containing 5% H ₂ ) to improve the ohmic properties of the source electrode 3 and drain electrode 4 (see h in the figure).

As a result of the above, we have achieved a MESFET with an extremely fine structure with a gate length of 1.0 μm, a source-to-gate distance, and a gate-drain distance of approximately 0.1 μm.

As another example, after the process shown _{in FIG} . Etch 2000Å (g' in the same figure). Thereafter, an ohmic electrode was formed under the same conditions as in the above example, and an FET was manufactured. In this example, we were able to miniaturize the gate length to 0.6 μm from a sample with the same structure as in the former example, and also ensured the separation between the gate and the ohmic electrode (h' in the same figure). .

In the present invention, the semiconductor materials are not limited in any way, and include GaAs as in the embodiment,
It can be widely applied to single-element semiconductors such as Si and other compound semiconductors. Therefore, the metal for the shot electrode can be selected depending on the respective semiconductor material. The same applies to ohmic electrodes. On the other hand, spacers also have vertical walls.
The purpose is to form a pattern with a size of about 1 μm in a thick film, and reactive sputter etching using reactive gas plasma is most suitable for this purpose. In the example, a film made of organic material was used, so O ₂ gas was used for etching, but it is also possible to use an inorganic compound for the spacer, and in this case, it should be noted that reactive sputtering using CHF ₃ gas is possible. do. The method of forming an insulating compound on the gate metal itself is not limited to anodic oxidation, but it is also possible to form an oxide film by plasma oxidation, thermal oxidation, etc., or to form a nitride film by plasma nitridation, etc. be. The purpose of the present invention can be achieved by selecting a method that can form a compound film that is chemically stable and has excellent uniformity, electrical insulation, etc. with respect to the metal used as the gate electrode.

On the other hand, as a semiconductor material, an ion-implanted layer is also possible in addition to an epitaxial layer. Furthermore, in the present invention, ion implantation is performed after the steps in FIGS. 4-e, 4-f, and 4-g to form an ohmic electrode region.
N ⁺ layer reduces resistance of ohmic electrode part,
It should be added that the structure allows for improved device performance. However, after ion implantation into the shot metal, 800
It is necessary to select materials that will not destroy the shot barrier type junction even after heat treatment at temperatures above ℃.
Examples include W, Mo, and alloys thereof.

As described above, the present invention has the following effects.

The present invention is characterized in that an insulating compound, such as an oxide, is formed with high precision on the side surface of the shot metal itself. At this time, the compound layer grows from the initial surface of the base metal to approximately the same thickness on both sides, so the gate length of the shot electrode is automatically shortened by an amount equal to the thickness of the compound layer, which has the effect of shortening the gate length. .

According to the present invention, the distance between the source and the gate is equal to the thickness of the compound film and can be controlled with high accuracy of 1/10 μm or less due to the characteristics of the formation method. (With the anodic oxidation method as in the example, it is extremely easy to control the film thickness within ±5% of the set value, which is about 1/10 or less of the control accuracy in normal wet etching or plasma etching.)
Therefore, by controlling the compound film thickness with high precision, the gate length can also be controlled with high precision.

According to the present invention, the source-gate electrode spacing is 1/10μ equal to the precisely controlled compound film thickness.
The order is m. This significantly reduces the parasitic resistance between the source and gate, and in combination with the effect of shortening the gate length, the MESFET characteristics are broadened to a higher frequency range.

According to the present invention, it is clear that the gate length and the source-to-gate distance can be easily controlled in the submicron range even by ordinary photolithography technology, and furthermore, the present invention can be used to achieve a resolution of 1 μm or less. If combined with lithography technology, it will be possible to fabricate MESFETs with even finer patterns.

A high electric field region is formed between the drain electrode and the gate electrode. If the two electrodes are too close together, the breakdown voltage of the transistor will decrease. According to the invention, the figure -
The distance between the electrodes can be controlled by performing diagonal deposition at an angle of 10° to 20° from the source electrode side in step h or 4-h'.

[Brief explanation of drawings]

FIG. 1 is a process explanatory diagram showing a general manufacturing method of MESFET, FIG. 2 is an example of a conventional method using a self-alignment method in manufacturing MESFET, and FIG. 4 is a cross-sectional view showing the structure of a MESFET to be manufactured, and FIG. 4 is a process explanatory diagram showing an embodiment of the present invention. 1...Substrate, 2...Semiconductor material operating layer, 3...
Source electrode, 4...Drain electrode, 5...Gate electrode, 5'...Metal compound film for gate electrode (aluminum oxide in the example), 6...Spacer,
6'... Spacer lower layer, 7... Metal film mask pattern (for processing 6, 6'), 8... Insulating film.

Claims (1)

[Scope of Claims] 1. A step of forming a two-layer thick film pattern having a vertical wall surface and an insulating material as a lower layer on a surface of a semiconductor material other than a portion where a shot gate electrode is to be formed; a step of burying metal for a shot gate electrode in a portion where the metal is not present, and forming an insulating film thereon; a step of removing an upper layer of the thick film pattern to expose an upper side surface of the shot gate electrode; a step of forming an insulating compound film made of the electrode material itself; a step of removing the insulating film formed on the lower layer of the thick film pattern and the upper surface of the shot gate electrode; and depositing an ohmic metal from above. Using the shot gate electrode and the insulating compound film as a mask, an ohmic electrode thinner than the lower layer of the thick film pattern is formed on the surface of the semiconductor material on both sides thereof, and at the same time, an ohmic metal film is formed on the top surface of the shot gate electrode and the insulating compound film. A method of manufacturing a field effect transistor, comprising: forming a field effect transistor. 2. The step of removing the insulating film formed on the lower layer of the thick film pattern and the upper surface of the shot gate electrode is as follows:
2. The method of manufacturing a field effect transistor according to claim 1, further comprising the step of laterally etching the lower side surface of the shot gate electrode exposed by removing the lower layer of the thick film pattern.