JPH0117298B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital multiplex converter using a staff synchronization method, and relates to a staff synchronization method that speeds up the pull-in time of a voltage-controlled oscillator when synchronization occurs on the receiving side and synchronization is restored again.

A staff synchronization method is generally used when multiplexing a plurality of asynchronous digital signals to transmit a single signal with a high frequency.

FIG. 1 shows a block diagram of a conventional digital multiplex converter using a staff synchronization method, where A indicates a transmitting section and B indicates a receiving section.

In the figure, 1 and 2 are transmission channel sections, and 3 and 14 are bipolar/unipolar conversion sections (hereinafter referred to as B/U
CONV), 4 and 22 are buffer memories,
5 and 15 are timing extractors, 6 is a phase comparator,
7 is a multiplexing section, 8 is a staff control circuit (adjustment control circuit), 9 is a multiplexing section, 1
0 is the main oscillator, 11 is the transmitting side clock generation circuit,
12 and 24 are unipolar/bipolar converters (hereinafter referred to as U/B CONV), 16 is a receiving side clock generation circuit, 17 is a frame synchronization circuit, 13, 1
8 is a separation unit, 19 is a destaph control circuit, 20,
21 is a receiving channel section, 23 is a phase synchronization circuit,
25 is an AIS signal generator.

In operation, the bipolar code input low-order group signal input from SIN is converted into a unipolar code by B/U CONV 3, and the timing pulse extracted from this signal by timing extractor 5 is written into buffer memory 4. On the other hand, a synchronization signal frequency that is slightly higher than the input low-order group frequency is inputted from the transmitting side clock generator 11 to the staff control circuit 8, and the pulses generated by the synchronization signal frequency are used to control the signal written in the buffer memory 4 as described above. read. At this time, by inserting a stuff pulse, the frequency deviation of multiplexing in the multiplexer 9 is absorbed.
At this time, information as to whether a stuff pulse is inserted or not is separately superimposed on the multiplexed signal as a staff designation pulse. Further, frame pulses and various service pulses for synchronization on the receiving side are also superimposed on the multiplexed signal. The multiplexed signals sent from each of the transmission channel sections 1, 2, etc. are multiplexed by the multiplexing section 9, converted into bipolar codes by the U/B CONV 12, and sent to the receiving side. On the receiving side, the B/U CONV 14 converts it into a unipolar code, and the timing pulse extracted by the timing extraction circuit 15 operates the receiving side clock generation circuit 16, and the frame synchronization circuit 17 synchronizes with the transmitted frame pulse. The signal is separated into each channel by the separation section 18. On the other hand, the staff designation pulse is detected and the staff pulse is separated from the signal. After being separated into each channel by the separation unit 18, it is written to the buffer memory 22, but the write clock from the de-staff control circuit 19 is prohibited where staff pulses, staff designation pulses, frame pulses, etc. are inserted. It is removed by doing this. The signal written in the buffer memory 22 is read out as a low-order group original signal by the readout clock smoothed by the voltage controlled oscillator in the phase synchronization circuit 23, and converted into a bipolar code by the U/B CONV 24. and sent from ROUT.
At this time, the write clock and the read clock are compared by a phase comparison circuit in the phase synchronization circuit 23, and the read clock is made to follow the frequency of the input low-order group signal on the transmitting side. However, if synchronization occurs in the receiving-side separation unit 13 for some reason, the signals will not be separated accurately and the frequency of the write clock from the de-staff control circuit 19 will change to that of the voltage-controlled oscillator in the phase-locked circuit 23. It ends up staying out of the pull-in range. In this state, even after synchronization is restored, it takes time for the voltage controlled oscillator to pull in, so there is a drawback that it takes time for the output signal from ROUT to return to normal.
Furthermore, when the separation unit 13 is out of synchronization, it is generally detected by the AIS signal (alarm indication signal, usually all "1") generator 25, and the out-of-synchronization is notified by sending the AIS signal to the lower order group. However, when the voltage controlled oscillator in the phase locked loop circuit 23 is out of the pull-in range, the frequency of the output signal to the lower order group of ROUT is also shifted, so the lower order group equipment cannot receive the AIS signal. There is a drawback that reception may not be possible.

An object of the present invention is to eliminate the above-mentioned disadvantages by using a repeating waveform of approximately the average staff frequency to set the center frequency of the voltage controlled oscillator to approximately the same frequency as before the loss of synchronization when a loss of synchronization occurs on the receiving side. To provide a staff synchronization system in which when a low-order group device can receive an AIS signal and synchronization returns again, a voltage controlled oscillator is immediately pulled in and the communication state immediately returns to normal.

In order to achieve the above object, the present invention is a multiple converter using a staff synchronization method. When an out-of-synchronization occurs on the receiving side, a repetitive waveform of about the average staff frequency is used to control the de-staff control circuit, and the average staff frequency is By prohibiting writing at a certain rate, the voltage controlled oscillator is made to have almost the same frequency as before it lost synchronization, allowing low-order devices to receive AIS signals and quickly when synchronization is restored again. It is characterized by the ability to pull in the voltage controlled oscillator.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a staff-synchronized digital converter according to an embodiment of the present invention, in which A is a transmitter;
B is a receiving section, and FIG. 3 shows a block diagram of the phase locked circuit.

Components in the figure that have the same functions as those in FIG. 1 are indicated by the same symbols. 26 is a phase comparison circuit, 27 is a low frequency filter, 2
8 is an amplifier, 29 is a voltage controlled oscillator, 30 is a rectangular wave generating circuit with a frequency approximately equal to the average staff frequency,
17' is a frame synchronization circuit, and 19' is a destaft control circuit.

The difference between FIG. 2 and FIG. 1 is that a rectangular wave generating circuit 30 with a frequency approximately equal to the average staff frequency is provided in the receiving section shown in B to prevent out-of-synchronization between the frame synchronization circuit 17' and the de-staff control circuit 19'. In this case, the only difference is that a function for inhibiting the write clock from the destaft control circuit 19' with a rectangular wave from the rectangular wave generating circuit 30 is added. The normal operation is therefore the same as described above. However, if synchronization occurs in the receiving section separation section 13, it is detected by the frame synchronization circuit 17', and the de-staff control circuit 19' is controlled, and the clock from the receiving side clock generation circuit 1 is changed to a frequency approximately equal to the average staff frequency. The clock from the rectangular wave generating circuit 30 controls the write clock from the destuff control circuit 19', and writing to the buffer memory 22 is prohibited at a rate of about the average stuff rate. As a result, the frequency of the voltage controlled oscillator 29 becomes almost the same as the frequency before the loss of synchronization. Therefore, from the AIS signal generator 25
Since the AIS signal is read by the clock of that frequency and transmitted from ROUT to the low-order group device, the low-order group device can reliably receive the AIS signal, and the synchronization will not occur at the high-order group receiving section in Figure 2B. It can be seen that Next, when the loss of synchronization is restored, the frame synchronization circuit 17' detects this and controls the destuff control circuit 19' to stop inhibiting using the clock from the rectangular wave generation circuit 30. As a result, the write clock from the destaft control circuit 19' returns to its original state and is input to the phase comparator circuit 26 in FIG. At this time, the voltage controlled oscillator 29 is oscillating at a frequency close to this frequency, so it immediately pulls in the write clock that has returned to its original state, returns to the normal state, and enters a normal communication state.

As explained in detail above, according to the present invention, even if synchronization occurs on the receiving side due to an abnormal condition at any point between the sending side and the receiving side,
The low-order group device can reliably receive AIS signals, and when the out-of-synchronization returns, it immediately returns to normal and has the effect of greatly shortening the time it takes for communication to stop.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional staff type digital multiplex converter, Figure 2 is a block diagram of a staff type digital multiplex converter according to an embodiment of the present invention, and Figure 3 is a block diagram of a phase locked circuit. be. In the figure, 1 and 2 are transmission channel sections, 3 and 14 are B/U CONV, 4 and 22 are buffer memories,
5 and 15 are timing extractors, 6 is a phase comparator,
7 is a multiplexing section, 8 is a staff control circuit, 9 is a multiplexing section, 10 is a main oscillator, 11 is a transmitting side clock generating circuit, 12 and 24 are U/B CONVs, 16 is a receiving side clock generating circuit, 17, 17' is a frame synchronization circuit, 13 and 18 are separation units, and 19 and 19'
is a destatus control circuit, 20 and 21 are reception channel sections, 23 is a phase synchronization circuit, 25 is an AIS signal generator, 26 is a phase comparator circuit, 27 is a low frequency amplifier,
28 is an amplifier, 29 is a voltage controlled oscillator, and 30 is a square wave generator.

Claims (1)

[Scope of Claims] 1. A de-staff control circuit for controlling a write pulse for selectively writing the received signal to a buffer memory by referring to a received signal of a digital multiplex converter using a staff synchronization method; In a receiving side device having a phase synchronization circuit that generates a clock pulse for reference and reading out the received signal from the buffer memory, a rectangular wave generation circuit that generates a repetitive waveform approximately equal to the average stuff frequency is provided, and a rectangular wave generation circuit is provided to generate a repeating waveform approximately equal to the average stuff frequency. A staff synchronization system characterized in that, upon detection of this, control of the write clock of the destaff control circuit is switched to control that refers to the output of the rectangular wave generation circuit.