JPS59835Y2 - Communication system converter for digital communication system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a conversion device for interconnecting digital communication systems with different clock frequencies.

In digital communication systems, signals are transmitted and received in synchronization with the system's clock.

Therefore, if the clock frequencies of the two systems are the same, by synchronizing both clocks, it is possible to mutually transmit information without dropping or duplicating signals, but if the clock frequencies of the two systems are different, then , clock-by-clock synchronization becomes impossible, and some other means must be used.

However, in the PCM communication system, which samples audio at regular intervals, encodes the amplitude value into a digital value, and then time-division multiplexes this signal, various clock frequencies can be used depending on the number of multiplexes and the format of the frame synchronization signal. These include, for example, a 24-channel audio multiplexing system with a clock frequency of 1.544 Mb/s (hereinafter referred to as 1.5M system).

) 30-channel audio multiplexing system with a clock frequency of 2.048 Mb/s (hereinafter referred to as 2M system).

) etc. In order to interconnect communication systems having different lock frequencies, a method has generally been used in which the output of one system is once decoded into an analog waveform and then digitized again by the encoder of the other system.

However, with such a configuration, code and decoding devices of both types are required at mutual connection points, and the devices require many parts and reliability also decreases.

Furthermore, repeating encoding and decoding causes deterioration of signal quality.

Alternatively, if the signal to be transmitted is not an analog waveform such as voice, but is originally a digital value, it is impossible to connect using the analog value as an intermediary as described above.

The present invention aims to solve these drawbacks by synchronizing the two systems at a frequency that is a common divisor of the different clock frequencies, and controlling the clock oscillator of the receiving system to maintain this synchronized state. This makes it possible to interconnect communication systems with different clock frequencies.

The features of the present invention for achieving this purpose include extracting a clock frequency from a time-division multiplexed input signal as a first clock frequency, temporarily storing information of one frame of the signal in a digital storage circuit, and A control oscillator that oscillates a second clock frequency that has no integer relationship with the first clock frequency or a divided frequency thereof using a divided output obtained by dividing the clock frequency, and a time division multiplexed output signal according to the second clock frequency. The present invention is aimed at a conversion device that converts the communication system of a digital communication system by reading out and transmitting the contents of the digital storage circuit according to the frame structure of the digital communication system.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a conversion device used in the present invention, and only one direction is shown.

In the figure, 1 is a signal input terminal connected to the other digital communication system with a different clock frequency, 2 is a receiver that converts the input signal into a waveform convenient for internal processing, and 3 is a clock extraction circuit that extracts the clock from the input signal. , 4 is receiver 2
5 is a frequency dividing circuit that divides the clock output from 3, and 6 is a voltage that oscillates the clock frequency of the receiving system. Control oscillator, 7 is a frequency dividing circuit that divides the output of 6, 8 is a phase comparison circuit that compares the phases of the output pulse of 5 and the output pulse of 7, and generates the control voltage of 6 based on the result, 9 is a 6 an address generation circuit for reading the signal stored in 4 by the clock output of 10;
is a transmitter that transmits the signal read from 4 from the signal output terminal 11 at a predetermined converted clock frequency.

Next, the operation of the device shown in Figure 1 will be explained using the PCM 1.5M system.
A case of converting to the M method will be explained.

Figures 2A and 2B show allocations for the 1.5M system and 2M system. In the 1.5M system, as shown in Figure 2A, one audio channel has an 8-bit structure, and one frame has 24 audio channels and 1 frame. It consists of a bit synchronization pulse S, and the frame repetition frequency is 8kHz (period: 125μs).
), the number of bits in one frame is 193 (=8X24+1
), clock frequency is 1,544MHz (8kHzx
193), and the 8th bit of each channel becomes a telephone signal bit every 6 frames.

On the other hand, in the 2M system, as shown in Figure 2B, one audio channel has an 8-bit configuration, and one frame consists of 30 audio channels, a frame synchronization channel (O channel), and a telephone signal channel (16th channel). The frame repetition frequency is 8 (period 125 μs), the number of bits in one frame is 256 (= 8, x 32),
The clock frequency is 2.048MHz (8kHz
256).

Therefore, when editing channels, instead of sequentially replacing 1.5M channels with 2M channels,
It is necessary to edit according to the frame structure (channel allocation) of the 2M system.

In Figure 1, 1, 5 input from signal input terminal 1
The M-system PCM signal is extracted by the clock extraction circuit 3 as the clock of the input signal as a first clock frequency, and is stored in the temporary storage circuit 4 via the receiver using this clock.

The temporary storage circuit 4 has storage elements with the number of words equal to the number of audio channels of the input PCM system, and signals are sequentially written in accordance with the channel number of the input PCM.

Note that the number of bits of a memory element for one word is equal to the number of bits of an audio channel.

In the frequency dividing circuit 5, the output of the clock extraction circuit 3 is 1.
, 544MHz is divided by 193 to obtain an 8kHz pulse.

For voltage controlled oscillator 6, initially approximately 2.048 MHz
Since it is oscillating, its output is divided into 256 by the frequency dividing circuit 7.
Divide the frequency to obtain an 8kHz pulse.

The phase comparison circuit 8 generates a voltage that lowers the oscillation frequency of the voltage controlled oscillator 6, and vice versa, if the phase of the output coverage of the frequency division circuit 7 is advanced with respect to the output coverage of the frequency division circuit 5. If the phase of the output pulse is delayed, a voltage is generated that increases the oscillation frequency.

In this way, the oscillation frequency of 6 will be divided by 7 and the phase will be compared again at 8, so the output pulse of 5 and the output pulse of 7 will be in a state where there is no lag in phase, that is, they are synchronized. will be removed.

The address generation circuit 9 creates frame timing based on the clock frequency of the oscillator 6, and sequentially instructs the address of the temporary storage circuit 4 according to the frame configuration of the output signal.
The contents of the memory circuit are read out, and the output signal is converted into a transmission waveform by the transmitter 10 and sent out from the terminal 11 onto the transmission path.

In this way, the frame repetition period completely matches the input and output of the temporary memory circuit 4, so the 2M address generation circuit 9 sequentially receives signals from the memory elements of each word of the temporary memory circuit according to its own frame configuration. All you have to do is read it out, and by the time it is read out in the next frame, a new signal will have been written into the corresponding memory element from the receiver 2, and situations such as missed signal reading or double reading will not occur.

Here, in order to interconnect the two systems and transmit information, voice channel signals, telephone signal information, frame period signals, etc. are required, but these signals are unique depending on the output side system. is reproduced or generated and added to it.

The number of audio channels that can be transmitted is 24 using the 1.5M system.
Since there are 30 channels in the 2M system, the effective information bit rates that can be transmitted are 192 bits per second and 240 bits per second, respectively, assuming 8 bits per channel.

Therefore, if 1.5M system 1 system and 2M system 1 system are connected, 24 out of 30 channels of 2M system will be connected.
In principle, it is inevitable that only channels can be used.

However, if a plurality of both systems are used to face each other, such as 2M system 4 systems synchronized to the same clock and 1,5M system 5 systems synchronized to the same clock, it becomes possible to connect them efficiently.

Here, the receiver 2 converts a manual waveform, such as a binary waveform, into a waveform convenient for writing into a temporary storage circuit, such as an NRZ waveform, and is known as a part of the PCM terminal equipment [e.g. Yamamoto, Murakami, PCM Terminal, Journal of the Institute of Electrical Communication Engineers, Vol. 49, No. 11 (November 1960)
P47-52].

The clock extraction circuit 3 can be easily constructed from a tank circuit formed from an element such as an LC.

The temporary storage circuit 4 can be composed of a semiconductor integrated circuit or a random access memory of a core memory.

The frequency dividing circuit 5 can achieve frequency division by 193 by applying feedback to the 8-stage binary counter so as to reset it at the 194th count pulse, and the frequency dividing circuit 7 can achieve 193 frequency division by applying feedback to the 8-stage binary counter to reset it with the 194th count pulse. That's fine.

The phase comparison circuit 8 and the voltage controlled oscillator 6 are collectively known as a phase controlled oscillator.

(Byrne, Proprerities and
Design of the Phase Cont.
rolled 0scillator with
aSawtooth Comparator, Be
11 System Tech, J.

vol, 44 (Nov, 1965), pp.
1843-1885] Note that a low-pass filter may be inserted between the phase comparator circuit 8 and the voltage controlled oscillator 6 in order to stabilize the oscillation waveform.

The address generation circuit 9 is easily constructed from a logic circuit, a counter, and the like.

The transmitter 10 sends the output waveform of the temporary storage circuit 4 to the output terminal 11 as a waveform suitable for a transmission path, such as a binary waveform, and can be configured by a known conversion circuit in a PCM terminal device, for example. .

FIG. 3 shows a block diagram of another embodiment of the conversion device according to the invention.

The difference between the embodiment shown in FIG. 3 and the embodiment shown in FIG. 1 is that in the embodiment shown in FIG. )
, the output thereof is directly applied to the phase comparison circuit 8, and in connection with this, the output of the voltage controlled oscillator 6a is multiplied by the multiplier circuit 12 to obtain a second clock frequency.

The 8 kHz output from the voltage controlled oscillator 6a is synchronized with the frame repetition frequency of the PCM signal input from the terminal 1.

The multiplier circuit 12 can be configured by a known circuit, and multiplies the output of the voltage controlled oscillator 6a by 256 to 2.048 MHz.
This is used as the second clock frequency for the output side PC.
This is the clock frequency of M.

Note that the conversion from the 2M system to the 1.5M system can be realized by a configuration similar to the circuit shown in FIG. 1 or 3.

As explained in detail in the embodiments above, according to the present invention, the input PCM signal and the output PCM signal are synchronized by the frame repetition frequency (-8kHz), which is a common divisor of their clock frequencies. Problems such as input signal dropouts and double feeds do not occur at all.

Even if the clock frequency of the input PCM deviates slightly, the clock frequency of the output PCM remains out of synchronization with the input PCM due to the operation of the phase-controlled oscillator, so that information is transmitted smoothly.

Furthermore, according to the present invention, all signals are received and received in digital format, so there is no deterioration in signal quality.

The present invention is particularly effective when the source information is not in an analog format such as voice, but in a digital format such as data.

Further, according to the present invention, the device can be realized using a relatively small number of integrated circuits, so that the device can be made smaller and more reliable.

[Brief explanation of the drawing]

1 and 3 show block diagrams of two embodiments of apparatuses to which the present invention is applied, and FIG. 2 shows allocations of 1, 5 MPCM and 2 MPCM systems to which the present invention is applied. Explanation of symbols 1...Signal input terminal, 2...
...Receiver, 3...Clock extraction circuit, 4...
... Temporary memory circuit, 5 ... Frequency division circuit, 6,
6a... Voltage controlled oscillator, 7... Frequency divider circuit, 8... Phase comparison circuit, 9... Address generation circuit, 10...・Transmitter, 11...
...Signal output terminal, 12... Multiplier circuit.

Claims (1)

[Claims for Utility Model Registration] A first time division multiplexed signal having a first frequency as a clock frequency has the same frame repetition frequency as the first time division multiplexed signal but a different frame structure, and In a communication system conversion device that converts the first time division multiplexed signal into a second time division multiplexed signal whose clock frequency is a second frequency that is not an integral multiple of the first frequency, a clock extraction circuit for extracting the first frequency; a temporary storage circuit for sequentially storing information for at least one frame of the first time division multiplexed signal using the output signal of the clock extraction circuit; a frequency divider that divides the output signal of the clock extraction circuit into the frame repetition frequency; a controlled oscillator that can control the oscillation frequency for creating the second frequency; a phase comparison circuit that compares the phase of a signal equal to the frame repetition frequency obtained by frequency division with the output signal of the frequency divider and controls the controlled oscillator so that both are in phase; The address of the frame information is obtained directly or by multiplying the output signal of the controlled oscillator so that the frame information is read out sequentially in an order according to the frame configuration of the second time division multiplexed signal. 1. A conversion device for a communication system in a digital communication system, characterized in that the conversion device comprises an address generation circuit that outputs an output to the temporary storage circuit at a frequency of 2.