JPS6330822B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention uses a digital multiplex converter to transmit data by synchronizing it with a synchronized clock for multiplexing an empty time slot and placing an asynchronous signal on the empty time slot. The present invention relates to a data transmission system that allows a receiving side to accurately and easily extract a timing signal of asynchronous data when the number of samplings cannot be increased due to a synchronization clock for multiplexing the asynchronous signal.

(b) Prior art and problems Figure 1 is a frame configuration diagram of a 30CHPCM multiplex converter, and Figure 2 is a time chart when an asynchronous signal is superimposed and transmitted using a conventional 30CHPCM multiplexer (A ) is an asynchronous signal with a repetition rate of 2.4KHz, (B) is a sampling pulse with a frequency of 4KHz,
(C) shows a signal in which an asynchronous signal is superimposed on time slot A, and (D) shows a signal in which the asynchronous signal is separated on the receiving side.

An example will be explained in which a 30CH PCM multiplex conversion device superimposes and transmits a 2400bps asynchronous signal.

As shown in Figure 1, the frame structure of the 30CH PCM multiplex conversion device is as follows: every two frames with a repetition frequency of 4KHz, a 1-bit game warning signal area indicated by x is followed by a 1-bit A and B time slot each. There is an empty area indicated by . When an asynchronous signal is superimposed and transmitted, the empty time slot A or B is used for transmission.

Now, when using the conventional method to superimpose the 2400bps asynchronous signal (data is 1, 0, 1, 0...) shown in Figure 2A onto an empty time slot, the 2 frames shown in Figure 2B are superimposed on an empty time slot. The signals are sampled using a sampling pulse having a repetition frequency (synchronization clock for multiplexing) of 4KHz, and are superimposed and transmitted as shown in FIG. 2C. When the signal superimposed on this empty time slot A is demultiplexed and extracted on the receiving side, compared to the length of the first 1, 0 level signal as shown in Figure 2D, the next 1 level signal is The signal will be 1/2 the length. In this way, if the difference between the repetition frequency (2400Hz) of the asynchronous signal and the sampling frequency 4KHz is small and the number of samplings is small, the ratio of the length of the long signal to the short signal is large, and the receiving side uses a phase-locked circuit (hereinafter referred to as a PLL circuit). ) to obtain a timing signal with a repetition frequency of 2400 Hz for an asynchronous signal, the distortion is large and it is extremely difficult to obtain it. The conventional method has such drawbacks.

(c) Object of the Invention In view of the above-mentioned drawbacks, the object of the present invention is to minimize the difference between the repetition frequency of the asynchronous signal and the frequency of the multiplexing synchronization clock, so that the number of times one frame of the asynchronous signal is sampled is at least An object of the present invention is to provide a data transmission system that allows a timing signal of the asynchronous signal to be accurately and easily extracted on the side.

(d) Structure of the Invention In order to achieve the above object, the present invention multiplexes the asynchronous signal by performing a logical product of the repetition frequency pulse of the asynchronous signal, the multiplexing synchronization clock, and the asynchronous signal. The signal indicating the valid signal among the valid signal and invalid signal of the asynchronous signal, which is generated by performing the AND operation, is synchronized with the synchronization clock for synchronization and transmitted on the first empty time slot. By taking the AND of the pulse of the repetition frequency of the signal and the synchronization clock for multiplexing, the signal is placed in the second empty time slot and transmitted, and on the receiving side, the signal is placed in the second empty time slot and transmitted. The present invention is characterized in that the effective signal is extracted and the timing signal of the asynchronous signal is extracted by outputting the multiplexing synchronization clock during the effective signal section.

(e) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings. FIG. 3 is a block diagram of a main part on the transmitting side of a 30CH PCM multiplexing apparatus according to an embodiment of the present invention, and FIG. 4 is a block diagram of a main part on a receiving side of a 30CH PCM multiplexing apparatus according to an embodiment of the present invention. FIG. 5 is a time chart of the signals of each part in FIGS. 3 and 4, where A is an asynchronous signal sent in time slot A, B is a signal indicating a valid signal sent in time slot B, and C is a signal of AND circuit 11. Shows the output signal.

In the figure, 1 and 10 are counters, 2 is a 2.048MHz oscillator, 3 is a multiplexing circuit, 4, 5, and 11 are AND circuits, 6 is a unipolar/bipolar conversion circuit (hereinafter referred to as the U/B conversion circuit), and 7 is a Bipolar/unipolar conversion circuit (hereinafter referred to as B/U conversion circuit),
8 is a frame synchronization circuit, 9 is a demultiplexing circuit, 12
1 is a memory, and 13 is a PLL circuit.

An example will be explained in which a 30CH PCM multiplex conversion device superimposes and transmits a 2400bps asynchronous signal.

In FIG. 3, the signal from the 2.048 MHz oscillator 2 is input to the counter 1 and the U/B conversion circuit 6. The counter 1 transmits various timing clocks to the multiplexing circuit 3 using a 2.048 MHz signal, and also transmits a 2400 Hz clock to the AND circuits 4 and 5. Also, a 4KHz multiplexing synchronization clock is transmitted to the AND circuit 4 at the timing to be placed on time slot A in FIG. 1, and to the AND circuit 5 at the timing to be placed on time slot B in FIG.
Data, synchronization signals, etc. are directly input to the multiplexing circuit 3 and multiplexed. The 2400 bps asynchronous signal is input to the AND circuit 4, ANDed with the 2400 Hz clock and the 4 KHz clock placed on time slot A, and transmitted to the multiplexing circuit 3.
In this case, the bit rate f ₁ of the asynchronous signal is 2400 and the bit rate f ₂ of the multiplexed synchronous signal is 4000, so
f ₁ /f ₂ = 3/5, so on average 2 out of 5 time slots are empty time slots.If we focus on time slot A, the part A in Figure 5A is valid with valid data. This is a signal part, and the part (b) is an empty data part. To obtain the signal indicating this valid signal, we perform the logical product of the 2400 Hz clock input to the AND circuit 5 and the 4 KHz clock at the timing to be placed on time slot B. As shown in B in the figure, a signal is obtained in which the portion indicating a valid signal is at 1 level and the vacant signal portion is at 0 level. If the outputs of the AND circuits 4 and 5 are input to the multiplexing circuit 3 and multiplexed, the outputs of the AND circuits 4 and 5 will be the first three timeslots of time slots A and B in FIG.
A signal indicating a valid signal is placed in the next two time slots A, and the next two time slots A are empty signals and time slot B is loaded.
is loaded with a signal indicating an empty signal, and becomes the frame structure shown in Figure 1 along with data and synchronization signals.
The signal is converted into a bipolar signal by the conversion circuit 6 and transmitted to the receiving side. On the receiving side shown in FIG. 4, the B/U conversion circuit 7 converts the signal into a unipolar signal, the frame synchronization circuit 8 synchronizes the signal, sends the received signal to the separation circuit 9, and extracts the 2.048MHz timing signal. The counter 10 sends various clocks to the separation circuit 9 and also sends a clock with a frequency of 4 KHz to the AND circuit 11.
The separation circuit 9 separates the data signal and the signals shown in FIG. 5A and B sent in time slots A and B, and separates the valid signal I of the signal shown in FIG. 5A sent in time slot A. The portion is stored in memory 12. Furthermore, the signal shown in FIG. 5B that has been separated by time slot B is sent to the AND circuit 11, and the part showing the effective signal as shown in FIG. A clock is output from the AND circuit 11 and sent to the PLL circuit 13 via the memory 12.The PLL circuit 13 extracts a timing clock of an asynchronous signal with a frequency of 2.4KHz, and stores it in the memory 12 using this 2.4KHz timing clock. Reads the valid signal that has been set and outputs an asynchronous signal. The three clock signals with a frequency of 4KHz shown in FIG. 5C outputted from the AND circuit 11 are accurate for each part showing the effective signal in FIG. It is possible to extract a KHz (4KHz x 3/5) clock signal.

Incidentally, since the time slot A of the empty signal portion RO in FIG. 5A is not used, another signal can be superimposed and used.

(f) Effects of the Invention As explained in detail above, according to the present invention, the difference between the repetition frequency of the asynchronous signal and the frequency of the multiplexing synchronization clock is small, and the number of times one frame of the asynchronous signal is sampled is small. Even if multi-point sampling is not possible, the receiving side can accurately and easily extract the timing signal of the asynchronous signal.

[Brief explanation of drawings]

Fig. 1 is a frame configuration diagram of a 30CHPCM multiplex conversion device, Fig. 2 is a time chart when an asynchronous signal is superimposed and transmitted in a conventional 30CHPCM multiplex conversion device, and Fig. 3 is a 30CHPCM multiplexing diagram of an embodiment of the present invention. FIG. 4 is a block diagram of the main part of the transmitting side of the converter, FIG. 4 is a block diagram of the main part of the receiving side of the 30CH PCM multiplex converter according to the embodiment of the present invention, and FIG. 5 shows the signals of each part of FIGS. 3 and 4. This is a time chart. In the figure, 1 and 10 are counters, 2 is a 2.048MHz oscillator, 3 is a multiplexing circuit, 4, 5, and 11 are AND circuits, 6 is a unipolar/bipolar conversion circuit, 7 is a bipolar/unipolar conversion circuit, and 8 is a frame synchronization circuit. 9 is a separation circuit, 12 is a memory, and 13 is a phase locked circuit.

Claims (1)

[Scope of Claims] 1. In a data transmission method in which an asynchronous signal is synchronized with a multiplexing synchronization clock and transmitted in an empty time slot in a digital multiplex converter, pulses of the repetition frequency of the asynchronous signal and the multiplex Synchronize the asynchronous signal with the multiplexing synchronization clock by taking the AND of the synchronization clock for multiplexing and the asynchronous signal, transmit it on the first empty time slot, and take the AND of the above. Of the valid signal and invalid signal of the asynchronous signal generated by this, a signal indicating a valid signal is logically ANDed between the pulse of the repetition frequency of the asynchronous signal and the multiplexing synchronization clock. A data transmission method characterized in that the asynchronous signal is transmitted in a time slot, and on the receiving side, the timing signal of the asynchronous signal is extracted by outputting the multiplexing synchronization clock during the effective signal period.