JPH01133287A - Device and method for driving sense amplifier in dynamic random access memory - Google Patents

Abstract

PURPOSE:To make larger the potential difference between the line pairs of bits at the time of reading data, to stabilize the action of a sense amplifier, and to execute the action of the sense amplifier at high speed by transferring the potential change of one driving signal line to the other driving signal line at the time of reading memory cell data. CONSTITUTION:When a driving signal on a word line 3 reaches the threshold voltage of a transfer gate FET 5 in a memory cell 1, '1' is red from the cell 1. On the other hand, clock signals, the inverse of phiT and phiT are respectively at 0 and Vcc, FETs 38 and 42 of a potential change transfer circuit 44 are both conducted, the potential change generated in a driving signal line 17 is transmitted to a driving signal line 14. At this time, an FET 50 is potential-lowered with the discharge of a bit line 7 through an FET 19 and is conducted. Consequently, the potential change quantity is transmitted to the line 14 is transmitted to a bit line 2 through the FET 15, and the potential of the line 2 is further raised. As the result, the charge of the line 7 is transmitted to the line 2, the potential of the line 2 is changed equal to or more than the potential read from the cell 1, and the potential of the line 7 is gradually lowered. After that, when the potentials, the inverse of phiT and phiT are raised and lowered respectively, the lines 14 and 17 are separated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus and method for driving a sense amplifier circuit used in a dynamic random access memory or the like, and particularly relates to improving the amplification degree of the sense amplifier circuit.

[Prior Art] FIG. 9 is a diagram showing the overall general configuration of a reading section of a dynamic random access memory that has been conventionally used and to which the present invention is applied. In FIG. 9, the dynamic random access memory includes a memory cell array MA in which a plurality of memory cells for storing information are arranged in rows and columns, and an address that generates an internal address in response to an external address given from the outside. Buffer AB, an X decoder ADX that decodes the internal address signal from address buffer AB to select the corresponding row of the memory cell array, and an X decoder ADX that decodes the internal column address from address buffer AB to select the corresponding column of the memory cell array. Y decoder ADY and memory cell array MA for
detects and amplifies the information possessed by the selected memory cell, and outputs the output buffer O in response to the signal from the Y decoder ADY.
(sense amplifier + l10) Sl for transmitting to B,
(Sense amplifier +l10) includes an output buffer OB for receiving read data from SI and transmitting output data Dout to the outside. Further, a control signal generation system CG for generating control signals for controlling the timing of various operations of the dynamic random access memory is provided as a peripheral circuit.

Details of each control signal generated by the control signal generation system CG will be described later.

FIG. 10 is a diagram schematically showing the configuration of the memory cell array section shown in FIG. 9. In FIG. 10, memory cell array MA includes a plurality of word lines WLl, WL2 . ...
WLn and multiple bit lines BLO, BLO, BLI,
BLI, =・BLm, including BL seats. word line WLI,
. . . One row of memory cells is connected to each WLn. The bit lines constitute a folded bit line, and two bit lines constitute a bit line pair. That is, bit line B
L.O.

■The bottom of τ constitutes one bit line pair, and BLI and BLT are one
A pair of bit lines is formed, and the bit line BLm
, BLm form a bit line pair.

A memory cell 1 is connected to each bit line BLO, BLO, -BLm, BLm at the intersection with every other word line.

That is, in each bit line pair, a memory cell is connected to the intersection of one word line and one of the bit lines of the pair of bit lines. Each bit line pair is provided with a precharge/equalize circuit 150 for balancing the potential of each bit line pair and precharging it to a predetermined potential VB. Further, each bit line pair is connected to a signal φ8. A sense amplifier 50 is provided which is activated in response to φB to detect and differentially amplify the potential difference between the bit line pair. Each bit line is connected to Y decoder AD
In response to the address decode signal from Y, it is selectively connected to the data input/output bus ■10° and 70,000. That is,
Bi Nodo Line BLO.

BLO is connected to data input/output buses I10. through transfer gates TO and TO', respectively. Connected to I10. Similarly, bit lines BLI and BLI are connected to transfer gates T1. Data input/output bus I1 via TI'
0. Bit lines BLm and BLm are connected to data input/output buses I10 and Ilo via transfer gates Tm and Tm', respectively. An address decode signal from the Y decoder ADY is transmitted to the gates of each transfer gate TO, TO', -Tm, Tm'. This allows a pair of bit lines to be connected to the data input/output bus I.
10. It will be connected to I10.

FIG. 11 is a diagram showing a detailed configuration of one of the bit line pairs shown in FIG. 10 and a sense amplifier control circuit. However, in FIG. 11, only one word line is shown to avoid complication of the drawing.

A precharge/equalize circuit 150 for precharging a pair of bit lines 2.7 to a predetermined potential VB during memory standby and equalizing the bit line 2.7 potential to a predetermined potential responds to a precharge signal φP. N-channel insulated gate field effect transistors (hereinafter simply referred to as MOS transistors) transmit a predetermined precharge potential va to bit lines 2 and 7, respectively, and respond to an equalize signal φE applied via a signal line to electrically connect bit line 2.7, thereby bit line 2.7
N-channel MOS transistor 1 for equalizing potentials
It consists of 2. N-channel MO for precharging
Both S transistors 9 and 10 are turned on in response to a precharge signal φP applied via a signal line 11, and the precharge potential VB transmitted on the signal line 8 is turned on.
are transmitted onto bit lines 2.7, respectively.

The sense amplifier 50 that differentially amplifies the signal on the bit line 2.7 is a pair of p-channel MOS transistors whose gates and one electrode are cross-connected and connected to the bit line 2.7.
) transistors 15 and 16, and a pair of n-channel MOS transistors 18 and 19 whose one electrode and gate electrode are cross-connected and connected to the bit line 2.7, respectively. p-channel MOS transistor 15.1
The other electrodes of 6 are both connected to the signal line 14, and the signal φ^
receive. The other electrodes of n-channel MOS transistors 18 and 19 are connected to signal line 17 and receive signal φB on signal line 17.

The first sense amplifier drive signal line 14 has a p-channel that is turned on in response to a control signal φ that gives timing for activating the sense amplifier and transmits the power supply potential Vcc onto the first sense amplifier drive signal line 14. MOS) transistor 24 and an n-channel M transistor for keeping the first sense amplifier drive signal line 14 at a predetermined potential during the bit line precharge period.
An OS transistor 30 and a constant voltage generation circuit 100 are provided.

The second sense amplifier drive signal line 17 has an n-channel signal for connecting the second sense amplifier drive signal line 17 to the ground potential in response to a second control signal φ that provides timing for activating the sense amplifier. A MOS) transistor 27 is provided.

The p-channel MOS transistor 24 for charging the first sense amplifier drive signal line 14 to the power supply potential Vcc is
Sense amplifier activation signal φR is received at the gate via signal line 25, and power supply potential Vcc is received via signal line 26. An n-channel MOS transistor 27 for discharging the second sense amplifier drive signal line 17 to the ground potential receives a second sense amplifier activation signal φ via a signal line 28 at its gate.

The constant voltage generation circuit 100 connects the signal line 26 to the power supply potential Vcc.
a resistor 33, one terminal of which is connected via the resistor 3;
3 through a node 32;
OS) A diode-connected p-channel MOS) connected in series with transistor 35 via node 34; An n-channel MOS transistor 31 that transmits a predetermined potential to 29 is provided. The n-channel MOS) transistor 30 is turned on in response to the precharge signal φP, and the node 2
9 is transmitted onto the first sense amplifier drive signal line 14.

N-channel MOS transistor 35 has its gate and drain connected to node 32, and makes the potential of node 32 higher than the potential of node 34 by its threshold voltage V,N. P channel MOS transistor 36 has its gate and drain connected, and is also connected to precharge potential VB via signal line 8. Therefore, a voltage higher than the precharge potential Va by the absolute value of the threshold voltage vTe is applied to the node 34. Resistor 33 is node 3
Provided to supply only voltage to 2, several M to several 10
It has a large resistance value of MΩ. With this configuration, node 3
The potential of 2 is VB + l V7 p l + vT. n-channel MO3) transistor 31 has a threshold voltage VTN and therefore VB+1vTP to node 29
Transmits a potential of 1.

Memory cell 1 includes a transfer gate 5 whose gate is connected to word line 3 and whose source is connected to bit line 2, and a capacitor 6 connected to the drain of transfer gate 5 via node 4. Data of memory cell 1 is stored in node 4. That is, the node 4 is a so-called storage node.

When word line 3 is selected, word line drive signal Rn is transmitted, and transfer gate 5, which is an n-channel insulated gate field effect transistor, is turned on.
Information held by memory cell 1 is transmitted onto bit line 2 . Although the memory cell connected to the bit line 7 is not shown, no memory cell is provided at the intersection of the word line 3 and the bit line 7, so when the memory cell 1 is selected according to the configuration shown in FIG. The bit line 7 provides a reference potential for the bit line 2.

Bit lines 2 and 7 each have a parasitic capacitance ff120. 21, and the first sense amplifier drive signal lines 14 and 17 each have a parasitic capacitance ff122.23.

FIG. 12 is a waveform diagram for explaining the operation of the circuit configuration shown in FIG. 11. In FIG. 12, logic "1" data is stored in memory cell 1; The operation when reading out information "1" stored in is shown. In order to explain the data read operation from the memory cell 1, it is necessary to explain the operation from the previous cycle, so FIG. 12 also shows an operation waveform diagram from the previous cycle.

Hereinafter, with reference to FIGS. 11 and 12, the memory cell 1
The operation when reading the logic "1" data possessed by the memory will be explained.

By reading data from the memory cell connected to bit line 2 or bit line 7 in the previous cycle,
The potential of bit line 2 is now OV1, and the potential of bit line 7 is Vcc
Suppose that the state is as follows.

Of course, this state is not limited, and the opposite state may exist depending on the data of the memory cell read in the previous cycle. After the level of the word line (not shown) that selected the memory cell in the previous cycle becomes OV, the sense amplifier drive signals φ and 3φ start to fall and rise, respectively, at time to, and the MOS transistors 27 and 24 start to rise. Both become non-conductive, and the sense amplifier 50 is inactivated.

Next, at time t1, when the bit line balancing signal φE begins to rise, the equalizing MOS transistor 12 becomes conductive. As a result, charges move from the bit line 7 side with a high potential to the bit line 2 side with a low potential, and the potentials of the bit lines 2 and 7 are both balanced to Vcc/2. Each bit line 2
, 7 reaches Vcc/2, the sense amplifier drive signal line 14 and 17 are connected to each other.
The MOS transistor included in the sense amplifier drive signal line 14 conducts, and charges move from the sense amplifier drive signal line 14 having a high potential to the sense amplifier drive signal line 17 having a low potential. That is, the potential of the sense amplifier drive signal line 14 is set to the MOS transistor 1 by the bit line equalization potential Vcc/2.
Vc is higher by the absolute value of the threshold voltage VTP of 5.16
c/2+ l Vv p l, and on the other hand, the potential of the sense amplifier drive signal line 17 becomes a potential Vcc/2-VTN lower than the bit line equalization potential Vcc/2 by the threshold voltage VTN of the MOS transistor 18.19. .

Next, at time t2, the potential of the bit line 2.7 is set to V c
In order to stabilize it at the c/2 level, the precharge clock signal φP rises from 0 volts, which makes the precharge MO3I transistors 9 and 10 conductive, and the potential of Vcc/2. A power supply line 8 having a power supply line 8 is connected to a bit line 2.7. Here, the precharge potential Va is half of the operating power supply potential Vcc, that is, Vc
It is set to c/2.

At time t3, the rise of the precharge clock signal φP ends and the previous cycle operation ends.

Next, at time t4, in order to complete the balancing and charging of the bit lines 2 and 7 and start the current cycle, both the bit line equalization signal φE and the precharge clock signal φP start to fall, which causes the MOS transistor 9,
10.12 becomes non-conductive.

At time t5, when word line 3 is selected in response to the row address decode signal from the X decoder, word line selection signal Rn is transmitted onto word line 3, and the potential of word line 3 rises. As a result, the MOS transistor 5 becomes conductive and the charge accumulated in the capacitor 6 moves to the bit line 2 side, and the potential of the bit line 2 starts to rise. This change in the potential of the bit line 2 makes the MOS transistor 19 included in the sense amplifier 50 conductive, and as a result, the potentials of the bit line 7 and the sense amplifier drive signal lines 14 and 17 change accordingly.

The details of the potential changes of the bit line 7 and the sense amplifier drive signal lines 14 and 17 will be described later.

This potential change of the bit line 2 is minute (several 100 mV) and generally has a rise time constant of several tens of nanoseconds.

At time t6, the sense amplifier drive signal φ.

increases, and the sense amplifier 50 is driven to amplify this minute signal difference between the bit lines 2 and 7. At this time, in order to operate the sense amplifier 50 stably, it is preferable that the potential difference between its input signals, that is, the bit lines 2.7, be as large as possible. In order to increase the potential difference on the bit line 2°7, it is necessary to increase the time interval between time t5 and time t6, but in order to increase the data read speed of the memory cell, the time interval between time t5 and time t6 is increased. The interval is set to 15 to 25 nS.

At time t7, amplification of the signal potential difference by the sense amplifier 50 is completed, the potential of the bit line 7 becomes the ground potential, and the potential difference is further increased.

Next, at time t7, when the bit line charging signal φ similarly falls, the charging MOS transistor 24 is turned on, and the potential of the sense amplifier drive signal line 14 rises to the power supply potential Vcc. As a result, the MO of the sense amplifier 50
The potential of bit line 2 is also charged to the power supply potential Vcc level via S transistor 15. This completes the sensing operation by the sense amplifier 50. Here the signal φ.

The operation triggered by the signal φ is sometimes distinguished from the sense operation, and the operation triggered by the signal φ is sometimes distinguished from the restore operation, but in the following description, both are defined as the sense operation.

After the potentials of the bit lines 2.7 are respectively determined to the power supply potential VcC1 and the ground potential Ov, the bit lines 2.7 are connected to the respective data input/output buses I10. It is connected to I10 and data is read out.

[Problems to be Solved by the Invention] The minute potential changes on the primary bit line during data reading will be explained in detail with reference to FIGS. 13 and 14.

FIG. 13 is a diagram showing the movement of charge between the sense amplifier drive signal line and the bit line via the sense amplifier and the potential after the potential change in each signal line.

FIG. 14 is a diagram showing potential changes in each signal line during memory cell data reading. Hereinafter, with reference to FIGS. 13 and 14, minute potential changes on the bit line during memory cell data reading will be described in detail.

Let us now consider the case where data of logic "1°" is read from memory cell 1. In this case, the word line drive signal Rn applied to word line 3 rises, and its potential level becomes VCC/2+
When VT'N exceeds VT'N, the MOS transistor 5 of the memory cell 1 starts to conduct, and the bit line 2 and the node 4 are connected. The potential of increases. This bit line 2
As the potential rises, the MOS transistor 19 begins to conduct, and charges move from the bit line 7 toward the sense amplifier drive signal line 17. As a result, the potential of the sense amplifier drive signal line 17 increases and the potential of the bit line 7 decreases. As the potential of this bit line 7 decreases, M
The OS transistor 15 becomes conductive, charges move from the sense amplifier drive signal line 14 toward the bit line 2, and the potential of the bit line 2 rises. It is thought that if the above-mentioned phenomenon is repeated, the potential of the bit line 2 will gradually increase, but in reality, the capacitance value of the parasitic capacitance 21 of the sense amplifier drive signal line 17 is equal to that of the parasitic capacitance 28 of the bit line 7. Since it is small compared to the capacitance value, the potential of the sense amplifier drive signal line 17 rises faster than the potential drop of the bit line 7, which makes it difficult for the MOS transistor 19 to conduct, and the potential rise of the bit line 2 is relatively small. Stay with the value. In order to further increase the potential rise of the bit line 2, it is conceivable to add a capacitor to the sense amplifier drive signal line 17, but this method increases the time constant of the discharge in the discharge path from the bit line 7. However, there may be cases where the potential drop of the bit line 7 becomes smaller on the contrary.

The phenomenon of potential change in the bit line 2.7 mentioned above is a transient phenomenon, and its details require calculation of the transient phenomenon.
Here, for the purpose of making a rough comparison with the configuration of the present invention described later, the final state where the movement of charges is stopped will be described in the 13th section.
This will be explained using figures.

Now, as shown in FIG. 13, bit line 2 after charge transfer
, 7, the potential changes of the sense amplifier drive signal lines 14 and 17 are assumed to be ΔV+ΔV2, Δ■7, ΔV14, and ΔV17, respectively. Here, ΔV is the amount of potential change caused by reading logic "12 data" from memory cell 1. Also, the capacitance values of parasitic capacitance 20°21.27.28 are C
20, C21, C27, and C28.

First, consider the movement of charges between the bit line 2 and the sense amplifier drive signal line 14. In this case, according to the law of conservation of charge, (VCC/2+ΔV)-C27 + (VCC/2+1VTP l) ・C2O-(V
cc/2+ΔV+ΔV2)-C27+ (Vc c/2
+ l VT P l-ΔV14)・C20°, that is, C27-ΔV2-C20-ΔV14 =・ (1) Similarly, by considering the law of conservation of charge between the bit line 7 and the sense amplifier drive signal line 17, , C28・ΔV7−
C21·ΔV17 (2) is obtained. Also M
Since the OS transistor 19 becomes non-conductive and the movement of charge to the sense amplifier drive signal line 17 is stopped, Vcc/2+ΔV+ΔV2-VT.

=Vcc/2 VTN+ΔV17 That is, ΔV+ΔV2−ΔV17 (3) Similarly, since the MOS transistor 15 becomes non-conductive and the movement of charge to the bit line 2 stops, V cc / 2−ΔV7+IVTP I-Vc
c/2+ l V7 F +-ΔV14, that is, ΔV7-ΔV14...(4)
is obtained. By substituting the above formula (4) into the above formula (2), C28・ΔV14−C21・ΔV17 (5)
is obtained.

On the other hand, from the above formula (1), ΔV14-(C27/C20)-ΔV2-(6) is obtained. Substituting this equation (6) into equation (5), we get (C27-
C28/C20)-ΔV2 -C21・ΔV17 That is, ΔV17− (C27・C28/C20・C21)・Δ
V2...(7) Expression (7) is expressed as (
Substituting into 3) gives ΔV-1(C27・C28/C20・C21)-1)
・ΔV2 That is, ΔV2−ΔV/f (C27・C28/C20・C21)
-11...(8) Similarly, ΔV7 sound ΔV14 Mi ΔV/f (C28/C21) -(C20/C27)l...(9) ΔV17
− (C28/C21) ・ΔV14−ΔV/ (1
-(C20・C21 /C27・C28)l ...(10) Now here,
(C27-C28): (C20-C21):;10
: 1. And if ΔV~200mV, then ΔV2=200/99”=2mV.

AV7-ΔV14-1. IX200 -220mV.

ΔV17-100・200/99=202mV.

The value is obtained. Using the above values, the human potential difference VS applied to the sense amplifier 50 is Vs=V2-V
7...(11)-Vcc/
2+ΔV+Δv2 − (Vcc/2−ΔV7) - ΔV+ΔV2+Δv7 −200+2+220 ■422 mV. This value is a value when the time between time t5 and time t6 is set to infinity, and this value is actually a relatively short finite time (for example, 15 to 25 ns) for high-speed reading of memory cell data. ).

On the other hand, due to voltage noise due to capacitive coupling between adjacent bit lines, and electrical imbalance between bit lines that occurs incidentally during actual memory device manufacturing, the potential between bit lines is 1/3 of the above value. This results in a problem that the operating margin of the sense amplifier circuit is reduced. In other words, in order for the sense amplifier to operate accurately, the larger the potential difference between the human input signals, the better. However, as mentioned above, the potential difference between the human input signals to the sense amplifier becomes smaller, and the operating margin of the sense amplifier circuit decreases, making it difficult to ensure reliable sensing. There was a problem that there were cases where the operation could not be performed.

Therefore, an object of the present invention is to eliminate the drawback that the input potential difference to the sense amplifier in the conventional dynamic random access memory is small as described above, and to increase the potential difference when reading data between bit line pairs. An object of the present invention is to provide a sense amplifier driving device and method that can make the operation of the sense amplifier stable and/or high-speed.

[Means for Solving the Problems] A sense amplifier driving device and method in a random access memory according to the present invention provides a sense amplifier driving signal line that drives a sense amplifier when a sense amplifier drive signal line is generated between a pair of sense amplifier drive signal lines that drive a sense amplifier when reading memory cell data. A transmission means is provided for transmitting a potential change of one drive signal line to the other sense amplifier drive signal line.

This potential change transmission means is deactivated before the sense amplifier is operated. Preferably, the potential change transmission means is constituted by coupling capacitance means.

The sense amplifier driving method according to the first invention capacitively couples a pair of sense amplifier drive signal lines, reads memory cell data, electrically isolates the pair of sense amplifier drive signal lines, and then capacitively couples a pair of sense amplifier drive signal lines. The method includes a step of activating the .

[Operation] According to the sense amplifier driving device and method according to the present invention, a potential change in one bit line that occurs when reading memory cell data is transferred from one sense amplifier drive signal line to the other via the potential change transmission means. The signal is transmitted to the sense amplifier drive signal line of the sense amplifier, and further transmitted to the other bit line via the transistor included in the sense amplifier. As a result, the potential difference between the bit line pair when reading memory cell data can be increased, and the operating margin of the sense amplifier can be expanded.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a diagram showing a sense amplifier driving device which is an embodiment of the present invention, and parts corresponding to those of the conventional sense amplifier system shown in FIG. 11 are given the same reference numerals. .

As is clear from a comparison between the device configuration shown in FIG. 1 and the conventional device configuration shown in FIG.
A potential change transmission circuit 44 is provided between the sense amplifier drive signal line 17 and the second sense amplifier drive signal line 17 for transmitting a potential change occurring in one sense amplifier drive signal line to the other sense amplifier drive signal line.

The potential change transmission circuit 44 is a p-channel MOS transistor whose one conductive terminal is connected to the first sense amplifier drive signal line 14, the other conductive terminal is connected to the node 37, and whose gate is coupled to the clock signal φT. 38, and a capacitor ff1 provided between the node 37 and the node 40.
41, one conductive terminal is connected to the node 40, the other conductive terminal is connected to the second sense amplifier drive signal line 17, and the gate thereof is coupled to the clock signal φd via the signal line 43. Channel MOS transistor 42
It consists of This potential change transmission circuit 44
The potential change occurring in the sense amplifier drive signal line 17 is transmitted onto the first sense amplifier drive signal line 14 by capacitive coupling, and thereby the change in potential that occurs in the sense amplifier drive signal line 17 is transferred from one bit line to the other bit line via the transistor included in the sense amplifier. It has the function of transferring charge to.

FIG. 2 is a waveform diagram showing the operation when using the sense amplifier driving device shown in FIG. 1, and is a diagram showing potential changes of each signal line when reading memory cell data. Note that in the operating waveform diagram of FIG. 2, the sense amplifier drive signal φ1
, φ5, precharge signal φP1 equalize signal φE1
The operation timing of the word line drive signal Rn is the same as in the prior art. In the following explanation, it is assumed that the potential (18) for precharging each bit line is half of the operating power supply potential Vcc, that is, Vcc/2. below,
The operation of a sense amplifier driving device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

As in the conventional case, word line 3 is selected in response to the row address decode signal, word line drive signal Rn is transmitted onto word line 3, and word line drive signal Rn begins to rise. Then, at time tA, the word line drive signal Rn is V
When CC/2+VTN (VTN is the threshold voltage of the transfer gate transistor 5 included in the memory cell 1) is reached, the N-channel MOS transistor 5 of the memory cell 1 starts conducting, and as a result, the logic “
1" data is read out. That is, the charge stored in the capacitor 6 of the memory cell 1 moves to the bit line 2 side via the MOS transistor 5, and the potential of the bit line 2 begins to rise. MoS transistor 19 begins to conduct as the potential of line 2 increases.As a result, bit line 7
The charge stored in the parasitic capacitance 21 of the sense amplifier moves to the second sense amplifier drive signal line 17 through the MOS transistor 19, and acts to increase the potential thereof. On the other hand, at this time, since the clock signals φT and φD are at the 0 and Vcc levels, respectively, the MoS transistors 38 and 42 of the potential change transmission circuit 44 are both sufficiently conductive. As a result, the potential change occurring in the second sense amplifier drive signal line 17 is transmitted as is to the first sense amplifier drive signal line 14 via the coupling capacitor 41. At this time, M
The potential of the OS transistor 15 decreases due to discharge via the MOS transistor 19 of the bit line 7, and the OS transistor 15 becomes conductive. Therefore, the first sense amplifier drive signal line 1
The amount of potential change transmitted to bit line 4 is transmitted to bit line 2 via MOS transistor 15, thereby further increasing the potential of bit line 2. Hereinafter, as the potential of the bit line 2 rises, the MOS transistor 19 is turned on, and as the potential of the bit line 7 falls, the N-channel MOS transistor 15 remains on. 2 sense amplifier drive signal line 17→
MOS transistor 42 → capacitor j141 → MOS transistor 38 → first sense amplifier drive signal line 14-MOS
This means that the signal is transmitted to the bit line 2 through the transistor 15. As a result, the potential of the bit line 2 changes to be higher than the potential read from the memory cell 1, while the potential of the bit line 7 also gradually decreases. At this time, since the sense amplifier drive signal lines 14 and 17 simply function as the above-mentioned charge transfer medium, the potentials φ, φB do not change, and each V
CC/2+1VTF l, Vcc/2VTN.

Next, at time tB, the clock signals 7 and φT are raised and lowered, respectively, so that the MOS transistors 38.
42 are both turned off, and the sense amplifier drive signal lines 14 and 17 are electrically isolated.

Next, at time tc, the sense amplifier drive signal φ rises, and a sensing operation of memory cell data is performed. At this time, in this embodiment, since potential changes have already occurred in opposite directions on each of the bit lines 2 and 7, a potential difference approximately twice as large as that in the conventional case has occurred, and the sense amplifier 50 It is possible to increase the read margin for the data, and to stabilize the operation.

Furthermore, when operating the sense amplifier 50 at the same potential difference between the bit line pairs as in a conventional memory device, the time required to reach that potential difference is much shorter than in the past, so it is faster than in the conventional device. Sense amp 50 at the moment
can be operated, and high-speed data reading is possible.

Furthermore, the operation of the sense amplifier 50 increases the sense amplifier drive signal φ at time tc, turns on the MOS transistor 27, and changes the potential of the first sense amplifier drive signal line 17 from Vcc/2-VTN to ground. This is done by lowering the potential to Ov, and this potential change is applied to the second sense amplifier drive signal line 1 via the capacitor 41.
At time t6 immediately before time tc, both MOS transistors 38 and 42 are rendered non-conductive to electrically isolate the first and second sense amplifier drive signal lines.

In addition, in the above embodiment, a state in which the memory cell 1 stores "1" was also explained, but the same argument holds true even in a state in which it stores "0°".

At this time, the potential of the bit line 2 drops, but charges move along the path of the bit line 2 -> MOS transistor 18 -> capacitor 41 - MOS transistor 16 -> bit line 7.

FIG. 3 is a diagram schematically showing a circuit configuration for generating a clock signal for controlling the operation of the potential change transmission circuit 44. The configuration shown in FIG. 3 includes a delay circuit 200 that delays the word line drive signal Rn by a predetermined time and outputs it, and a clock signal φ that responds to the signal from the delay circuit 200.
A clock signal generation circuit 201 that generates clock signals φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8, φ8. and a sense amplifier drive signal generation circuit 203 that generates φ, respectively. In this configuration, the clock signal generation circuit 201 generates the clock signal φT after a predetermined time has elapsed after the word line drive signal Rn rises.

77 to lower and raise respectively. Sense amplifier drive signal φ5. φ and φ rise and fall respectively after a predetermined time has elapsed after the clock signal φd falls.

Although the rising and falling points of each of the clock signals φd and φd are not clearly shown, the sense amplifier drive signal φ rises and the potential difference between the bit line pair increases at this starting point. It may be at any point after being enlarged.

In other words, the potential change transmitting means 44 amplifies the potential difference between the bit line pair when memory cell data is successively transmitted to increase the manual potential difference of the sense amplifier. The amplifier drive signal line 17 is electrically separated from the amplifier drive signal line 17 at a timing that prevents a drop in the potential of the second drive signal line from being transmitted to the first drive signal line when sensing the potential difference between the bit line pair. Any point in time is fine. Note that in the configuration of FIG. 3, the delay time of the delay circuits 200 and 202 is set to an appropriate value in the design of each memory device.

Note that in the above embodiment, the sense amplifier drive signal line 1
4.17, the configuration uses one p-channel MOS transistor and one n-channel MOS transistor, but instead of this configuration, transistors of the same conductivity type are used as shown in FIGS. 4 and 5, respectively. Even if a MOS transistor having a channel of 1 is used, the same effect as in the above embodiment can be obtained. Here, FIG. 4 shows two n-channel MOS
FIG. 5 shows a circuit configuration when transistors 42, 42' are used, and FIG. 5 shows p-channel MOS transistors 38, 42'.
38' is used. However, in this configuration, the polarities of the clock signals must be reversed.

Furthermore, in the configurations shown in FIGS. 4 and 5, the MO
Although a configuration using two S transistors is shown, instead of this, one MOS transistor is used as shown in FIGS. 6 and 7.
Even if the transmission circuit 44 is configured using transistors, the same effects as in the above embodiment can be obtained. That is, in the configuration of FIG. 6, the n-channel MOS transistor 42 is provided between the capacitor f141 and the second sense amplifier drive signal vA17. A tarlock signal φd is applied to the gate of this n-channel MOS transistor 42 via a signal line 43. In the configuration shown in FIG. 7, an n-channel MOS transistor 42' is provided between the first sense amplifier drive signal line 14 and the capacitor 41. Furthermore, in the configurations shown in FIGS. 6 and 7, n-channel MOS transistors 42, 42
A similar effect can be obtained by using n-channel MOS transistors instead of . However, in this case, unnecessary current may flow through the capacitor 41 during the sensing operation, resulting in a slight increase in power consumption, but there is no problem in practical use, and the same effects as in the above embodiment can be obtained. here,
When an n-channel MOS transistor is used instead of the n-channel MOS transistor shown in FIGS. 6 and 7, the polarity of the clock signal φT must be reversed.

Furthermore, although so-called dummy cells are omitted in the embodiment shown in FIG. 1, the effects of the present invention can be further improved by connecting dummy cells to the bit lines.

In this dummy cell system, dummy word lines 62 and 65 are provided as shown in FIG.
A MOS transistor 64 having the same shape as the transistor 5 is connected, and a MOS transistor 61 having the same shape as the MOS transistor 5 is also provided at the intersection of the dummy word line 62 and the bit line 7. When the word line 3 is selected, the word line drive signal Rn is transmitted to the word line 3, and the potential of the word line 3 rises from OV to Vcc, the parasitic window ff160 between the word line 3 and the bit line 2
It is conceivable that the word line and bit line are coupled together, and the potential of the bit line 2 is slightly raised. In order to avoid this, an MOS transistor of the same shape as the MOS transistor 5 is provided on the bit line 7 side at the intersection with the dummy word line 62.
S) A similar parasitic capacitance 63 is formed between the dummy word line 62 and the bit line 7 by the transistor 1, and the same coupling voltage as that on the lipit line 2 side is applied to the bit line 7, thereby reducing voltage noise due to capacitive coupling. canceled out.

That is, when the word line 3 is selected, the dummy word line 62 is selected, and the dummy word line drive signal DRn is transmitted onto the dummy word line 62.

On the other hand, when bit line 7 is selected, dummy word line 65 is selected, and dummy word line drive signal DRn is transmitted onto dummy word line 65. These dummy word line drive signals DRn and DRn are both generated at the same timing as the word line drive signal Rn and have the same waveform. In addition, these dummy word line drive signals DRn, DR
n can be easily generated based on the row address decode signal. As described above, if the dummy cell method shown in FIG. 8 is applied to the configuration shown in FIG. 1, it becomes possible to further stabilize the operation of the sense amplifier.

Further, in the above embodiment, the sense amplifier 50 is driven by first performing a discharging operation using the sense amplifier drive signal line 17, but this is different from performing a charging operation using the sense amplifier drive signal line 14 first. In this case, the same effects as in the above embodiment can be obtained. That is, either sense amplifier drive signal φS or φ may be activated first.

Furthermore, in the above embodiment, 1/2 Vcc
Although a precharge type memory device has been described, the present invention is also applicable to a Vcc precharge type memory device. However, at this time, since it is necessary to hold the first drive signal line 14 at a potential higher than the precharge potential, the power supply potential Vcc applied to the signal line 28 in FIG. It is necessary to set it to a high potential VcC'.

[Effects of the Invention] As described above, according to the present invention, the second sense amplifier drive signal is connected between the first sense amplifier drive signal line and the second sense amplifier drive signal line when reading memory cell data. Since a potential change transmission circuit is provided to transmit the potential change occurring in the line to the first sense amplifier drive signal line, this transmitted charge (i.e. potential change) is transmitted between the bit line pair via the sense amplifier. Therefore, it is possible to increase the potential difference between the bit line pair when reading memory cell data, thereby increasing the input potential difference when operating the sense amplifier, and increasing the operating margin of the sense amplifier. At the same time, if the sense amplifier is driven at the same potential difference between the bit line pairs as in the prior art, it becomes possible to activate the sense amplifier at an earlier point in time than in the prior art, making it possible to read data at high speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a sense amplifier driving device in a dynamic random access memory which is an embodiment of the present invention. FIG. 2 is a waveform diagram showing potential changes due to each signal line when a sense amplifier driving device according to an embodiment of the present invention is operated. FIG. 3 is a diagram showing an example of a circuit configuration for generating a clock signal for controlling the operation of a potential change transmission circuit according to an embodiment of the present invention. FIG. 4 is a diagram showing a first modification of the potential change transmission circuit shown in FIG. 1. FIG. 5 is a diagram showing a second modification of the potential change transmission circuit shown in FIG. 1. 6th
This figure shows a third modification of the potential change transmission circuit shown in FIG. 1. FIG. 7 is a diagram showing a fourth modification of the potential change transmission circuit shown in FIG. 1. FIG. 8 is a diagram showing an example of a configuration when a dummy cell system is applied to the bit line configuration in another embodiment of the present invention. FIG. 9 is a diagram showing a schematic configuration of a reading section of a conventional dynamic random access memory to which the present invention is applied. FIG. 10 is a block diagram showing the detailed configuration of the memory cell array section shown in FIG. 9. FIG. 11 is a diagram showing a conventional configuration of a pair of bit lines, a sense amplifier, and a sense amplifier drive system. FIG. 12 is a diagram showing potential changes on each signal line in the conventional sense amplifier driving method. FIG. 13 is a diagram showing potential changes and charge flows on the bit line and sense amplifier drive signal line during memory cell data reading. FIG. 14 is a diagram showing potential changes on each signal line when reading memory cell data in a conventional sense amplifier. In the figure, 1 is a memory cell, 2.7 is a bit line, 3 is a word line, 14 is a first sense amplifier drive signal line, 17
1 is a second sense amplifier drive signal line, 44 is a potential change transmission circuit, 50 is a sense amplifier, 100 is a constant voltage generation circuit,
150 is a bit line pair precharge/equalize circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (11)

[Claims] (1) A plurality of bit line pairs configured by repeatedly arranging first and second bit lines to form a pair, each of which is connected to a plurality of memory cells, and each of the plurality of bit line pairs. and a plurality of sense amplifiers that are provided and activated in response to signals transmitted via the first and second signal lines to differentially amplify signals on corresponding bit line pairs. A sense amplifier driving device in a memory, comprising: potential change transmitting means provided between the first and second signal lines and transmitting a potential change of the second signal line to the first signal line; A sense amplifier driving device in a dynamic random access memory, comprising control signal generating means for generating a signal for controlling the operation of the potential change transmitting means in response to a control signal that defines information read timing of the memory cell. (2) The potential change transmitting means is inactivated before activation of the sense amplifier in response to the output of the control signal generating means, and electrically connects the first signal line and the second signal line. A sense amplifier driving device in a dynamic random access memory according to claim 1, comprising means for isolating. (3) The electrical isolation means is activated before the information of the selected memory cell is transmitted onto the corresponding bit line in response to a control signal that defines information read timing of the memory cell. , A sense amplifier driving device in a dynamic random access memory according to claim 2. (4) In the dynamic random access memory according to claim 1, wherein the potential change transmission means includes capacitive coupling means for capacitively coupling the first signal line and the second signal line. Sense amplifier drive device. (5) The potential change transmission means includes a switching means that turns off in response to the output of the control signal generation means, and a capacitance means connected in series with the switching means. A sense amplifier driving device in the dynamic random access memory described above. (6) The potential change transmission means is provided with a capacitor and a first insulated gate field effect that is provided between the capacitor and the first signal line and turns off in response to the output of the control signal generating means. and a second insulated gate field effect transistor provided between the capacitor and the second signal line and turned off in response to the output of the control signal generating means. A sense amplifier driving device in the dynamic random access memory according to item 1. (7) The potential change transmission means is provided between a capacitor having one electrode and the other electrode coupled to the first signal line, and the other electrode of the capacitor and the second signal line. a third insulated gate field effect transistor which is turned off in response to the output of the control signal generating means;
A sense amplifier driving device in a dynamic random access memory according to claim 1. (8) The potential change transmission means is provided between a capacitor having one electrode and the other electrode coupled to the second signal line, and the other electrode of the capacitor and the first signal line. a fourth insulated gate field effect transistor which is turned off in response to the output of the control signal generating means;
A sense amplifier driving device in a dynamic random access memory according to claim 1. (9) The sense amplifier is provided between the first bit line and the second bit line, one electrode and the gate electrode are provided in a cross-connected manner, and the other electrode is connected to the sense amplifier. A connection provided between a pair of n-channel insulated gate field effect transistors to which two signal lines are coupled, and the first bit line and the second bit line, and one electrode and the gate electrode are cross-connected. a pair of p-channel insulated gate field effect transistors, the other electrode of which is coupled to the first signal line; 2. The device according to claim 1, further comprising means for maintaining the first signal line potential at a value higher than the precharge potential than the absolute value of the threshold voltage of the p-channel insulated gate field effect transistor. Sense amplifier driver in dynamic random access memory. (10) Claim 1 further comprising a dummy cell connected to each of the first bit line and the second bit line and having a capacitance value equal to the capacitance of each of the plurality of memory cells. A sense amplifier driving device in the dynamic random access memory described in 2. (11) A plurality of bit line pairs configured by arranging first and second bit lines to form a pair, each of which is connected to a plurality of memories; and a plurality of bit line pairs provided in each of the plurality of bit line pairs. , a plurality of sense amplifiers that are activated in response to signals transmitted via first and second signal lines and differentially amplify signals on corresponding bit line pairs. A sense amplifier driving method, comprising: capacitively coupling the first signal line and the second signal line; accessing the plurality of memory cells;
a step of transmitting information possessed by a selected memory cell onto a corresponding bit line; and a step of electrically separating the first signal line and the second signal line and activating the sense amplifier. A sense amplifier driving method in a dynamic random access memory.