JP2995219B2 - Dynamic constant speed call storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a constant-speed call storage device using dynamic storage cells. (Prior Art and its Problems) The operation of a conventional dynamic constant-speed call storage circuit is described in U.S. Pat.
8,844 and 3,514,765 and Walstrom (Wahl
No. 3,699,537 to the inventors of the present invention and U.S. Pat. Nos. 3,902,082 and 3,969,706 to the inventors of Proebsting et al. It is common to use a sense amplifier to sense the differential voltage on each bit line connected to each storage cell, as shown in the Wallstrom and Pavesting patents. The connection of the storage cell to the bit line changes the previously generated voltage on this bit line to produce the desired data state as a differential voltage on each bit line. However, the change in the voltage of this bit line caused by the connection of the storage cell to the bit line is very small, and the detection of such a small voltage change causes a serious problem in the structure of the dynamic constant-speed memory. Another problem is that electrical noise is transmitted and received by the bit lines, and this electrical noise can disrupt the desired voltage offset created by the storage cells. In addition, manufacturing tolerances of the integrated circuit may cause unbalanced bit lines, which will prevent reading of the storage cells. In response to these problems, it has conventionally been practiced to make a dummy cell cooperate with each bit line of a storage device. The dummy cell is precharged (precha) to a given voltage state.
rge) and connected to the unselected bit line in each pair of bit lines during each storage cycle. However, the provision of cooperating circuits with multiple dummy cells increases the size of the integrated circuit and further complicates the circuit. Due to the above-mentioned problem, it is operated such that a dummy cell for each bit line is not required in such dimensions, and at the same time, a reliable and identifiable dynamic constant velocity of the voltage state stored in each storage cell. Call storage is needed. (Solution of Problem by the Present Invention) The present invention provides a method for operating a dynamic constant-speed call storage device in the following steps. A high voltage state corresponding to the first data state or a low voltage state corresponding to the second data state is stored in the dynamic storage cell. The storage cell is then connected to one of the bit lines after setting the pair of bit lines to an intermediate voltage state. When a memory cell that stores a low voltage is connected to a bit line, the voltage of the bit line decreases. When a memory cell storing a high voltage is connected to a bit line, the voltage of this bit line rises. When the voltage state of one bit line is being changed by the connection of a storage cell to this bit line, the other bit line of the pair is substantially maintained at the set intermediate voltage state. Dripping. After connecting the storage cell to one of the bit lines, the bit line with the lowest voltage is driven to a lower voltage state and the other bit line is driven to a higher voltage state. The storage cell is disconnected from the corresponding bit line after driving the corresponding bit line to a low or high voltage state. After disconnecting the memory cell from the corresponding bit line, the bit lines are interconnected and brought to an intermediate voltage state in preparation for a new cycle. (Embodiment) FIG. 1 illustrates a dynamic constant-speed call storage device according to the present invention. A storage address is sent to the storage device 10 via a group of address lines 12. The address line 12 is provided in each of a plurality of row decoders such as the row decoder 14. Each address line 12
Are connected to a plurality of respective column decoders such as the decoders 16 and 17. The address bits for the selected row line are provided in parallel at a time over each line 12 during a storage cycle. Also, the address bits for the selected column are provided delayed via each line 12 during the storage cycle. This is is illustrated by the address waveform A ₀ to A _n shown in Figure 2. The row address bits select a row decoder, such as decoder 14, and activate row line 18. Line 18 is the access
It is connected to a dynamic storage cell 22 comprising a transistor 24 and a storage capacitor 26. The gate terminal of access transistor 24 is connected to row line 18 and the access transistor
The source terminal of 24 is connected to the first terminal of the storage capacitor 26. The remaining terminals of the storage capacitor 26 are connected to a ground connection (node) 28. The drain terminal of the access transistor 24 is connected to the bit line 30. The row line 20 is charged by the row decoder 21 and connected to the dynamic storage cell 32. Dynamic storage cell 32
Includes an access transistor 34 and a storage capacitor 36. The gate terminal of access transistor 34 is connected to line 20 and its source terminal is connected to the first terminal of storage capacitor 36. The remaining terminals of the storage capacitor 36 are connected to the ground connection 28. access·
The drain terminal of the transistor 34 is connected to the bit line 38. When driving a row line 18 to a high voltage state, the corresponding access transistor 24 is activated, forming a conductive path between the bit line 30 and the storage capacitor 26. The row line voltage selected by the row decoder is illustrated by the timing signal 40 shown in FIG. Sense amplifier 44
Is activated in response to a latch signal transmitted via the latch connection 46. The latch signal L has a waveform 48 shown in FIG.
As an example. The storage device 10 includes a balance circuit having transistors 50 and 52. The source and drain terminals of transistor 50 are connected between bit line 30 and latch connection 46, and the source and drain terminals of transistor 52 are connected between bit line 38 and latch connection 46. The gate terminals of the transistors 50 and 52 are connected to the balanced signal E
Connected to the connection section 54 for receiving the signal. The balanced signal E is illustrated as a waveform 56 in FIG. When the balanced signal E is set to a high voltage state, each transistor 50, 52 is turned on, connecting each bit line 30, 38 to the connection 46. The pull-up circuit 60 is connected to the bit line 30 via a line 62. The pull-up circuits 60 are shown in FIG.
The precharge signals exemplified as 63, 64, and 66 operate in response to P ₀ and P ₁ . A similar pull-up circuit 68 is connected to bit line 38 via line 70. Each pull-up circuit 6
0,68 detect when the voltage on the corresponding bit line is higher than the previously set voltage level, and when receiving a precharge signal, raise the bit line to the supply voltage as described below. Each bit line is provided with a column transistor that transmits the data state within and from each of the storage cells. The source terminal and the drain terminal of the column transistor 74 are connected between the bit line 30 and the input / output line 76. The gate terminal of the column transistor 74 is connected to the column decoder 16. Similarly, the drain terminal and the source terminal of the column transistor 80 are connected between the bit line 38 and the input / output line 82. The gate terminal of the column transistor 80 is connected to the column decoder 17 which responds to the same column address signal as the column decoder 16. Each column decoder 16, 17 activates a selected column transistor in response to a column address bit received over address line 12 to transmit a data state to and from the addressed storage cell. Input / output lines 76, 82 are connected to an input / output circuit 84 which serves to transmit the data states written into and read from each storage cell. The data action is received from an external circuit via a data input terminal 86 and transmitted to an external circuit via a data output terminal 87. Next, the operation of the dynamic constant speed call storage device 10 according to the present invention will be described with reference to FIGS. 1, 2, 3, and 4. FIG. This circuit operates from a 5.0V power supply. The storage cycle is started by a row address strobe (RAS) signal 90. The RAS signal 90 is activated when transitioning from a high level to a low level. The row address bits are provided in row body 14, as shown by waveform 92a. The row address bits are received immediately after the RAS signal goes active. Row decoder 14 sends a row enable signal 40 to the selected row line. When row enable signal 40 is at a level of 5V, access transistor 24 in storage cell 22 is conductive and
The storage capacitor 26 is connected to the bit line 30. Bit line 3
0,38 were previously equilibrated to a voltage level of about 2.0V, as shown by waveform 96. If the storage capacitor 26 had previously been charged to the stored level of 5.0 V, the bit line 30 would be driven by the waveform 96a of FIG. 2 for charge sharing between the storage capacitor 26 and the bit line 30. Driven to about 2.3V as shown. However, if storage capacitor 26 had previously been discharged to ground potential, bit line 30 would be at about 1.8V, as shown by waveform 96b. After the storage cell 22 is connected to the bit line 30, the latch signal L shown as waveform 48 goes to ground potential. Sense amplifier 44
Responds to a latch signal by bringing one of the bit lines connected to it and at the lower voltage to ground potential. If the capacitor 26 had previously been discharged, the voltage on the bit line 30 would be as shown by waveform 96b when this voltage was brought to ground potential. However, if storage capacitor 26 is charged to the stored high voltage level as shown by waveform 96a, bit line 30 will not be affected by the operation of sense amplifier 44. However, if bit line 30 is rising to the voltage shown by waveform 96a, bit line 30 will exceed the voltage on bit line 38 shown as waveform 98, and bit line 38 will be at ground potential as shown by waveform 98a. However, if the voltage on bit line 30 is pulled down by storage capacitor 26, the balanced voltage on bit line 38 is not affected by sense amplifier 44. This condition is shown by waveform 98b. After the sense amplifier 44 lowers one of the bit lines to the ground potential, the pull-up circuits 60, 6
After precharging 8, precharge signals P ₀ and P ₁ are received, and pull-up circuits 60 and 68 are activated. Each of the pull-up circuits 60, 68 detects which one of the bit lines has a higher voltage than the previously set voltage. One of the bit lines will be at ground potential and the other bit line will be at a balanced voltage or a rising voltage caused by connecting to a storage capacitor storing a high voltage.
Bit lines with high voltages are pulled up to the supply voltage. For a bit line that has received a high charge from a storage cell, this condition is illustrated by waveform 96a. The waveform 98b is shown for the bit line at the balanced voltage.
At this time, the storage capacitor connected to the bit line has returned to its original voltage. When one of the bit lines is driven to a supply voltage and the other bit line is at ground potential, the column transistors 74, 80 are turned on, connecting each bit line 30, 38 to the input / output lines 76, 82, respectively. The voltage state of each bit line is transmitted to the input / output circuit 84 via each input / output line. The input / output circuit 84 is connected to the input / output line 7
A sense amplifier is provided to detect a differential voltage between 6,82. The sense amplifier in the input / output circuit measures the voltage state stored in the storage cell and transmits this voltage state via data output line 87. After one of the bit lines is at ground potential and the other bit line is at supply voltage, the data state in the storage cell is stored again. The row line 18 then returns to ground potential and separates the charge on the storage capacitor. These bit lines are then left floating. The balanced signal 56 is then applied to each transistor
In addition to the gate terminals of 50 and 52, the transistors 50 and 52 are turned on, and the bit line 30 is connected to the bit line 38 via the latch connection 46. This connection allows the charge to be shared by each bit line,
These bit lines are balanced to a voltage approximately midway between the supply voltage and ground potential. This is shown in both waveforms 96 and 98. In this case, each of the waveforms 96 and 98 returns to the balanced voltage of 2V. A representative circuit for the sense amplifier 44 shown in FIG. 1 is illustrated in FIG. The source and drain terminals of the pass transistor 104 are connected to the bit line 30 and the connection 106
Connected between Second pass transistor 108
The source terminal and the drain terminal are connected between the bit line 38 and the connection part 110. The gate terminals of both transistors 104, 108 are connected to a high voltage source such as the supply voltage V _CC . Each transistor 104, 108 is always conductive and acts as a resistor. The drain terminal of the transistor 112 is connected to the connection 106, and the source terminal is connected to the connection 46.
, And the gate terminal is connected to the connection unit 106. The operation of the sense amplifier is as follows.
That is, it occurs after connection to line 30 or line 38. One of the bit lines is now at a higher voltage than the other bit line. For example, it is assumed that the bit line 30 has a higher voltage. When the connection portion 46 is gradually set to the ground potential by the latch signal, the bias from the gate to the source of the transistor 114 is larger than the bias from the gate to the source of the transistor 112. Turned on. Transistor 114
When is conducting, connection 110 is discharged to latch connection 46 via transistor 114. When the connection portion 110 is discharged, the gate bias of the transistor 112 decreases and the transistor 1
12 is prevented from becoming conductive. When the latch signal is pulled down to ground potential, transistor 114
Continue conduction. This is because the bit line 30 and the connection unit 106 remain in the previous high charge state. When the connection portion 110 is discharged, the bit line 38 is discharged by the conduction of the transistor 108.
That is, after the latch signal has completely reached the ground potential, the bit line 38
Again at ground potential. If the line 38 goes to the higher voltage after connecting the storage cell to one of the bit lines, the transistor 112 will be conductive and
The connection 106 is discharged to set the bit line to the ground potential. A circuit diagram of the pull-up circuits 60 and 68 is illustrated in FIG. The drain terminal of the transistor 120 is connected to the _VCC power supply, the source terminal is connected to the connection unit 122, and the gate terminal is connected to receive the precharge signal P.
The drain terminal of the transistor 124 is connected to the connection portion 122, the source terminal is connected to the bit line 30, a gate terminal connected to receive a precharge signal P _0. The drain terminal of the transistor 126 is connected to the precharge signal P
₁ , the gate terminal is connected to the connection 122, and the source terminal is connected to the gate terminal of the transistor 128. The drain terminal of transistor 128 is V
_It is connected to a _CC power supply, and its source terminal is connected to the bit line 30. When receiving the precharge signal P, a transistor
120 becomes conductive and pre-charges connection 122 to a high voltage state. When the precharge signal returns to a lower voltage level, connection 122 remains floating at the higher voltage state. When the precharge signal P ₀ is approximately 2V, the transistor 124 is rendered conductive if the bit line 30 is at a sufficiently low voltage state, at least one transistor threshold between the gate and source terminals of the transistor 124 Voltage is present. When the transistor 124 is turned on, the connection section 122 is discharged to the bit line 30. However, the charge on the bit line 30 is sufficiently high that the transistor 12
If there is less than one transistor threshold voltage between the fourth gate and source terminals, the connection portions 12 in the transistor 124 does not become in a conductive state by the precharge signal P ₀
Leave 2 floating at the higher voltage level. Then P
The signal is applied to the drain terminal of transistor 126. When the connection portion 122 is at a high voltage, transistor 126 is conductive, the source of the transistor 126 follows the signal P ₁ above V _CC. This bootstraps connection 122 to a high voltage level due to the channel capacitance of transistor 126. Yotsute full voltage level of the precharge signal P ₁ which is bootstrapped applied to the gate terminal of the transistor 128, the total supply voltage V _CC is by applied to the bit line 30, the bit line voltage state of V _CC . That is, when the voltage of the bit line 30 is higher than the previously set level, the bit line is connected to the precharge circuit.
The operation of 60 raises the supply voltage, but if the voltage on bit line 30 is lower than the previously set level, precharge circuit 60 does not affect bit line 30. (Effect of the Present Invention) In short, the present invention resides in a dynamic constant-speed call storage device in which each bit line is equilibrated to about half of the supply voltage before connecting a storage cell to each bit line. The sense amplifier detects a voltage difference between the bit lines caused by connecting the storage capacitor to one of the bit lines, and sets the bit line having the lower voltage to the ground potential. The pull-up circuit sets the bit line having the higher voltage to a high voltage. After the voltage state has been transferred via the input / output lines and after the storage cells have been separated, each bit line is floated and connected to each other via a latch connection, and these bit lines are connected between these bit lines. The voltage is returned to the equilibrium voltage by charge transfer. One embodiment of the present invention is illustrated and described in detail in the accompanying drawings. However, the present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the scope of the present invention. Of course.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of one embodiment of a dynamic constant-speed call storage device according to the present invention, and FIG. 2 is generated in the dynamic constant-speed call storage device illustrated in FIG. 3 is a timing diagram of various signals, FIG. 3 is a circuit diagram of the sense amplifier shown in FIG. 1, and FIG. 4 is a circuit diagram of a pull-up circuit shown in FIG. is there.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Prevstaying, Rabat, Jei               Dara, 75248, Texas, United States               Su, Harvest Glen 6623                (56) References JP-A-54-101228 (JP, A)                 JP-A-54-101229 (JP, A)                 JP-A-55-70990 (JP, A)

Claims (1)

(57) [Claims] (A) storing a first voltage state corresponding to the first data state and a second voltage state corresponding to the second data state in the dynamic storage cell; and (b) a pair of bit lines. Is set to a third voltage state, the dynamic memory cell is connected to one of the bit lines, and when the first voltage state is stored in the memory cell, Connect the connected bit line to the fourth
Or when the second voltage state is stored in the storage cell, the bit line connected to the storage cell is driven to a fifth voltage state. Substantially maintaining the other one of the bit lines at the third voltage state; and (c) driving the bit line having the lower voltage of the two bit lines to a lower voltage state. (D) driving the other one of the bit lines having a higher voltage to a higher voltage state; (e) disconnecting the storage cell from the corresponding bit line; F) floating each bit line; and (g) driving one bit line of the pair of bit lines to the low voltage state and driving the other bit line to the high voltage state. After that, the bit lines are connected to a common connection. And the third voltage state is between the first voltage state and the second voltage state due to charge transfer between the two bit lines. The third
Is between the fourth voltage state and the fifth voltage state, the voltage of both bit lines is changed to the third voltage state.
Balancing the dynamic state of the dynamic constant speed call storage device. 2. In connecting the two bit lines to each other, a charge is shared between the bit lines so that the bit lines are balanced to a third voltage state, and the third voltage state is changed to a high voltage state and a low voltage state. 2. The method of claim 1 wherein the state is approximately intermediate between the states. 3. The step of driving one bit line having the lowest voltage of the two bit lines to a low voltage state is performed before the step of driving the other bit line to a high voltage state. The operation method according to claim 1. 4. (A) at least one pair of bit lines; and (b) each of the bit lines for storing a first voltage state corresponding to a first data state or a second voltage state corresponding to a second data state. (C) connecting one of these storage cells to a corresponding bit line in response to a supplied storage address, but connecting both bit lines to a third one; And the bit line connected to the storage cell is set to the fourth voltage state if the first voltage state is stored in the storage cell connected to the bit line. A connection means for driving the memory cell connected to the bit line to the fifth voltage state if the second voltage state is stored in the memory cell connected to the bit line; Low connected to each bit line and thus connected A sense amplifier that drives a bit line having one of the charges to a low voltage state when receiving a latch signal; and (e) sets a connected bit line of the pair of bit lines to a low bit state, After being driven to the voltage state,
(F) pulling up the bit line previously connected to the storage cell to the low voltage state or the high voltage state, and then driving the storage cell to the high voltage state. (G) driving one of the pair of bit lines to the low voltage state and driving the other bit line to the high voltage state, and then connecting the pair of bit lines to a common bit line. A charge is connected between the bit lines of the pair and the bit lines of the plurality of other dynamic memory cells by connecting to a connection portion also connected to the bit lines of the plurality of other dynamic memory cells. The third voltage state is between the first voltage state and the second voltage state, and the third voltage state is the fourth voltage state and the fourth voltage state, mainly due to causing the transfer. In a fifth voltage state, both bits Including a connection means for the voltage to be equilibrated by the third voltage state, the dynamic constant velocity call storage device. 5. 5. The semiconductor device according to claim 4, further comprising: separating means for separating each bit line from each other after driving one of the bit lines to a low voltage state and driving the other bit line to a high voltage state. A dynamic constant velocity call storage device as described. 6. Connecting means for connecting the two bit lines to each other, a first transistor having a drain terminal and a source terminal connected between one of the pair of bit lines and a latch connection of the sense amplifier; A second transistor having a drain terminal and a source terminal connected between the other of the number of bits of the pair and the latch connection portion, and turning on each of the transistors to set a voltage of both bit lines. 5. The device according to claim 4, wherein the gate terminal of each of said transistors is connected so as to receive a balanced signal for balancing said third voltage by charge transfer of said bit lines. . 7. A first terminal of a storage capacitor having a drain terminal connected to one of the bit lines and a gate terminal connected to a row line, and a second terminal connected to a common connection; 5. A dynamic constant-speed call storage device according to claim 4, wherein said access transistor has a source terminal connected to said access transistor.