JP2985031B2 - Operating method of dynamic constant speed call storage device. - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a constant speed call storage device using dynamic storage cells. 2. Description of the Related Art The operation of a conventional dynamic constant-speed call storage circuit is based on Christeneo.
n), U.S. Pat. Nos. 3,588,844 and 3,514,765, and Walstrom (Wa).
hlstrom) in US Patent 3,69.
No. 9,537 and Proebsti
ng) et al., US Pat. No. 3,902,082.
And No. 3,969,706. It is common to use a sense amplifier to sense the differential voltage on each bit line connected to each storage cell, as shown in the Wallstrom and Pavesting patents. The connection of the storage cell to the bit line changes the previously generated voltage on this bit line to produce the desired data state as a differential voltage on each bit line. However, the change in the voltage of this bit line caused by the connection of the storage cell to the bit line is very small, and the detection of such a small voltage change causes a serious problem in the structure of the dynamic constant-speed memory. Another problem is that electrical noise is transmitted and received by the bit lines, and this electrical noise can disrupt the desired voltage offset created by the storage cells. In addition, manufacturing tolerances of the integrated circuit may cause unbalanced bit lines, which will prevent reading of the storage cells. In response to these problems, it has conventionally been practiced to make dummy cells cooperate with each bit line of a memory device. Dummy cells are precharged to a given voltage state and connected to unselected bit lines in each pair of bit lines during each storage cycle. However, the provision of cooperating circuits with multiple dummy cells increases the size of the integrated circuit and further complicates the circuit. Due to the above-mentioned problems, operation is performed such that a dummy cell for each bit line is not required in such a size, and at the same time, a reliable and identifiable operation of a voltage state stored in each storage cell is performed. There is a need for a constant speed call storage device. SUMMARY OF THE INVENTION The present invention provides a method for operating a dynamic constant speed call storage device in the following steps. A high voltage state corresponding to the first data state or a low voltage state corresponding to the second data state is stored in the dynamic storage cell. The storage is then connected to one of the bit lines after setting the pair of bit lines to an intermediate voltage state. When a memory cell that stores a low voltage is connected to a bit line, the voltage of the bit line decreases.
When a memory cell storing a high voltage is connected to a bit line, the voltage of this bit line rises. When the voltage state of one bit line is being changed by the connection of the storage cell to this bit line, the other bit line of the pair is substantially maintained at the set intermediate voltage state. Dripping. After connecting the storage cell to one of the bit lines, the bit line with the lowest voltage is driven to a lower voltage state and the other bit line is driven to a higher voltage state. The storage cell is disconnected from the corresponding bit line after driving the corresponding bit line to a low or high voltage state. After disconnecting the storage cell from the corresponding bit line, the bit lines are interconnected and brought to an intermediate voltage state in preparation for a new cycle. FIG. 1 illustrates a dynamic constant speed call storage device according to the present invention. A storage address is sent to the storage device 10 via a group of address lines 12. The address line 12 is provided in each of a plurality of row decoders such as the row decoder 14.
Each address line 12 is connected to a plurality of respective column decoders such as decoders 16 and 17. Address bits for the selected row line are provided in parallel at a time over each line 12 during a storage cycle. Also, the address bits for the selected column are delayed through each line during the storage cycle. This means that the address waveform _Ao shown in FIG.
It is illustrated by to A _n. The row address bits select a row decoder, such as decoder 14, and activate row line 18. Line 1
8 is connected to a dynamic storage cell 22 having an access transistor 24 and a storage capacitor 26. The gate terminal of access transistor 24 is connected to row line 18, and the source terminal of access transistor 24 is connected to a first terminal of storage capacitor 26. The remaining terminal of the storage capacitor 26 is connected to a ground connection (node) 2.
8 is connected. The drain terminal of the access transistor 24 is connected to the bit line 30. The row line 20 is charged by a row decoder 21 and connected to a dynamic storage cell 32. The dynamic storage cell 32 includes an access transistor 34 and a storage capacitor 36. access·
The gate terminal of transistor 34 is connected to line 20 and its source terminal is connected to the first terminal of storage capacitor 36. The remaining terminals of the storage capacitor 36 are connected to the ground connection 28. The drain terminal of the access transistor 34 is connected to the bit line 38. When driving row line 18 to a high voltage state,
The corresponding access transistor 24 is activated,
A conductive path is formed between bit line 30 and storage capacitor 26. The row line voltage selected by the row decoder is illustrated by the timing signal 40 shown in FIG. Sense amplifier 44 is activated in response to a latch signal transmitted via latch connection 46. Latch signal L is illustrated as waveform 48 in FIG. The storage device 10 includes transistors 50 and 52
Is provided. The source and drain terminals of transistor 50 are connected between bit line 30 and latch connection 46, and the source and drain terminals of transistor 52 are connected between bit line 38 and latch connection 46. Each transistor 50,
The gate terminal of 52 is connected to a connection section 54 that receives the balanced signal E. The balanced signal E is illustrated as a waveform 56 in FIG. When the balanced signal E is set to a high voltage state, each transistor 50, 52 is turned on and connects each bit line 30, 38 to the connection 46. The pull-up circuit 60 is connected to the bit line 30 via a line 62. The pull-up circuit 60 operates in response to the precharge signals P ₀ and P ₁ illustrated as waveforms 63, 64 and 66 in FIG. 2, respectively. A similar pull-up circuit 68 is connected to bit line 38 via line 70. Each pull-up circuit 60, 68 detects when the voltage on the corresponding bit line is higher than a previously set voltage level, and upon receiving a precharge signal, raises the bit line to a supply voltage as described below. . Each bit line is provided with a column transistor for transmitting the data state within and from each storage cell. The source terminal and the drain terminal of the column transistor 74 are connected between the bit line 30 and the input / output line 76. The gate terminal of the column transistor 74 is connected to the column decoder 16. Similarly, the drain terminal and the source terminal of the column transistor 80 are connected between the bit line 38 and the input / output line 82. The gate terminal of the column transistor 80 is connected to the column decoder 17 which responds to the same column address signal as the column decoder 16. Each column decoder 16, 17 activates a selected column transistor in response to a column address bit received via address line 12 to transmit a data state to and from the addressed storage cell. The input / output lines 76, 82 are connected to an input / output circuit 84 which serves to transmit data states written into and read from each storage cell.
The data action is received from an external circuit via the data input terminal 86 and transmitted to the external circuit via the data output terminal 87. Next, a dynamic constant speed call storage device 1 according to the present invention.
The operation of 0 will be described with reference to FIGS. 1, 2, 3 and 4. This circuit is operated by a power supply of 5.0V. The storage cycle is based on the row address strobe (RA
S) Started by signal 90. The RAS signal 90 is activated when transitioning from the high level to the low level. The row address bits are provided at row 14 as shown by waveform 92a. The row address bits are received immediately after the RAS signal goes active. Row decoder 14
Sends a row enable signal 40 to the selected row line. When row enable signal 40 goes to a level of 5 volts, access transistor 24 in storage cell 22
Becomes conductive, and the storage capacitor 26 is connected to the bit line 30.
Connect to Bit lines 30, 38 have been previously balanced to a voltage level of about 2.0 volts, as shown by waveform 96. If storage capacitor 26 had previously been charged to the stored level of 5.0 volts, bit line 30 would cause waveform 96a in FIG. 2 to share charge between storage capacitor 26 and bit line 30. Is driven to about 2.3V as indicated by. However, if storage capacitor 26 had previously been discharged to ground potential, bit line 30 would be at about 1.8V, as shown by waveform 96b. After the storage cell 22 is connected to the bit line 30, the latch signal L shown as a waveform 48 goes to ground potential. Sense amplifier 44 responds to the latch signal by bringing one of the bit lines connected to it and at the lower voltage to ground. If the capacitor 26 had previously been discharged, the voltage on the bit line 30 would be as shown by waveform 96b when this voltage was brought to ground potential. However, if storage capacitor 26 is charged to the stored high voltage level as shown by waveform 96a, bit line 30 will not be affected by the operation of sense amplifier 44. However, if bit line 30 has risen to the voltage shown by waveform 96a, bit line 30 will become bit line 38 shown as waveform 98.
, The bit line 38 goes to ground potential as shown by the waveform 98a. However, if the voltage on bit line 30 is pulled down by storage capacitor 26, the balanced voltage on bit line 38 will not be affected by sense amplifier 44. This state is shown by the waveform 98b. After the sense amplifier 44 lowers one of the bit lines to the ground potential, and after precharging the pull-up circuits 60 and 68 with the precharge signal P, the precharge signals P ₀ and P ₁ are received and Up circuit 60,
68 is started. Each pull-up circuit 60, 68 detects which one of the bit lines has a higher voltage than the previously set voltage. Bit line 1
One will be at ground potential and the other bit line will be at a balanced voltage or elevated pressure caused by connecting to a storage capacitor that has stored a high voltage. Bit lines with high voltages are pulled up to the supply voltage. For a bit line that has received a high charge from a storage cell, this state is indicated by waveform 96.
Indicated by a. Waveforms 98b are shown for bit lines with balanced voltages. At this time, the storage capacitor connected to the bit line has returned to its original voltage. When one of the bit lines is driven to the supply voltage and the other bit line is set to the ground potential, the column transistors 74,
80 is turned on and connects each bit line 30, 38 to input / output lines 76, 82, respectively. The voltage state of each bit line is transmitted to the input / output circuit 84 via each input / output line.
The input / output circuit 84 includes a sense amplifier to detect a differential voltage between the input / output lines 76 and 82. The sense amplifier in the input / output circuit measures the voltage state stored in the storage cell and transmits this voltage state via the data output line 87. After one of the bit lines is at ground potential and the other bit line is at supply voltage, the data state in the storage cell is stored again. And the line 18 returns to ground potential,
Separates the charge on the storage capacitor. These bit lines are then left floating. Then the balanced signal 56 is
In addition to the gate terminals of the transistors 50 and 52, the transistors 50 and 52 are turned on, and the bit line 30 is connected to the bit line 38 via the latch connection 46. This connection shares the charge with each bit line, and these bit lines are balanced to a voltage approximately halfway between the supply voltage and ground potential. This is shown in both waveforms 96 and 98. In this case, each of the waveforms 96 and 98 returns to the balanced voltage of 2V. A representative circuit for the sense amplifier 44 shown in FIG. 1 is illustrated in FIG. The source terminal and the drain terminal of the pass transistor 104 are connected to the bit line 3
0 and the connection portion 106. The second pass transistor 108 has a source terminal and a drain terminal connected between the bit line 38 and the connection part 110. The gate terminals of both transistors 104, 108 are connected to a high voltage source such as the supply voltage _Vcc . Each transistor 104, 108 is always conductive and acts as a resistor. The transistor 112 has a drain terminal connected to the connection portion 106, a source terminal connected to the connection portion 46, and a gate terminal connected to the connection portion 106. The operation of the sense amplifier occurs after the storage cell is connected to one of the bit lines, ie, line 30 or line 38. One of the bit lines is now at a higher voltage than the other bit line. For example, it is assumed that the bit line 30 has a higher voltage. Latch signal L (waveform 4 in FIG. 2)
8), the bias from the gate to the source of the transistor 114 is larger than the bias from the gate to the source of the transistor 112, so that the transistor 114 is
Turned on before transistor 112. When transistor 114 conducts, connection 110 is discharged through transistor 114 to latch connection 46. When the connection portion 110 is discharged, the gate bias of the transistor 112 is reduced, so that the transistor 112 is not turned on. When the latch signal is pulled down to ground potential, transistor 114 remains conductive. This is because the bit line 30 and the connection unit 106 remain in the previous high charge state. When the connection portion 110 is discharged, the transistor 108
, The bit 38 is discharged. That is, the bit line 38 also goes to the ground potential after the latch signal goes to the ground potential. If the line 38 goes to a higher voltage after the storage cell is connected to one of the bit lines, the transistor 112 becomes conductive and the connection 106 is discharged to bring the bit line to ground potential. The circuit diagram of the pull-up circuits 60 and 68 is shown in FIG.
This is illustrated in the figure. The drain terminal of the transistor 120 is connected to the _Vcc power supply, the source terminal is connected to the connection unit 122, and the gate terminal is connected to receive the precharge signal P. The drain terminal of the transistor 124 is connected to the connection portion 122, the source terminal is connected to the bit line 30, a gate terminal connected to receive a precharge signal P _0. The drain terminal of the transistor 126 is connected to receive the precharge signal P ₁ , the gate terminal is connected to the connection section 122, and the source terminal is connected to the gate terminal of the transistor 128. The drain terminal of the transistor 128 is connected to the _Vcc power supply, and the source terminal is connected to the bit line 30. When receiving precharge signal P, transistor 120 is turned on to precharge connection 122 to a high voltage state. When the precharge signal returns to a lower voltage level, connection 122 remains floating at the higher voltage state. Precharge signal P ₀ is about 2V
, When the bit line 30 is at a sufficiently low voltage state, the transistor 124 is turned on and the transistor 1
There is at least one transistor threshold voltage between the 24 gate and source terminals. Transistor 12
When 4 conducts, the connection section 122 is discharged to the bit line 30. [0026] However, when the charge of the bit line is less than one transistor threshold voltage between sufficiently high gate and source terminals of the transistor 124, the transistor 124 does not become in a conductive state by the precharge signal P ₀ The connection 122 is left floating at the higher voltage level. The P signal is then applied to the drain terminal of transistor 126. When connection 122 is at a high voltage, transistor 126 conducts and transistor 126
The source is to follow the signal _{P 1} of more than _{V cc} of. This bootstraps connection 122 to a high voltage level due to the channel capacitance of transistor 126. Yotsute full voltage level of the precharge signal P ₁ which is bootstrapped applied to the gate terminal of the transistor 128, the total supply voltage V _cc is by applied to the bit line 30, the bit line voltage state of V _cc .
That is, when the voltage of the bit line 30 is higher than the previously set level, the bit line is
The operation of 0 raises the supply voltage, but if the voltage on bit line 30 is lower than the previously set level, precharge circuit 60 does not affect bit line 30. In essence, the present invention resides in a dynamic constant speed call storage device that balances each bit line to about half the supply voltage before connecting a storage cell to each bit line. The sense amplifier detects a voltage difference between the bit lines caused by connecting the storage capacitor to one of the bit lines, and sets the bit line having the lower voltage to the ground potential. The pull-up circuit sets the bit line having the higher voltage to a high voltage. After transferring the voltage state via the input / output lines and after separating the memory cells,
Each bit line is floated and interconnected via a latch connection so that the bit lines return to a balanced voltage by charge transfer between the bit lines. More specifically, the operation and effect of the pull-up circuit will be described. Each of the pull-up circuits (60, 68) detects the voltage on the bit line connected thereto and performs one of the following two operations. That is, when the voltage on the connected bit line is higher than a predetermined level, the voltage on that bit line is raised to the supply voltage _Vcc . On the other hand, when the voltage on the connected bit line is lower than a predetermined level, it has no effect on the voltage on the bit line. The pull-up circuit is suitable for writing the maximum voltage to the storage capacitor at the end of a read cycle, in addition to providing sufficient potential difference between the bit lines to be sensed by the sense amplifier in the input / output circuit. It has an important function of pulling up a necessary bit line to _Vcc . The function of this pull-up circuit is obtained by the transistor shown in FIG. First
Is supplied to the transistor 120, and this transistor is turned on. The precharge connection unit 122 enters a high voltage state. Next, the first precharge signal is removed, and the precharge connection section 122 floats. Next, the second precharge signal P ₀ is supplied to the transistor 124, if the bit line 30 is a low voltage state, the precharge connection portion 122 becomes the transistor 124 in a conducting state is discharged to the bit line, thus the pull-up circuit Does not affect the voltage on the bit line. However, when the bit line 30 is in a high voltage state, the transistor 124 is not turned on even by the second precharge signal.
Next, a third pre-charge signal _{P 1} the transistor 126
Supplied to Since the precharge connection 122 is in a floating state, the third precharge signal P ₁ can bootstrap the precharge connection 122, so that the full voltage level of the third precharge signal P ₁ is higher than the transistor 126. Is applied to the gate terminal of the transistor 128. Therefore, the entire supply voltage _Vcc is
And the voltage on the bit line is pulled up to _Vcc . This pull-up circuit requires substantially only enough charge to charge the bit line to a high voltage state. That is, there is no direct current path between _Vcc and ground in this pull-up circuit at any time. This pull-up circuit functions to directly turn off the bit line. There is no need to detect the potential difference between the two bit lines to determine which of the two bit lines is raised to _Vcc . This allows the pull-up circuit to be located at the end of the bit line, not between the two bit lines where the sense amplifier is located. By locating the pull-up circuit at the end of the bit line, the effect of shortening the memory access time can be obtained. This is because the input / output circuit connected near the end of the bit line, ie, the pull-up circuit, does not need to wait for the pull-up voltage to propagate down the bit line (the bit line is relatively high). Due to the capacitance, there is a considerable delay for the voltage pulse applied to one end to reach the other end). That is, since the potential difference between all the bit lines is applied to the input / output circuit, and thus the human / output circuit can be enabled immediately after the pull-up circuit is enabled, the speed can be increased. While one embodiment of the present invention has been illustrated and described in detail in the accompanying drawings, it is to be understood that the invention is not limited to the described embodiment, and that various changes and modifications may be made without departing from the scope of the invention. Of course.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of an embodiment of a dynamic constant-speed call storage device according to the present invention. FIG. 2 is a timing diagram of various signals generated in the dynamic constant-speed call storage device illustrated in FIG. 1; FIG. 3 is a circuit diagram of the sense amplifier shown in FIG. 1; FIG. 4 is a circuit diagram of a pull-up circuit shown in FIG. 1; [Description of Signs] 10 Storage device 22, 32 Dynamic storage cell 30, 38 Bit line 44 Sense amplifier 60, 68 Pull-up circuit 84 Input / output circuit

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Prevstaying, Rabat, Jei               Dara, 75248, Texas, United States               Su, Harvest Glen 6623                (56) References JP-A-54-101228 (JP, A)                 JP-A-55-70990 (JP, A)                 JP-A-54-101229 (JP, A)                 JP-A-53-544430 (JP, A)                 JP-A-53-128940 (JP, A)

Claims (1)

(57) [Claims] (A) storing a first voltage state corresponding to the first data state and a second voltage state corresponding to the second data state in the dynamic storage cell; and (b) a pair of bit lines. Is set to a third voltage state, the dynamic memory cell is connected to one of the bit lines, and when the first voltage state is stored in the memory cell, Connect the connected bit line to the fourth
Or when the second voltage state is stored in the storage cell, the bit line connected to the storage cell is driven to a fifth voltage state. and maintaining the other bit line of the bit line to the third voltage state, the relative voltage condition between the two bit lines in the sense amplifier connected to the two bit lines during (c) sensing operation Sensing the difference and driving the bit line with the lower voltage of the two bit lines to a lower voltage state; and (d) switching the other of the bit lines with the higher voltage to (E) disconnecting the storage cell from the corresponding bit line to float each of the bit lines; and (f) connecting the two bit lines to the high voltage state. Sense amplifier floating latch Connecting to each other via a connection to balance the voltages of said two bit lines to said third voltage state, comprising: Operation method.