JPH01126788A - Portable medium - Google Patents

Abstract

PURPOSE:To always carry out the voltage drop of a battery at a correct detecting point by providing a single resistance to generate the checked battery in a battery checking circuit at the outside of a LSI, and selecting a suitable resistance value at the time of manufacture. CONSTITUTION:When a CPU 28 is activated, the CPU 28 supplies an envelope signal, turns on semiconductor switches 141 and 142, and impresses a reference voltage Vref generated by a Zener diode 149 to the non-inverted input edge of a differential amplifier 145. On the other hand, a checking voltage VCH divided by a variable resistor 148, which provides a voltage VDD of an internal battery 25 at the outside of an IC, and a resistance 147 is impressed on the inverted input edge of the differential amplifier 145. Thus, when the checking voltage VCH is smaller than the reference voltage Vref, the differential amplifier 145 outputs a battery alarm signal through an inverter circuit 143 to the CPU 28.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention has a built-in CPU, data memory, internal battery, etc., and can be used as a stand-alone card in calculators, time displays, etc., or as a terminal device. The present invention relates to portable media such as multifunctional IC cards that can be used by inserting them into a computer.

(Prior technology) Traditionally, cards have a built-in CPU, data memory, internal battery, etc., and have a keyboard, display, etc., and can be used as a standalone card in calculators, time displays, etc., or by being inserted into a single terminal. Multi-functional IC cards have been developed.

Such an IC card is internally equipped with a deterioration detection circuit for detecting deterioration of the internal battery. Such a drop detection circuit compares the reference voltage generated by the voltage from the internal battery using a Zener diode with the voltage to be tested obtained by dividing the voltage from the internal battery using a resistor, and Some devices are being considered that output a battery alarm signal when the voltage drops below a reference voltage.

However, with this type of device, there is a problem in that the low battery detection point differs due to variations in the resistance value of the resistor that creates the voltage to be tested, making it impossible to perform detection at an accurate detection point.

(Problems to be Solved by the Invention) As described above, this invention eliminates the drawback that battery voltage drop cannot be detected at an accurate detection point. The aim is to provide a portable medium that can be used in

[Structure of the Invention] (Means for Solving the Problems) The portable medium of the present invention has at least a control element, and includes a battery that supplies power to the control element;
Voltage generating means generates a voltage to be tested from the voltage of the battery using a resistor that can be set in advance during manufacturing, and the voltage of the battery is determined by comparing the voltage to be tested from this voltage generating means with a reference voltage. It consists of a detection means for detecting.

(Function) This invention generates a voltage to be tested from the voltage of a battery using a resistor that can be set in advance at the time of manufacture, and compares the generated voltage to be tested with a reference voltage to determine the voltage of the battery. It is designed to be detected.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

In FIG. 3, 10 is an IC card as a portable medium, which is a multifunctional card having various functions. For example, it has an online function that is used in conjunction with a terminal device to be described later, an offline function that allows the IC card 10 to operate independently, and a waiting state in which only the clock is counted.

The offline functions mentioned above include a calculator mode that can be used as a calculator, a time mode that displays the time according to the clock used by the user, and an electronic notebook (electronic width) that allows you to register and read out addresses, names, phone numbers, etc. mode,
Alternatively, the IC card 10 can be used alone, such as in a shopping mode in which the IC card 10 is used as a plurality of credit cards.

In the above shopping mode, the used balance, expiration date, shopping record, etc. are stored in the IC card 10, and each time the IC card 10 makes a purchase, the amount spent is deducted from the balance in the IC card 10, and the shopping information is recorded. It is. The above IC card 10
If the balance in the card or the expiration date has expired, it can be updated by having the contracted bank issue a secret code.

On the surface of the IC card 10, a contact section 11 is arranged at a position that matches the card specifications.A keyboard section 12 consisting of 20 keys is arranged on the top surface of the keyboard section 12, and a display section is formed of a liquid crystal display element. (Display means) 13
, and magnetism generating members 14a and 14b are provided.

The contact portion 11 includes, for example, a plurality of terminals 11a to 11a.
llf, and the operating power supply voltage (V
It consists of terminals for cc, +5V), write power supply voltage for EEPROM, ground, clock signal, reset signal, and data input/output.

The keyboard section 12 has selection keys (TI, T2, T3, T4) 1.2a for selecting processing corresponding to card types, ie, various credit cards, cash cards, etc.
, Numeric keypad 12b1 Four arithmetic operation keys as function keys, that is, addition (+) key 12C1 Subtraction (-) key 1
2d1 Division (÷) key 12e1 Multiplication (×) key 12f1
Decimal point (,) key 12g1 and equal (-) key 1
It is composed of 2h.

The addition key 12c is used as a NEXT key, that is, a mode selection key for selecting a mode during offline date and time display, and the subtraction key 12d is used as a BACK key.
This key is used as a key to return the display state of the display section 13 to the previous state, the multiplication key 12f is used as a start key, the decimal -6= point key 12g is used as a NO key and an end key, and the equal key 12h is used as a NO key. is used as a YES key and a NOWARE ON key.

For example, equal key 12h as a power-on key
When is pressed, the CPU (to be described later) is released from the HALT state, and the time and date of the operation start message are displayed on the display 13.
to be displayed.

In this state, when the numeric keypad 12b is pressed, the IC card 10 enters a calculator mode, and four arithmetic operations can be performed.

Further, the addition key 12c as a mode selection key is used as a key to advance the display state of the display section 13 which is currently displaying the date and time to another mode, and displays menus on the display section 13 such as electronic width, time set, and date. Each time the key is pressed, the transaction mode such as set, purchase, etc. is displayed. When executing these modes, press the equal key 12h above.
By pressing the YES key, the mode is entered and execution becomes possible.

The display section 13 is a 16-digit dot matrix with each digit being 5×7.

The magnetism generating members 14a and 14b are embedded inside the IC card 10 in alignment with the track positions of a magnetic card reader (magnetic head) on the reading side (not shown).

FIG. 4 shows an IC card reading/writing unit 1 used in a terminal such as a personal computer that handles an IC card 10.
This shows the appearance of No. 6. In other words, card insertion slot 1
By connecting with the contact part 11 of the IC card 10 inserted from 7, data in the memory of the IC card 10 can be read or data can be written into the memory.

The IC card reading/writing section 16 is connected to the main body of a personal computer (not shown) by a cable.

Further, the electric circuit of the IC card 10 is constructed as shown in FIG. That is, the contact portion 1
1. A communication control circuit 21, a reset control circuit 22, a power supply control circuit 23, an internal battery (built-in power supply) 25 of, for example, 3 volts, and an offline IC card 10 that determines whether the voltage value of this internal battery 25 is higher than a specified value. Battery check circuit 2 that checks only once when starting to use the
4 (described in detail in FIG. 10), a clock control circuit 26, and an oscillator 2 which is a crystal oscillator for oscillating a calculation clock and outputs a signal with an oscillation frequency of 200KH2 (high-speed clock).
7. CPU for control (central processing
unit) 28, program ROM 29 in which control programs are recorded, program working memory 30
, a password, data, etc., are recorded therein, and are composed of a data memory 31 composed of a FROM, a timer 32 used for timing during processing operations, a calendar circuit 33, and a crystal oscillator for basic clock oscillation. An oscillator 34 outputting a signal with an oscillation frequency (low-speed clock) of 768KH2, a display control circuit 35, a display driver 36 for driving the display 13, a keyboard interface 38 as a key input circuit for the keyboard 12, and a magnetism generating member control circuit 40 that controls the magnetism generating members 14a and 14b.

The communication control circuit 21, reset control circuit 22, power supply control circuit 23, battery check circuit 24, clock control circuit 26, CPU 28, ROM 29, program working memory 30, timer 32, calendar circuit 33, display control circuit 35, keyboard interface 38,
The magnetism generating member control circuit 40 is constituted by a one-chip microcomputer, and is an LSI 150.

The communication control circuit 21, CPU 28, ROM 29, program working memory 30, data memory 31, timer 32, calendar circuit 33, display control circuit 35, keyboard interface 38, and magnetism generation for controlling the magnetism generation members 14a and 14b. Component control circuit 40
are connected by a data bus 20.

When the communication control circuit 21 receives data, that is, the terminal 16
The serial input/output signals supplied from the contact section 11 are converted into parallel data and sent to the data bus 2.
0, and during transmission, that is, parallel data supplied from the data bus 20 is converted into a serial input/output signal and output to the terminal 16 via the contact section 11. In this case, the format contents of the conversion are determined by the terminal device 16 and the IC card 10.

When the reset control circuit 22 goes online, it generates a reset signal and starts the CPU 28.

When the power supply control circuit 23 goes online, it switches from being driven by the internal battery 25 to being driven by an external power supply after a predetermined period of time has elapsed, and when it goes offline, that is, when the external voltage drops, it switches from being driven by the external power source to being driven by the external power source. The drive is switched to the battery 25.

The battery check circuit 24 creates a reference voltage Vref from the voltage of the internal battery 25 using a Zener diode, and compares and checks the voltage value of the internal battery 25 with a check voltage VCH obtained by dividing the voltage value of the internal battery 25 using a comparator. and the voltage value of the internal battery 25 is 2.5
When the voltage exceeds volts, the battery alarm signal is set to CP.
It is output to U28. The battery check circuit 24 has a reference voltage Vref and a check voltage VC).
Current flows through the circuit that creates I only once at the time of detection, that is, when the power-on key is input in offline mode and before the time and date are displayed. If a dispersion alarm occurs due to this detection, CALL-BANK etc. will be displayed instead of the time and date.
The system notifies the operator that the battery is at the end of its life, and if no alarm has been activated, the time and date are displayed and the operator can proceed to the next menu selection.

The clock control circuit 26 switches between a low-speed clock and a high-speed clock in a timely manner in the offline mode in which the card operates with the internal battery 25, and also controls the oscillation frequency of 200 KH2 (described later) for power down after executing the HALT command. The oscillation circuit (second clock generation means) 67 that outputs a high-speed clock signal is stopped, and the clock supply to the CPU 28 is also stopped, so that the CPU 28 stands by in a completely stopped state. The clock control circuit 26 is basically configured to select a clock mode when a reset or HALT command is executed.

The data memory 31 records information corresponding to a plurality of contracted credit cards (companies) and information corresponding to a cash card.
The information is read out in accordance with the type of card selected by the keys 12a1, . . . The above information is the same as the information recorded on the conventional magnetic stripe for each card. For example, first track data corresponding to the first track of the card and second track data corresponding to the second track are stored.

The calendar circuit 33 has a display clock that can be freely set and changed by the card holder, and, for example, sets the world standard time at the time of card issuance, and then performs transactions that cannot be changed. I have a watch for the day.

The display unit control circuit 35 converts the display data supplied from the CPU 2g into a character pattern using a character generator (not shown) configured with an internal ROM, and converts the display data supplied from the CPU 2g into a character pattern on the display unit 13 using the display unit driver 36. It is to be displayed.

The keyboard interface 38 converts keys input on the keyboard section 12 into human input signals corresponding to keys, and outputs the signals to the CPU 28.

When a shopping mode and a card type are specified, the magnetism generating member control circuit 40 controls the data and reading device supplied from the data memory 31 via the data bus 20 in accordance with the card type. By controlling the drive of the magnetism generating members 14a and 14b according to the drive rate corresponding to manual reading or automatic conveyance reading, and outputting first track data and second track data as magnetic information. , which is in the same state as a conventional magnetic stripe.

For example, in the case of manual reading, a drive rate with a fast reading speed is selected, and in the case of automatic conveyance reading, a drive rate with a slow reading speed is selected.

When the shopping mode is designated, the magnetism generating member control circuit 40 sequentially generates magnetic information (data for the first track, data for the second track) from the magnetic generating members 14a and 14b in accordance with the type of card. data).

The power supply control circuit 23 will be explained in detail using FIG. 5. In other words, Inno Ku Ichiyo Circuit 51.54.5
5. Counter 52, D-type flip-flop circuit (FF
circuit) 53, semiconductor switch 56, 58 composed of MOSFET, diode 57, and internal battery 25
It is made up of.

The count value of the counter 52 is a value that is not affected by chattering of the external power supply. The above diode 57
is for protecting the power supply voltage Vout, and when the power supply voltage VCC from the outside decreases, the power supply voltage Vout will not drop even if the power supply voltage VCC drops below the memory drive voltage before the semiconductor switch 56 is turned on. As shown, it is protected by an internal battery 25.

The operation of this configuration will be described with reference to the timing chart shown in FIG. That is, when the IC card 10 is not connected to the terminal device 16 through the contact section 11, the semiconductor switch 56 is turned on.
The power supply voltage of the internal battery 25 is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

Further, when the IC card 10 is connected to the terminal device 16 through the contact section 11, an external power supply voltage Vcc is supplied to the gate of the semiconductor switch 58, and a clock signal CLK is supplied to the counter 52 via the inverter circuit 51. is supplied to the clock terminal ck of. As a result, the counter 52 starts counting, and when the value of the counter 52 reaches a predetermined value, the FF circuit 5
Set 3. Due to the set output Q of the FF circuit 53, a "0" signal is supplied to the gate of the semiconductor switch 58, a "1" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned on, and the semiconductor switch 56 is turned off. Therefore, the external power supply voltage Vcc is applied to the output Vo of the power supply control circuit 22 via the semiconductor switch 58.
It is applied to each part as ut.

Note that when returning from the online state to the offline state, a reset signal is output from the reset control circuit 22 when the external power supply voltage Vcc decreases. This results in
The reset signal causes the counter 52 and the FF circuit 53 to
is reset. Then, a "1" signal is supplied to the gate of the semiconductor switch 58, a "0" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned off, and the semiconductor switch 56 is turned on. Therefore, the power supply voltage of the internal battery 25 is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

The battery check circuit 24 will be explained in detail with reference to FIG. That is, semiconductor switch 141.
142, inverter circuits 143 and 144, a differential amplifier 145 as a comparator, resistors 146, 147, and 148, a Zener diode 149, and an OR circuit 150.

That is, an envelope signal is supplied from the CPU 28 to the bases of the semiconductor switches 141 and 142 via the OR circuit 150 and the inverter circuit 144. Then, the semiconductor switches 141 and 142 are turned on, and the reference voltage Vref generated by the Zener diode 149 is applied to the non-inverting input terminal of the differential amplifier 145. Also,
The voltage value VDD of the internal battery 25 is set by the resistor 148 and the resistor 1.
A check voltage (voltage to be inspected) VCH divided by 47 is applied to the inverting input terminal of the differential amplifier 145. As a result, the differential amplifier 145 receives the check voltage V. When H becomes smaller than the reference voltage Vref, the inverter circuit 14
3, outputs a battery alarm signal to the CPU 28.

In this way, the resistor 14 is only used when checking the battery voltage.
6, Zener diode 149, and resistor 147.1
48, the current consumption can be reduced compared to when current is constantly flowing.

The resistor 148 is a resistor connected to the outside of the LSI 150, and is connected to the inverting input terminal of the differential amplifier 145 when the voltage value VDD of the internal battery 25 becomes 2.5 volts or less during manufacturing. Check voltage VCH supplied
A resistance value is selected such that the voltage becomes smaller than the reference voltage Vref supplied to the non-inverting input terminal, and a battery alarm signal is output from the differential amplifier 145.

The selection of this resistor 148 will be explained with reference to FIG. That is, an external testing device 160 is connected to the L SI 150. The external inspection device 160 includes a relay (not shown) and a plurality of resistors having different resistance values selected by the relay. in this case,
The external inspection device 160 applies 2.5 volts to the batt p a % pb for the internal battery 25 of the LS1150, outputs a test signal to the test batt PC, and the resistance selected by the relay is applied between the batts pdSpe. It is meant to be inserted. In this state, by switching the relay and matching resistors with different resistance values, when the battery alarm signal is output from the output batt PF,
A resistor having a resistance value at that time is selected as the resistor 148.

That is, a test signal from the external testing device 160 is supplied to the bases of the semiconductor switches 141 and 142 via the OR circuit 150 and the inverter circuit 144. Then, the semiconductor switches 141 and 142 are turned on, and the reference voltage Vref generated by the Zener diode 149 is turned on.
is applied to the non-inverting input terminal of differential amplifier 145. In addition, a check voltage (voltage to be tested) V obtained by dividing the voltage value VDD (constant 2.5 V) of the internal battery 25 by a resistor (not shown) in the external test device 160 and a resistor 147 is applied.
CH is applied to the inverting input terminal of differential amplifier 145. As a result, the differential amplifier 145 receives the check voltage V. When H becomes smaller than the reference voltage Vref, a battery alarm signal is output to the external inspection device 160 via the inverter circuit 143.

Therefore, in order to solve the problem that when all the battery check circuits 24 are mounted in the LSI 150, the low battery detection point varies from lot to lot, the battery check circuit 24 is installed as described above. One of the resistors 24 is provided externally, and an appropriate resistor is selected at the time of manufacture. Thereby, there is no variation in the battery drop detection point, and it is possible to accurately detect the voltage drop of the internal battery 25.

The clock control circuit 26 will be explained in detail using diagram N7. That is, the stop signal HALT from the CPU 28 is supplied to the clock input terminal ck of the FF circuit 62. The set output of this FF circuit 62 is
The machine cycle small signal M1 from the CPU 28 is supplied to the clock input terminal ck of this FF circuit 63. The FF circuits 62 and 63 are used for stop mode timing. Above FF circuit 6
The set output of 3 is supplied to the data input terminal of the FF circuit 64, and the clock input terminal ck of this FF circuit 64 is supplied with the clock of 32.763KH2 from the calendar circuit 33. The reset output of the FF circuit 64 is supplied to the data input terminal of the FF circuit 65, and the clock input terminal ck of this FF circuit 65 is supplied with the clock of 32.763KH2 from the calendar circuit 33. . The FF circuit 65 is used to stop clock oscillation. The set output of the FF circuit 65 is supplied to one end of an AND circuit 66, and the other end of this AND circuit 132 is supplied with a forced stop signal from the CPU 28. The output of the AND circuit 132 is supplied to one end of the NAND circuit 66.
An oscillation circuit 67 is connected between the output end of 6 and the other end.

Further, the key human interrupt signal from the CPU 28 and the reset signal from the reset control circuit 22 are supplied to the reset input terminals R of the FF circuits 62.6B and 64 via the OR circuit 61, and circuit 6
It is supplied to the set input terminal S of No. 5.

The oscillation circuit 67 includes the oscillator 27 having an oscillation frequency of 200KH2, a resistor 68, and capacitors 70 and 71.

The output of the NAND circuit 66 is supplied to the clock input terminal ck of the FF circuit 74 and the clock input terminal ck of the binary counter 130 via the inverter circuit 72, and to one end of the NAND circuit 75 via the inverter circuits 72 and 73. Supplied.

The binary counter 130 counts the oscillation clocks generated by the oscillation circuit 67, and outputs a signal from the output terminal Qn when the counted value reaches a predetermined value. The signal from the output terminal Qn of the binary counter 130 is FF
is supplied to the clock input terminal ck of the circuit 131, and this FF
The ready signal as the set output of the circuit 131 is the CPU2
8.

The FF circuit 131 is set by the output of the binary counter 130, so that the oscillation circuit 67
It is set when the is in the ready state.

Further, the reset signal from the reset control circuit 22 is supplied to the set input terminal S of the FF circuit 77, and the clock selection signal from the CPU 28 is supplied to the data input terminal of the FF circuit 77. A clock of 32.763KH2 from the calendar circuit 33 is supplied to ck. The set output of the FF circuit 77 is supplied to one end of a NAND circuit 79, and the other end of the NAND circuit 79 is supplied with 32.76 ms of the calendar circuit 33.
A 3KH2 clock is supplied via an inverter circuit 78. The output of the NAND circuit 79 is supplied to one end of the NAND circuit 8o.

Further, the reset output of the FF circuit 77 is supplied to the data input end of the FF circuit 74, and the set output of this FF circuit 74 is supplied to the other end of the NAND circuit 75. The FF circuit 74 is used for clock switching.

The outputs of the NAND circuits 75 and 79 are supplied to the NAND circuit 80, and the outputs of the NAND circuit 80 are fed to the FF circuits 81 and 81.
3 is supplied to the clock input terminal ck of the FF circuit 81.
The set output of the FF circuit 63 is supplied to the data input terminal of the FF circuit 63 via an inverter circuit 82.

Further, the set output of the FF circuit 83 is provided by a NAND circuit 86.
The output of the AND circuit 80 is supplied to the other end of the NAND circuit 86 via the inverter circuit 85. The output of the NAND circuit 86 is output to the CPU 28 as a clock signal.

The operation in such a configuration will be explained. First, the stopped state will be explained. That is, "1" is supplied from the CPU 28 as the clock selection signal. As a result, the FF circuit 77 is set. This results in
Watch clock (32,768KH2) is connected to FF via i', bar'i' circuit 78, and NAND circuit 79.8o.
It is led to circuits 81, 82 and an inverter circuit 85.

Next, restarting from a stopped state will be explained.

In other words, when the YES key (equal key) 12h is pressed as the power-on key, a key interruption signal is supplied from the CPU 28.

Then, the FF circuits 62, 63, and 64 are reset, and the FF circuits 62, 63, and 64 are reset.
Circuit 65 sets. The set output of the FF circuit 65 enables the oscillation circuit 67. As a result, the oscillation circuit 67 starts oscillating.

Furthermore, by resetting the FF circuit 63, the FF circuit 8
“1” is supplied to the data input end of “1”. As a result, the output of the NAND circuit 8o causes the FF circuit 8
1.83 is set and opens the gate of NAND circuit 86.

Therefore, the clock from the inverter circuit 85 is output to the CPU 28 via the NAND circuit 86. Therefore, the CPU 28 is operated by the low speed clock from the FF circuit 86 and performs various processes.

Also, the clock (200KH2) by the oscillation circuit 67
is supplied to the clock input terminal of the FF circuit 74 and the clock input terminal of the binary counter 130 via the inverter circuit 72.

Also, the oscillation circuit 67 is controlled by the binary counter 130.
The clocks are counted, and when a predetermined count value is reached, the FF circuit 131 is set by the output.

Then, when a predetermined period of time has elapsed since the key input signal was output, the CPU 28 senses whether the FF circuit 131 is set, thereby determining whether the oscillation circuit 67 is operating normally (oscillating). to judge. That is,
If the FF circuit 131 is set, the oscillation circuit 67 is determined to be normal; if the FF circuit 131 is not set, the oscillation circuit 67 is determined to be abnormal.

As a result of this determination, if the oscillation circuit 67 is normal, the CPU 28 determines to operate with the high speed clock, and if the oscillation circuit 67 is abnormal, the CPU 28 determines to operate with the low speed clock.

If it is determined that the oscillation circuit 67 is normal as described above, the CP
O28 outputs "0" as a clock selection signal to the FF circuit 7.
7 data input end. As a result, the FF circuit 77 is reset, and the reset output of the FF circuit 77, that is, the "1" signal is supplied to the data input end of the FF circuit 74.

Then, the FF circuit 74 is set, and the set output opens the gate of the NAND circuit 75. As a result, the clock (200KH2) generated by the oscillation circuit 67 is outputted to the CPU 28 via the inverter circuits 72, 73, the NAND circuits 75, 80, the inverter circuits 85, and the NAND circuits 86 in sequence.

As a result, by setting the clock selection signal to "0", synchronization is achieved in the FF circuit 74, the clock clock (low speed clock) is switched to the high speed clock, and the CPU 28
is designed to start up with a high-speed clock.

After the CPU 28 is started, the CPU 28 sets the clock selection signal to "1", so that the FF circuit 77 is set, and the set output of the FF circuit 77, that is, the "1" signal is supplied to the NAND circuit 79. gate is open. Therefore, the watch clock is output to the CPU 28 via the inverter circuit 78, the NAND circuits 79 and 80, the inverter circuit 85, and the NAND circuit 86 in sequence. As a result, a clock is output to the CPU 28. Therefore, the CPU 28 operates with the low-speed clock from the FF circuit 86 and performs various processes.

Also, at this time, a forced stop signal (“
0" signal) is supplied to the AND circuit 132, the gate of the AND circuit 132 is closed. As a result, the oscillation circuit 67 becomes disabled, and the oscillation circuit 6
7 stops oscillation.

Additionally, if it is determined that the oscillation circuit 67 is abnormal, the CPU 28
supplies a forced stop signal (“0” signal) to the AND circuit −29=132 while supplying 1″ as a clock selection signal to the data input end of the FF circuit 77. In the state in which the oscillation circuit 67 is outputted, the oscillation circuit 67 enters a disabled state, and the oscillation circuit 67 stops oscillating.

As a result, a clock is output to the CPU 28.

Therefore, the CPU 28 operates with the low-speed clock from the FF circuit 86 and performs various processes.

Next, an explanation will be given of the operation when a specific process such as a transaction mode is selected as the above process.

That is, first, when the transaction mode is selected, the CPU 2
8 stops supplying the forced stop signal to the AND circuit 132.

Then, the set output of the FF circuit 65 is output to the AND circuit 1 again.
32 to the oscillation circuit 67, and the oscillation circuit 67 is enabled. As a result, the oscillation circuit 67 starts oscillating.

As a result, the clock (200
KH2) is supplied to the clock input terminal of the FF circuit 74 and the clock input terminal of the pinary counter 130 via the inverter circuit 72.

Also, the oscillation circuit 67 is controlled by the binary counter 130.
The clocks are counted, and when a predetermined count value is reached, the FF circuit 131 is set by the output.

When calculating the transaction completion code in the shopping mode, the CPU 28 determines whether the oscillation circuit 67 is operating normally (oscillating) by sensing whether the FF circuit 131 is set. That is, if the FF circuit 131 is set, the oscillation circuit 67 is determined to be normal, and if the FF circuit 131 is not set, the oscillation circuit 67 is determined to be abnormal.

As a result of this judgment, if the oscillation circuit 67 is normal, the CPU 2
8 supplies "0" to the data input end of the FF circuit 77 as a clock selection signal. As a result, the FF circuit 77 is reset, and the reset output of the FF circuit 77 becomes "1".
A signal is supplied to the data input end of the FF circuit 74.

Then, the FF circuit 74 is set, and the set output opens the gate of the NAND circuit 75. As a result, the clock (200KH2) generated by the oscillation circuit 67 is outputted to the CPU 28 via the inverter circuits 72, 73, the NAND circuits 75, 80, the inverter circuits 85, and the NAND circuits 86 in sequence.

As a result, by setting the clock selection signal to II O#, synchronization is achieved in the FF circuit 74, the clock clock (low speed clock) is switched to the high speed clock, and the CPU
28 is operated by a high-speed clock and calculates the transaction completion code.

After calculating the transaction completion code by the CPU 28, the CP
By setting the clock selection signal to “1”, U28
The FF circuit 77 is set, the set output of the FF circuit 77, that is, the "1" signal is supplied to the NAND circuit 79, and the gate of the NAND circuit 79 is open. Therefore, the clock for the watch is the inverter circuit 78, the NAND circuit 79.80,
The signal is sequentially output to the CPU 28 via an inverter circuit 85 and a NAND circuit 86. As a result, a clock is output to the CPU 28. Therefore, the CPU 28 operates using the low-speed clock from the FF circuit 86.

At this time, a forced stop signal from the CPU 28 is supplied to the AND circuit 132, so that the AND circuit 1
32 gates are closed. As a result, the oscillation circuit 67
becomes disabled, and the oscillation circuit 67 stops oscillating.

Note that if the oscillation circuit 67 is abnormal as a result of the above judgment, C
The PU 28 supplies a forced stop signal to the AND circuit 132 while supplying the clock selection signal "1" to the data input end of the FF circuit 77.

As a result, while the low-speed clock is being output from the FF circuit 86, the oscillation circuit 67 becomes a disabled state, and the oscillation circuit 67 stops oscillating.

As a result, the watch clock is output to the CPU 28 again. Therefore, the CPU 28 operates based on the low-speed clock from the FF circuit 86 and calculates the transaction completion code.

-33= Next, a case will be described in which the processing is ended and the process is brought to a halt state (standby state). That is, the CPU 28 supplies the stop signal HALT to the clock input terminal ck of the FF circuit 62. Then, the FF circuit 62 is set, and the set output is supplied to the data input end of the FF circuit 63.

Then, the FF circuit 63 is set by the machine cycle signal M1 from the CPU 28, and a "0" signal is supplied to the data input terminal of the FF circuit 81. As a result, after the set output of the FF circuit 63 is sent for two pulses to the FF circuits 81 and 83, the gate of the NAND circuit 86 is closed, thereby stopping the output of the clock to the CPU 28. As a result, the CPU 28 is brought to a halted state.

The calendar circuit 33 will be explained in detail using FIG. 8. That is, the oscillator 34 of 32.768 KH2
A frequency dividing circuit 91 outputs signals every second from output terminals a and b by dividing the oscillation output of the frequency dividing circuit 9.
A counter 92 that outputs a signal every 10 seconds by counting the signal from the output terminal a of 1;
A counter 93 that outputs a signal every 60 seconds, that is, every minute, by counting the signals from this counter 93, a counter 94 that outputs a signal every 10 minutes by counting the signals from this counter 93, and a counter 94 that outputs a signal every 10 minutes by counting the signals from this counter 93. A counter 95 that outputs a signal every 60 minutes, that is, every hour, by counting the signals from this counter 95, and a counter 96 that outputs a signal every 24 hours, that is, every day, by counting the signals from this counter 95. A counter 97 outputs a signal every 10 seconds by counting the signal from the output terminal of the circuit 91, and a signal is output every 60 seconds, that is, every minute by counting the signal from this counter 97. Counter 98, which outputs a signal every 10 minutes by counting the signal from this counter 98.
9. A counter 1 that outputs a signal every 60 minutes, that is, every hour, by counting the signal from this counter 99.
001 The counter 101 is configured to count the signals from the counter 100 and output a signal every 24 hours, that is, every day.

Here, the counters 92 to 96 constitute a transaction clock that counts seconds, minutes, and hours, and the counters 97 to 1 constitute a clock for counting seconds, minutes, and hours.
01 constitutes a display clock that counts seconds, minutes, and hours. The contents of the counters 97 to 101, that is, the counted values, can be changed using the keyboard section 12, while the contents of the counters 92 to 96, that is, the counted values cannot be changed using the keyboard section 12.

In addition, the year, month, day, and day of the week are displayed on the counter 9 every 24 hours.
6. In response to the signal from 101, an interrupt request for updating the date is output to the CPU 28.

Thereby, the CPU 28 uses the data memory 31 to update the year, month, day and day of the week of the corresponding area. Also, 2
As shown in FIG. 9, the two clocks shift the phase of the one-second reference clock, so that interrupts do not occur at the same time.

Next, the operation in such a configuration will be explained.

First, we will explain the offline function used by the card alone. That is, in this IC card 10, normally only the clock operates, and the CPU 28 stops (HAL) as described above.
T) state.

In this state, the IC card 10 can only be controlled from the outside by pressing the YES key 12h as a power-on key and in online mode.

This allows the YES key 12h to be used as a power-on key.
Insert. Then, the keyboard interface 38
outputs a key human interrupt signal to the clock control circuit 26. Then, the clock for the clock is supplied from the clock control circuit 26 to the CPU 28, and the C and P U 28 are stopped (H
ALT) state is released. After this, the startup process as described above is performed.

After the CPO 28 is activated, the CPU 28 reads out the seconds, minutes, and hours for the display clock from the counters 97 to 101 in the calendar circuit 33, and also reads the year, month, day, and day of the week for the display clock from the data memory 31, and It is converted into a format and output to the display control circuit 35. As a result, the display control circuit 35 uses an internal character generator (not shown) to convert it into a character pattern, and uses the display driver 36 to alternately display the date and time on the display 13.

As a result, the date and time as a message for starting the operation are displayed on the display section 13.

Then, the CPU 28 stands by with all the keys on the keyboard section 12 ready for reception.

Furthermore, when the CPO 28 is activated, the battery check circuit 24 is accessed to check the voltage value of the battery 25. As a result of this check, if the voltage value of the battery 25 has decreased, the CPU 28 displays the rCALL on the display section 13.
A message such as BANKJ is displayed, and subsequent offline use of the IC card 10 is prohibited.

That is, when the CPU 28 starts up, the envelope signal is supplied from the CPU 28, and the inverter circuit 144
It is supplied to the bases of semiconductor switches 141 and 142 via. Then, the semiconductor switches 141 and 142 are turned on, and the reference voltage Vref generated by the Zener diode 149 is applied to the non-inverting input terminal of the differential amplifier 145.

Also, the voltage value VDD of the internal battery 25 is set to the variable resistor 1.
Check voltage V divided by 48 and resistor 147. H is applied to the inverting input terminal of differential amplifier 145.

As a result, the differential amplifier 145 outputs a battery alarm signal to the CPU 28 via the inverter circuit 143 when the check voltage VCH becomes smaller than the reference voltage Vref. This battery alarm signal causes
The CPU 28 displays a message such as rcALL BANKJ on the display unit 13, informs the operator that the battery has reached the end of its life, and uses the IC card offline from now on]
Prohibit the use of 0.

Further, differential amplifier 145 does not output a battery alarm signal when check voltage VCH is greater than reference voltage Vref. In this case, the display advances to the next time and date display.

Note that the battery check circuit 24 performs the battery drop detection operation as shown in the flow chart shown in FIG.

By pressing the addition key 120 as a mode selection key while the date and time are displayed, different modes are sequentially displayed. Accordingly, when the YES key 12h is pressed while the transaction mode is being displayed, that mode is selected and the CPU 28 displays a reception message and a password input request on the display unit 13.

Further, as described above, depending on the selection of the transaction mode, the CPU 28 controls the oscillation circuit 67 in the clock control circuit 26.
starts high-speed clock oscillation.

When the above-mentioned password input request is displayed, the card user inputs the password using the numeric keypad 12b. Then,
The CPU 28 checks whether the correct password registered on the card has been input, and if the correct password has been entered, the process moves to the next operation.

Furthermore, if it is determined that an incorrect PIN number has been input, if the correct number is input within three times, the PIN error counter in the IC card 10 is reset and the process proceeds to the next operation. However, if you enter the wrong information all three times, rPINERRORJ will be displayed on the display 13, and you will not be able to use this mode from now on until you have your contracted bank issue a secret code and cancel the PIN ERROR on your card. , shopping with the IC card 10 will no longer be possible.

Such a method is a means to improve the security of the card.

If the above PIN is entered correctly, the CPU 28 will display the first menu in transaction mode, ``Do you want to shop?''
is displayed on the display unit 13. At this time, YES key 12
When you input h, it becomes shopping mode. Here, each time the mode selection key 12c is pressed, menus within the transaction mode are sequentially displayed on the display section 13.

When entering the shopping mode, a request to input the shopping amount in the currently selected currency unit is displayed on the display section 13. At this time, as described above, the CPU 28 controls the clock control circuit 2.
It is determined whether the high-speed clock in 6 is normal or not, and if the high-speed clock is normal, a "0" signal is output as a clock selection signal. This allows the clock control circuit 26 to
Change the drive clock to 28 from a low-speed clock (watch clock) to a high-speed clock.

Furthermore, if the high speed clock is abnormal, the drive clock for the CPU 28 is left as the low speed clock.

The purchase amount is input using the numeric keypad 12b according to the above display. Then, the CPU 28 generates a transaction completion code using random numbers, and displays the result and the shopping items alternately on the display unit 13. After the above transaction completion code is generated, C
The PU 28 outputs a "1" signal to the clock control circuit 26 as a clock selection signal. As a result, the drive clock from the clock control circuit 26 to the CPU 28 is returned from the high speed clock to the low speed clock (clock for clock) = 4
2- Leave.

At this point, the IC card 10 is handed over to the store clerk. The clerk is an IC
When the card 10 is received, the IC card 10 is set in a terminal (not shown) equipped with a magnetic tape reader. And I
Insert the YES key 12h of the C card 10. Then,
The CPU 28 sends data similar to that of a conventional magnetic tape card from the magnetism generating members 14a and 14b to the magnetic head of the terminal by controlling the magnetism generating member control circuit 40. If the terminal correctly receives this data, the purchase is completed and this mode ends.

In addition, in stores without terminals, by recording the transaction completion code generated by the IC card 10 or imprinting the embossed characters on the surface of the IC card on a designated slip,
recorded.

Next, the online function used by inserting the IC card 10 into the terminal 16 will be explained. That is,
Insert the IC card 10 into the insertion slot 17 of the terminal 16.

Then, the IC card 10 is accepted, and the connection section inside the terminal 16 and the contact section 11 of the IC card 10 are connected. As a result, when the power supply voltage clock and reset are supplied from the outside via the contact portion 11, the power supply control circuit 23 checks the level of the power supply voltage as described above, and changes the power supply voltage from the internal battery 25 to the external power supply. Switch to power supply voltage drive. Further, due to the above reset, the reset control circuit 22 generates a reset signal, and the CPU 2
8. At this time, the CPU 28 uses the clock from the terminal 16 as a driving clock.

When the reset is released, the CPU 28 executes the program from address 0 of the program ROM 29 using the external clock. When the IC card 10 starts from address 0, it checks the state of the external voltage, and if the external voltage is on and the power down for detecting a drop in the external voltage is not set, it executes the online mode program.

In the online mode, the data communication arrangements prepared in the IC card 10 are first sent to the terminal 16, and then the terminal 16 waits for a command from the terminal 16. Once received, the terminal 16 uses the application to request data from the IC card 10, rewrite the data, and register new data.

The online mode ends when the power supply voltage from the terminal 16 is stopped and the IC card 10 is ejected.

As mentioned above, one resistor for generating the voltage to be tested in the battery check circuit is provided outside the LSI,
Since a suitable resistance value is selected at the time of manufacture, the voltage drop of the battery can always be detected at an accurate detection point.

Note that in the above embodiment, an IC card is used (but is not limited to this; any card having a data memory and a control element and capable of selectively inputting/outputting from the outside may be used, and the shape is also card-like). Instead, it may have another shape such as a rod shape.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a portable medium that can detect a battery voltage drop at an accurate detection point.

[Brief explanation of the drawing]

The drawings are for explaining one embodiment of the present invention, and FIG. 1 shows the configuration of the battery check circuit, FIG. 2 shows the schematic configuration of the electric circuit of the IC card, and FIG. 3 shows the I/O circuit.
FIG. 4 is a plan view showing the configuration of a C card, FIG. 4 is a diagram showing a terminal device that handles IC cards, FIG. 5 is a diagram showing an example of the configuration of a power supply control circuit, and FIG. 7 is a diagram showing the configuration of the clock control circuit, FIG. 8 is a schematic block diagram of the calendar circuit, FIG. 9 is a diagram showing the output timing of the signal from the frequency dividing circuit, and FIG. FIG. 10 is a flowchart for explaining the operation when a low battery is detected, and FIG. 11 is a diagram for explaining the connection state of the external testing device to the LSI. DESCRIPTION OF SYMBOLS 10... IC card (portable medium), 11... Contact part, 12... Keyboard part, 12b... Numeric keypad, 12c... Addition key, 12h... Equal key, 13... Display unit, 24...Battery check circuit, 25...Internal battery (battery), 28...C
PU (control element), 141.142...Semiconductor switch, 147...Resistor, 150...LSI, 160
...External inspection equipment. Applicant's agent Patent attorney Takehiko Suzue Figure 10 Figure 11

Claims (3)

[Claims] (1) In a portable medium having at least a control element, a battery that supplies power to the control element, and a voltage generating means that generates a voltage to be tested from the voltage of the battery using a resistance that can be set in advance during manufacturing. , a detection means for detecting the voltage of the battery by comparing the voltage to be tested from the voltage generation means with a reference voltage. (2) The portable medium according to claim 1, wherein the control element is a CPU. (3) The portable medium according to claim 1, wherein the detection by the detection means is performed only when necessary.