JPS63255788A - Portable medium - Google Patents

Abstract

PURPOSE:To increase a processing speed and to reduce current consumption by using a low frequency clock to operate a control element at the time of indicating the start by an input means and using a high frequency clock to operate the control element at the time of next input operation. CONSTITUTION:A contact part 11 arranged in a position according with the standard of an IC card 10, a keyboard part 12, a display part 13 which is arranged on the upper face of the keyboard part 12 and consists of a liquid crystal display element, and magnetic generating members 14a and 14b are provided on the surface of the IC card 10. A clock control circuit 26 uses the low frequency clock to operate a CPU 28 at the time of indicating the start by the keyboard part 12 and uses the high frequency clock to operate the CPU 28 at the time of next input operation.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention has a built-in CPU, data memory, internal battery, etc., and can be used as a stand-alone card for calculators, timepieces, etc., or as a terminal device. Multifunctional IC that can be used by inserting
Regarding portable media such as cards.

(Prior art) Conventionally, ICs with built-in CPUs, data memory, etc., keyboards, display parts, etc., are used as stand-alone cards in calculators, time displays, etc., or are used for other functions when inserted into terminals. cards are being developed.

When such an IC card is used as a standalone card (offline), a low frequency with low current consumption is used for the CPU clock because the processing operation is performed by a built-in battery. However, processing speed becomes slower at low frequencies, so
Although high frequencies may be used to speed up processing, they have the disadvantage of increasing current consumption.

(Problems to be Solved by the Invention) As described above, the present invention eliminates the drawback that increasing the processing speed during offline operation results in a large amount of current consumption.

[Configuration of the Invention (Means for Solving Problems) The portable medium of the present invention has an input means and is operated by an internal power supply, and constantly generates a low-frequency clock. When the first clock generation means, the second clock generation means that generates a high frequency clock, and the human power means instruct the start of startup, the low frequency clock from the first clock generation means is used to control the control element. At the same time, the second clock generation means starts generating a clock, and when an input operation is performed by the input means, the operation of the control element is controlled by a high frequency signal generated by the second clock generation means. It consists of a control means for switching to a clock.

(Function) The present invention operates a control element using a low-frequency clock from the first clock generation means and a high-frequency clock from the second clock generation means when the input means instructs the start of activation. When oscillation is started and the input means performs the next input (・ψ operation), the high frequency clock generated by the second clock generation means is used to operate the control element. be.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

In FIG. 3, 10 is an IC card as a portable medium, which is a multifunctional card having various functions. For example, an online function that is used using a terminal described below, an offline function that allows the IC card 10 to operate independently,
and has a wait state that only counts the clock.

The offline functions mentioned above include a train mode that can be used as a calculator, a time display mode that displays the time according to the user's clock, a time change mode that changes the time of the user's clock, address, and name. ,
Electronic width mode for registering and reading phone numbers, etc., or using the IC card 10 with multiple credit cards,
It has a shopping mode where it can be used as a cash card.

On the surface of the upper 3Q IC card 10, there are contact parts (connection means) 11 arranged at positions that match the specifications of the card.
A keyboard section (display means) 12 consisting of 20 keys, a display section (display means) 13 disposed on the upper surface of the keyboard section 12 and formed of a liquid crystal display element, and magnetism generating members 14a and 14b are provided.

The contact portion 11 includes, for example, one terminal 11a.
~llf. The terminal 11a is for operating power supply voltage (+5V, Vcc), the terminal 11b is for grounding, the terminal 11c is for a clock signal, the terminal lid is for a reset signal, and the terminals 11e to llf are for data input/output.

The keyboard section 12 includes mode keys (Ml, M2, M3, M4) 12a for specifying processing modes.

Numeric keypad 12b1 Four arithmetic operation keys as function keys, that is, addition (+) key 1205 Subtraction and equals (
-) key 12h.

The mode key 12a is used to control the processing for the telephone mode (Ml), time display mode (M2), electronic passbook mode (M3), or shopping mode (M4) when offline, that is, when processing is performed only with the IC card 10. You get to choose. In the shopping mode, the user selects a process corresponding to the type of card, ie, various credit cards, cash card, etc., depending on the combination of the M4 key and the numeric keypad 12b.

"-The addition key 12C is the NEXT key, that is, the display section 13.
The subtraction key 12d is used as a BACK key, that is, a key that returns the display state of the display section 13 to the previous one, the multiplication key 12f is used as a start key, and the decimal point key 12g is NO
The equal key 12 is used as the end key, and is used as the end key.
h is used as a YES key and a power-on key.

The display section 13 is a 16-digit dot matrix with each digit being 5×7.

The magnetism generating members 14a and 14b are embedded inside the IC card 10 in alignment with the track positions of a magnetic card reader (magnetic head) on the reading side (not shown).

FIG. 4 shows an IC card reading/writing unit 1 used in a terminal such as a personal computer that handles an IC card 10.
This shows the appearance of No. 6. In other words, card insertion slot 1
By connecting with the contact part 11 of the IC card 10 inserted from 7, data in the memory of the IC card 10 can be read or data can be written into the memory.

The IC card reading/writing section 16 is connected to the main body of a personal computer (not shown) by a cable.

Further, the electric circuit of the IC card 10 is constructed as shown in FIG. That is, the contact portion 1
1. Communication control circuit 21, reset control circuit 22, power supply control circuit 23, for example, a 3-volt internal battery (built-in power supply) 25, and a battery check circuit that checks whether the voltage value of this internal battery 25 is above a specified value. 24,
A clock control circuit 26, an oscillator 27 which is a crystal oscillator for arithmetic clock oscillation and outputs a signal at the oscillation frequency (high frequency) of the IMH2, a CPU (central processing unit) 28 for control, and a control program is recorded therein. 2 program ROMs, a program working memory 30, a data memory 31 which stores a password (for example, 4 digits), data, etc. and is composed of FROM, a timer 32 used for timing during processing operations, a calendar circuit 33, An oscillator (first clock generation means) 34, which is a crystal oscillator for basic clock oscillation and always outputs a signal with an oscillation frequency of 32.768 KH2 (low frequency and high precision), a display control circuit 35, A display unit driver 36 that drives the display unit 13, and a keyboard interface 38 that serves as a key input circuit for the keyboard unit 12.
, and a magnetism generating member control circuit 40 that controls the magnetism generating members 14a and 14b.

The communication control circuit 21, CPU 28, ROM2O, program working memory 30, data memory 31, timer 32, calendar circuit 33, display control circuit 35, keyboard interface 38, and magnetism generation for controlling the magnetism generation members 14a and 14b. Component control circuit 40
are connected by a data bus 20.

When the communication control circuit 21 receives data, that is, the terminal 16
The serial input/output signals supplied from the contact section 11 are converted into parallel data and sent to the data bus 2.
0, and during transmission, that is, parallel data supplied from the data bus 20 is converted into a serial input/output signal and output to the terminal 16 via the contact section 11. In this case, the format contents of the conversion are determined by the terminal device 16 and the IC card 10.

When the reset control circuit 22 goes online, it generates a reset signal and starts the CPU 28.

When the power supply control circuit 23 goes online, it switches from being driven by the internal battery 25 to being driven by an external power supply after a predetermined period of time has elapsed, and when it goes offline, that is, when the external voltage drops, it switches from being driven by the external power source to being driven by the external power source. This is to switch to driving by the battery 25.

In the offline mode in which the card is operated by the internal battery 25, the clock control circuit 26 generates a signal at the oscillation frequency (high frequency) of the IMH 2, which will be described later, during standby, that is, when the key is not pressed manually for a certain period of time. an oscillation circuit (second clock generation means) 6 that outputs
7 and also stops supplying the clock to the CPU 28, thereby standing by in a completely stopped state. The clock control circuit 26 also controls the oscillation circuit 6 from the stopped state.
When restarting 7, that is, power on key (equal key)
12h is turned on (after the start of the offline function is instructed) and until the next key input is performed, the watch clock is output as the clock for the CPU 28, and the next key input (for example, the mode specification using the mode key) is output. When this occurs, the output is switched to the high frequency clock, that is, the IMH2 clock.

The data memory 31 records information corresponding to a plurality of contracted credit cards (companies) and information corresponding to a cash card. The information is read out in accordance with the type of card selected using the numeric keypad 12b according to the numerical keys displayed on the display section 13 and the abbreviations such as credit company names and bank names.

The above information is the same as the information recorded on the conventional magnetic stripe for each card.

For example, first track data corresponding to the first track of the card and second track data corresponding to the second track are stored.

The calendar circuit 33 has a display clock that can be freely set and changed by the card holder, and a transaction clock that sets, for example, world standard time when the card is issued and cannot be changed thereafter. ing.

The display unit control circuit 35 converts the display data supplied from the CPU 28 into a character pattern using a character generator (not shown) configured with an internal ROM, and converts the display data supplied from the CPU 28 into a character pattern on the display unit 13 using a display unit driver 36. It is to be displayed.

The upper keyboard interface 38 converts the keys inputted on the keyboard section 12 into human key signals corresponding to the keys, and outputs the signals to the CPU 28.

When a shopping mode and a card type are specified, the magnetism generating member control circuit 40 controls the data and reading device supplied from the data memory 31 via the data bus 20 in accordance with the card type. By controlling the drive of the magnetism generating members 14a and 14b according to the drive rate corresponding to manual reading or automatic conveyance reading, and outputting first track data and second track data as magnetic information. , which is in the same state as a conventional magnetic stripe.

For example, in the case of manual reading, a drive rate with a fast reading speed is selected, and in the case of automatic conveyance reading, a drive rate with a slow reading speed is selected.

The magnetism generating member control circuit 40 controls the magnetism generating member 14 corresponding to the track designated by the operator in accordance with the type of card when the shopping mode is designated.
Magnetic information (first track data or second track data) is generated from either a1 or 14b.

For example, the "1" key and the division key 1 in the numeric keypad 12b
2e manually specifies the first track, selects generation of magnetism for the first track by the magnetism generating member 14a, and presses the "2" key in the numeric keypad 12b and the division key 12.
By inputting "e", the second track is designated, and the generation of magnetism for the second track by the magnetism generating member 14b is selected.

The power supply control circuit 23 will be explained in detail using FIG. 5. That is, inverter circuit 51154.55
, a counter 52, a D-type flip-flop circuit (FF circuit) 53, and a semiconductor switch 56 composed of a MOSFET.
．． 58, a diode 57, and an internal battery 25.

- The count value of the F counter 52 is a value that is not affected by chattering of the external power supply. Diode 5 above
7 is for protecting the power supply voltage Vout, and even if the power supply voltage Vcc drops below the memory drive voltage before the semiconductor switch 56 is turned on when the power supply voltage Vcc from the outside decreases, the power supply voltage Vout will drop. It is protected by an internal battery 25 to prevent this from happening.

The operation of this configuration will be described with reference to the timing chart shown in FIG. That is, when the IC card 10 is not connected to the terminal device 16 through the contact section 11, the semiconductor switch 56 is turned on.
The power supply voltage of the internal battery 25 is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

Further, when the IC card 10 is connected to the terminal device 16 through the contact section 11, an external power supply voltage Vcc is supplied to the gate of the semiconductor switch 58, and a clock signal CLK is supplied to the counter 52 via the inverter circuit 51. is supplied to the clock terminal ck of. As a result, the counter 52 starts counting, and when the value of the counter 52 reaches a predetermined value, the FF circuit 5
Set 3. By the set output Q of the second OFF circuit 53, a "0" signal is supplied to the gate of the semiconductor switch 58, a "1" signal is supplied to the gate of the semiconductor switch 56, the semiconductor switch 58 is turned on, and the semiconductor switch 56 is turned on.
turns off.

Therefore, the external power supply voltage Vcc is applied to each part via the semiconductor switch 58 as the output Vout of the power supply control circuit 22.

Note that when returning from the online state to the offline state, a reset signal is output from the reset control circuit 22 when the external power supply voltage Vcc decreases. This results in
The reset signal causes the counter 52, FF1lil
D path 53 is reset. Then, the semiconductor switch 5
A “1” signal is supplied to the gate of semiconductor switch 5.
A 0" signal is supplied to the gate of semiconductor switch 58.
is turned off, and the semiconductor switch 56 is turned on. Therefore, the power supply voltage of the internal battery 25 is applied to each part via the semiconductor switch 56 as the output Vout of the power supply control circuit 22.

The clock control circuit 26 will be explained in detail using FIG. 7. That is, the stop signal HALT from the CPU 28 is supplied to the clock input terminal ck of the FF circuit 62. The set output of this FF circuit 62 is
The machine cycle signal M1 from the CPU 28 is supplied to the clock input terminal ck of this FF circuit 63. The FF circuits 62 and 63 are used for stop mode timing. Above FF circuit 6
The set output of 3 is supplied to the data input end of the FF circuit 64, and the 32.763KH2 clock from the calendar circuit 33 is supplied to the clock input end ck of this FF circuit 64. The reset output of the FF circuit 64 is supplied to the data input end of the FF circuit 65, and the 32.763 KH2 clock clock from the calendar circuit 33 is supplied to the clock gck of the second OFF circuit 65. Ru. The FF circuit 65 is used to stop clock oscillation. The set output of the FF circuit 65 is:
is supplied to one end of the NAND circuit 66, and this NAND circuit 66
An oscillation circuit 67 is connected between the output end and the other end.

Further, the key human interrupt signal from the CPU 28 and the reset signal from the reset control circuit 22 are supplied to the reset input terminals R of the FF circuits 62, 63, and 64 via the OR circuit 61, and circuit 6
It is supplied to the set input terminal S of No. 5.

The oscillation circuit 67 includes an oscillator 27 having an oscillation frequency of IMHZ, a resistor 68, and a capacitor 70.71.

"-The output of the NAND circuit 66 is supplied to the clock input terminal ck of the FF circuit 74 via the inverter circuit 72,
Also, the NAND circuit 75 is connected to the inverter circuit 72, 73.
supplied to one end of the

Further, the reset signal from the reset control circuit 22 is supplied to the set input terminal S of the FF circuit 76, and the clock ick of this FF circuit 76 is supplied to an OR circuit 84, which will be described later.
output is supplied.

Further, a clock selection signal from the bipedal CPU 28 is supplied to the data input terminal D1 and the reset input terminal R of the FF circuit 76. The set output of the FF circuit 76 is F
It is supplied to the data input terminal of the F circuit 77, and the clock input terminal ck of this FF circuit 77 is supplied with a clock of 32.763 KH2 from the calendar circuit 33.

The set output of the FF circuit 77 is supplied to one end of a NAND circuit 79, and the clock of 32.763KH2 from the calendar circuit 33 is supplied to the other end of the NAND circuit 79 via an inverter circuit 78. . The output of the NAND circuit 79 is supplied to one end of a NAND circuit 80.

Further, the reset output of the FF circuit 77 is supplied to the data input end of the FF circuit 74, and the set output of this FF circuit 74 is supplied to the other end of the NAND circuit 75. The FF circuit 74 is used for clock switching.

'' The outputs of the two-legged NAND circuits 75 and 79 are supplied to the NAND circuit 80, and the output of this NAND circuit 80 is fed to the FF circuits 81.
83 clock input terminal ck, and the FF circuit 8
The set output of the FF circuit 63 is supplied to the data input terminal of No. 1 via the inverter circuit 82.

The set output of the FF circuit 81 and the FF circuit 8
The reset output No. 3 is outputted to the clock input terminal ck of the FF circuit 76 via the OR circuit 84.

Further, the set output of the FF circuit 83 is provided by a NAND circuit 86.
The output of the AND circuit 80 is supplied to the other end of the NAND circuit 86 via an inverter circuit 85. The output of the NAND circuit 86 is output to the CPU 28 as a clock signal.

The operation of such a configuration will be described with reference to the flowchart shown in FIG. First, the stopped state will be explained. That is, "1" is supplied from the CPU 28 as the clock selection signal. This allows FF
Circuits 76 and 77 are set. As a result, the watch clock (32,768KH2) is connected to the inverter circuit 78.
, FF circuit 81.82 via NAND circuit 79.80
, and an inverter circuit 85.

Next, restarting from a stopped state will be explained.

In other words, equal key 1 as the power-on key described in
2h, a key human interrupt signal is supplied from the CPU 28. Then, FF circuit 62, 63, 64
is reset, and the FF circuit 65 is set. The set output of the FF circuit 65 enables the oscillation circuit 67. As a result, the oscillation circuit 67 starts oscillating.

Furthermore, by resetting the FF circuit 63, the FF circuit 8
“1” is supplied to the data input end of “1”. As a result, the output of the NAND circuit 80 causes the FF circuit 8 to
1.83 is set and opens the gate of NAND circuit 86.

Therefore, the clock from the inverter circuit 85 is output to the CPU 28 via the NAND circuit 86.

Next, the CPU 28 outputs a key manual interrupt signal, and then, in response to input of the mode key as the next key manual input,
“0” is supplied to the data input end of the FF circuit 76 as a clock selection signal. As a result, the FF circuit 76.77
is reset, and the reset output of the FF circuit 77, that is, “1
“A signal is supplied to the data input end of the FF circuit 74.

At this time, 500 to 600 m5 e c or more elapses while the next mode key is pressed manually, and the oscillation circuit 67 stably oscillates.

Also, at this time, the clock (IMH2
) is supplied to the clock input terminal of the FF circuit 74 via the inverter circuit 72.

Therefore, the FF circuit 74 is set, and the set output opens the gate of the NAND circuit 75.

As a result, the clock (IMH2) generated by the oscillation circuit 67 is generated by the inverter circuit 72.73, the NAND circuit 75.80,
The signal is sequentially output to the CPU 28 via an inverter circuit 85 and a NAND circuit 86.

Thereby, by setting the clock selection signal to "0", synchronization is achieved in the FF circuit 74, and the clock is switched from the clock for high-speed processing to the clock for high-speed processing.

Next, a case will be described in which the processing is ended and the system is placed in a stopped state (standby state). That is, when the key human power standby state in the offline state has elapsed for a predetermined period of time, the CPU 28 sets the clock selection signal to "1" so that the FF circuits 76 and 77 are set, and the set output of the FF circuit 77, that is, "1". The signal is supplied to a NAND circuit 79,
The gate of NAND circuit 79 is open. Therefore, the clock for the watch consists of the inverter circuit 78 and the NAND circuit 79.
．． 80, an inverter circuit 85, and a NAND circuit 86.

As a result, the watch clock is output to the CPU 28 again.

Next, a stop signal is supplied from the CPU 28 to the data input end of the FF circuit 62. Then, the FF circuit 62 is set, and the set output is supplied to the data input end of the FF circuit 63. Then, the FF circuit 63 is set by the machine cycle signal M1 from the CPU 28, and a "0" signal is supplied to the data input terminal of the FF circuit 81. As a result, the set output of the FF circuit 63 is changed to the set output of the FF circuit 81.8.
After sending two pulses in step 3, the gate of the NAND circuit 86 is closed to stop outputting the clock to the CPU 28. As a result, the CPU 28 is brought to a halted state.

Further, the set output of the FF circuit 63 is the FF circuit 64.
After sending two pulses at step 65, the gate of the NAND circuit 66 is closed to stop the oscillation by the oscillation circuit 67.

As a result, after stopping the output of the clock to the CPU 28, the oscillation circuit 67 is stopped.

In this way, the clock control circuit 26 operates as an oscillator 27.
In order to cover the rising edge of crystal oscillation caused by this, the clock for the watch and the clock for IMH2 are effectively switched.

- The calendar circuit 33 will be explained in detail with reference to FIG. That is, oscillator 3 of 32.768KH2
By frequency dividing the oscillation output of 4, a frequency dividing circuit 91 outputs a signal every second from output terminals a and b, and by counting the signal from output terminal a of this frequency dividing circuit 91, 10
A counter 92 that outputs a signal every second, this counter 9
A counter 93 that outputs a signal every 60 seconds, that is, every minute by counting the signals from 2;
A counter 94 that outputs a signal every 10 minutes by counting the signal from this counter 94, a counter 95 that outputs a signal every 60 minutes, that is, every hour, by counting the signal from this counter 94; A counter 96 outputs a signal every 24 hours, that is, every day, by counting the signals from the frequency dividing circuit 91, and a counter 97 outputs a signal every 10 seconds by counting the signals from the output terminal of the frequency dividing circuit 91. , a counter 98 that outputs a signal every 60 seconds, that is, one minute, by counting the signal from this counter 97, a counter 99, which outputs a signal every 10 minutes by counting the signal from this counter 98, A counter 100 outputs a signal every 60 minutes, that is, every hour, by counting the signal from the counter 99. A counter 101 outputs a signal every 24 hours, that is, every 10, by counting the signal from this counter 100. It consists of

Here, the counters 92 to 96 constitute a transaction clock that counts seconds, minutes, and hours, and the counters 97 to 1 constitute a clock for counting seconds, minutes, and hours.
01 constitutes a display clock that counts seconds, minutes, and hours. The contents of the counters 97 to 101, that is, the counted values, can be changed using the keyboard section 12, while the contents of the counters 92 to 96, that is, the counted values cannot be changed using the keyboard section 12.

In addition, the year, month, day, and day of the week are displayed on the counter 9 every 24 hours.
6. An interrupt request is output to the CPU 28 by the signal from 101. Thereby, the CPU 28 uses the data memory 31 to update the year/month/day and day of the week of the corresponding area. Furthermore, as shown in FIG. 9, the two clocks are shifted in the 1-second clock digit 111, which is the basis, so that interrupts do not occur at the same time.

The magnetism generating member control circuit 40 will be explained in detail using FIG. 10. That is, command data supplied from the CPU 28 via the data bus 20 is supplied to the command OFF circuit 110. This FF circuit 1
10 consists of four FF circuits, and depending on the command data supplied from the data bus 20, a clock selection signal corresponding to the drive rate for the first track is output from the output terminal 110a, a start signal is output from the output terminal 110b, or the output rJ 110 A clock selection signal corresponding to the drive rate for the second track is output from c, and a start signal is output from output terminal 110d.

1- A command write start signal from the CPU 28 is supplied to the clock input terminal cp of the FF circuit 110. The clock selection signal corresponding to the drive rate indicates whether the type of reader is a manual type reader or an automatic conveyance type reader.

The clock selection signal output from the output terminal 110a of the FF circuit 110 is supplied to the input terminal S of the selection circuit 111. A signal with a frequency of 8KH2 is supplied from an oscillator (not shown) to the input terminal A of this selection circuit 111, and the input terminal B
A signal with a frequency of 4KH2 is supplied from an oscillator (not shown).

In response to the clock selection signal from the FF circuit 110, the selection circuit 111 selects the signal at the input terminal A when the type of reader is manual reading, and outputs it from the output terminal Y.
If the type of reader is an automatic conveyance type reader, the signal at the input end B is selected and output from the output end Y.

The start signal output from the output end 110b of the F circuit 110 and the output of the selection circuit 111 are supplied to a timing circuit 112.

This timing circuit 112 generates a hexadecimal clock,
Clock input terminal C of parallel/serial conversion circuit 115
The first clock d1 is supplied to the load input terminal of the parallel/serial conversion circuit 115 as a load signal. Further, the timing circuit 112 has data “0”.
Select circuit 11 for selecting clock for data “1” and clock for data “1”
6.

Further, first track data as magnetic data supplied from the CPU 28 via the data bus 20 (varies depending on the type of card selected) is supplied to the data latch circuit 113.
A data write start signal is supplied from the CPU 28.

The data latch circuit 113 operates on the data bus 2 when a data write start signal is supplied from the CPU 28.
It latches magnetic data of 7 bits supplied from 0 onwards.

The data latched in the data latch circuit 113 is 7
It is supplied to the data input terminal IN of the parallel/serial conversion circuit 115 for bits. The parallel/serial conversion circuit 115 loads the data from the data latch circuit 113 in response to the supplied load signal, shifts the loaded data in order, and converts the data into 1-bit signals (
The signal is converted into a "1" signal or a "0" signal and output.

The output of the parallel/serial conversion circuit 115 is supplied to the input terminal S of the selection circuit 116. This selection circuit 11
6 selects and outputs the data "1" clock supplied from the timing circuit 112 when a "1" signal is supplied to the input terminal S, and when a 0" signal is supplied to the input terminal S. , the clock for data "0" supplied from the timing circuit 112 is selected and output.The output of the selection circuit 116 is output from the J-KFF circuit 11.
The set output and reset output of this J-KFF circuit 117 are supplied to a driver 118.

This driver 118 generates a magnetic field by driving the magnetism generating member 14a in response to a signal from the FF circuit 117. For example, when the FF circuit 117 is set, it generates a magnetic field as shown by arrow C, and when it is reset, it generates a magnetic field as shown by arrow d.

Incidentally, a timing chart of the main parts of the magnetism generating member control circuit 40 is as shown in FIG.

In the selection circuit 116, as shown in FIG.
The clock cycle ratio for data "1" and "0" is 1:2. J-K with this clock
By operating the FF circuit 117 in the inversion mode, "1", 0" signals in the format required as magnetic data (data for the first track) are obtained, and the magnetic generation member 14
I) to drive a.

Further, the data write start signal from the CPU 28 is inverted and supplied to the set input terminal of the FF circuit 114 for empty detection, and the reset input terminal of this FF circuit 114 receives the first signal from the timing circuit 112. The clock is inverted and supplied. This results in
When the data of the data latch circuit 113 is loaded into the data latch circuit 115, the FF circuit 114 is set, and the set output of the FF circuit 114, that is, the buffer empty signal is supplied to the CPU 28.

As a result, the CPU 28 determines that the next data can be set, and outputs the next data to the data latch circuit 113. In this way, the CPU 28 sets data in order while sensing the output of the empty detection FF circuit 114, and after outputting all the data, turns off the command write start signal and data write start signal. There is. As a result, the timing circuit 11
2 stops generating the signal, and the operation ends.

Note that each of the circuits 111 to 118 described above is a circuit for the first track, and the circuit for the second track also includes a selection circuit 119, a timing circuit 120, and a data latch circuit 1.
21, empty detection FF circuit 122, parallel/serial conversion circuit 123, selection circuit 124, J-KFF circuit 125
, and a driver 126. However, the location where the timing circuit 120 operates in quinary is different.

As described above, the magnetism generating member control circuit 40 generates a magnetic field on the reader side by generating a magnetic field in accordance with the magnetic data of a predetermined credit card or cash card selectively read out from the data memory 31. A head (not shown) is provided with the same signals as when reading a conventional magnetic stripe. For example, the magnetism generating member 14 corresponds to the first track of the card.
Data for the first track is outputted by a, and data for the second track is outputted by the magnetism generating member 14b corresponding to the second track.

Next, the operation in such a configuration will be explained.

First, we will explain the offline function used by the card alone. That is, when the electronic mode is designated by the mode key 12a, that is, the M1 key, it can be used as a calculator using the numeric keypad 1.2b and the four arithmetic operation keys 12c.

Also, by pressing the mode key 12a, that is, the M2 key,
When the time display mode is specified, the CPU 28 reads the seconds, minutes, and hours for the display clock from the counters 97 to 101 in the calendar circuit 33, and also reads the seconds, minutes, and hours from the counters 97 to 101 in the calendar circuit 33, and
The year, month, day, and day of the week for the display clock are read from , converted into a specified format, and output to the display control circuit 35 . As a result, the display unit control circuit 35 uses an internal character generator (not shown) to convert the character pattern into a character pattern, and uses the display unit driver 36 to convert the display unit 1 into a character pattern.
Display in 3.

Further, when the electronic width mode is specified by the mode key 1'2a, that is, the M3 key, the CPU 28
Read out the address, name, phone number, etc. stored in 1.
It is displayed on the display section 13. Further, when registering the above-mentioned address, name, etc. in the electronic width, for example, the mode key 12a and the numeric keypad 12b are used. That is, rAJ is rMl,2'', rBJ is rM2.2'', rCJ is rFv
1B, 2'', rDJ is 1li41.3'', and can be specified by inputting .

When the shopping mode is specified using the mode key 12a, that is, the M4 key, the type of contracted credit card or cash card is selected using the numeric keypad 12b, and the type of reader (external device), that is, whether the reading is manual or not, is selected using the numeric keypad 12b. Select automatic transport type, and select whether to output data for the first truck or data for the second trunk.

For example, the number keys displayed on the display section 13 and the abbreviations such as credit company names, bank names, etc.
Use b to select the type of contract credit card or cash card. In addition, in response to the message "Is the reader reading manual?" displayed on the display unit 13, if it is manual reading, press the YES key (equal key 12h').
), select it by inputting the NE
By pressing the XT key (addition key 120), the display section 13
In response to the message "Is the reading automatic transfer type" displayed on the screen, press the YES key (equal key 12h) to select it. Furthermore, "1" in the numeric keypad 12b
Specify the first track manually using the key and the division key 12e, and press the "2" key in the numeric keypad 12b and the division key 128.
By specifying the second track by inputting , it is possible to select whether to output data for the first track or data for the second track.

With the above selection, the CPU 28 selects the first data from the data memory 31 as data (72 characters) corresponding to the selected credit card or cash card.
The track data and the second track data are read and output to the magnetism generating member control circuit 40. Also, CPU28
outputs a drive rate corresponding to the selection of manual type or automatic conveyance type to the magnetism generating member control circuit 40. moreover,
The CPU 28 outputs command data, a command write start signal, and a data write start signal to the magnetism generating member control circuit 40.

Next, when the start key (multiplication key 12f) is turned on, the CPU 28 outputs a start signal to the magnetism generating member control circuit 40. As a result, when the output of the data for the first track is selected, the magnetism generating member control circuit 40 generates a magnetic field corresponding to the data for the first track of the credit from the magnetism generating member 14a, thereby controlling the reader. A side magnetic head (not shown) is provided with the same signal as when reading the conventional first track magnetic stripe. In this case, when the manual type is selected as the drive rate, the 8KH2 signal is selected as the drive clock in the magnetism generating member control circuit 40, and in accordance with this signal, magnetic data with a high generation speed is transmitted to the magnetism generating member 14a. generated from. Further, when the automatic conveyance type is selected as the drive rate, the 4KH2 signal is selected as the drive clock in the magnetic generation member control circuit 40, and in accordance with this signal, magnetic data with a slow generation speed is transferred to the magnetic generation member 14a. generated from.

Further, when the output of the data for the second track is selected, the magnetism generating member control circuit 40 applies a magnetic field to the magnetism generating member 14b according to the data for the second track of the credit.
The magnetic head (not shown) on the reader side is supplied with the same signal as when reading the conventional magnetic stripe of the second track. In this case, when the manual type is selected as the drive rate, the 4KH2 signal is selected as the drive clock in the magnetism generating member control circuit 40, and in accordance with this signal, the magnetic data that is generated at a high speed is transmitted to the magnetism generating member 14b. generated from. Also,
When the automatic conveyance type is selected as the drive rate, the drive clock in the magnetism generating member control circuit 40 is set to 2.
The KH2 signal is selected, and in response to this signal, magnetic data with a slow generation speed is generated from the magnetic generation member 14b.

As a result, in shopping mode, it can be used as a conventional credit card.

The designation of the track is maintained until the end key (decimal point key 12g) instructing the end of the transaction in the mode is pressed or the other track is designated.

In addition, the output of the above magnetic data normally ends once, but if the start key (multiplication key 12f) continues to be pressed, the data is output continuously, that is, the data for each trunk is repeatedly output. .

In this case, there is no change to the specified track.

Next, the online function used by inserting the IC card 10 into the terminal 16 will be explained. That is,
Insert the IC card 10 into the insertion slot 17 of the terminal 16.

Then, the IC card 10 is accepted, and the connection section inside the terminal 16 and the contact section 11 of the IC card 10 are connected. Accordingly, when an external power supply voltage is supplied via the contact portion 11, the power supply control circuit 23 switches from driving by the internal battery 25 to driving by the external power supply voltage, as described above. Further, the recess/node control circuit 22 generates a reset signal to start up the CPU 28.

After this activation, if the CPU 28 confirms that it is operating online, it performs online processing according to the contents of the program ROM 29. This online processing involves exchanging data by updating data between the terminal 16 and the IC card 10, and
New data is written into the card 10.

As mentioned above, in order to reduce the current consumption of the card, the internal oscillation circuit is used in on/off operation, and it also prevents the waiting time and key input due to the rise time of the oscillation circuit from being overlooked. It is highly reliable and can extend the lifespan of the card.

In addition, when the CPU is offline and in the HALT state, high-frequency oscillation is started by pressing the power-on key, and the CPU clock is switched from low frequency to high frequency by manually pressing the next key. The oscillation stabilizes in the time between the on-key input and the next key input.

Furthermore, in normal mode, where faster processing speed is better as the CPU clock, a high frequency is used to clock the CPU in the waiting state.
When the U is in the halt state (HALT), the clock is not supplied to the CPU, and high-frequency oscillation during CPU operation is stopped by quitting the CPU or by pressing a specific key.
Since U is placed in the HALT state, current consumption is small and processing speed can be increased.

In the above embodiment, an IC card is used, but the IC card is not limited to this, as long as it has a data memory and a control element, and selectively performs input/output from the outside, and the shape is not card-like. , or other shapes such as a rod shape.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a portable medium that can perform processing with high processing speed and low current consumption during offline operation.

[Brief explanation of the drawing]

Since the drawings are for explaining one embodiment of the present invention, FIG. 1 is a flowchart for explaining the off-line operation, FIG. 2 is a diagram showing a schematic configuration of an electric circuit of an IC card, and FIG. 3 is a diagram showing a schematic configuration of an IC card. Plan view showing the configuration of the card, No. 4
Figure 5 shows a terminal that handles IC cards, Figure 5 shows an example of the configuration of a power supply control circuit, Figure 6 is a timing chart for explaining the operation of the main parts in Figure 5, and Figure 7 shows an example of the configuration of a power supply control circuit. A diagram showing the configuration of the clock control circuit, FIG. 8 is a schematic block diagram of the calendar circuit, FIG. 9 is a diagram showing the output timing of signals from the frequency dividing circuit, and FIG. 10 is a configuration example of the magnetic generation member control circuit. 11 and 12 are timing charts for explaining the operation of the main parts in FIG. 10. 10... IC card (portable medium), 11... Contact section, 12... Keyboard section, 12a... Mode key, 12b... Numeric keypad, 12c... Addition key (NEXT key), 12d--Subtraction key, 12e
-Division key, 12f... Multiplication key (start key), 1
2 g... Decimal point key (NO key, end key), 12
h...Equal key (YES key), 13 middle display,
14a, 14b... Magnetism generating member, 16... Terminal, 23... Power supply control circuit, 25... Internal battery,
28... CPU (control element), 31... data memory (storage means), 40... magnetism generating member 1i control circuit (driving means). Applicant's agent Patent attorney Suzue Nana Figure 3 Figure 4

Claims (4)

[Claims] (1) In a portable medium that has an input means and a control element and is operated by an internal power supply, a first clock generating means constantly generates a low frequency clock, and a first clock generating means generates a high frequency clock. a second clock generating means; when the input means instructs to start the activation, the control element is operated using the low frequency clock from the first clock generating means, and the second clock generating means operates the control element; and control means for switching the operation of the control element to the high-frequency clock generated from the second clock generation means when the next input operation is performed by the input means. Features a portable medium. (2) The portable medium according to claim 1, wherein the control element is a CPU. (3) The portable medium according to claim 1, wherein the first clock generating means generates a clock for a watch. (4) The portable medium according to claim 1, wherein the instruction to start activation is an instruction to start an offline function.