JPH01101656A - Laminated integrated circuit - Google Patents

Abstract

PURPOSE:To reduce dimensions with a plurality of built-in capacitors and interconnections by integrally forming a multilayer interconnection ceramic substrate, in which a ceramic layer is interposed between internal conductors for interconnection, with a laminated capacitor network. CONSTITUTION:A laminated integrated circuits comprises ceramic green sheets 30A-30E and individual internal connectors 31A-31I to be printed onto the surfaces of the green sheets. In other words, a multilayer interconnection ceramic substrate is integrally formed with a laminated capacitor network where a plurality of capacitors are constructed with a ceramic layer interposed between the internal conductors 31A-31I for capacitors, with a ceramic layer interposed between the internal conductors 31A-31I for interconnection. According to the constitution, a multilayer interconnection substrate with a capacitor network base having a plurality of built-in capacitors and interconnections can be obtained, and such substrate contributes to reducing the outside dimensions while allowing to dispense with a capacitor mount.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a laminated integrated circuit incorporating a plurality of capacitors and multilayer wiring.

(Prior Art) Multilayer wiring ceramic substrates have been known for a long time, and there are three types of manufacturing methods: a green sheet printing method, a green sheet lamination method, and a thick film method.

The green sheet printing method is a ceramic green sheet (
Printing of a conductive paste such as Ag-Pd and dielectric paste such as alumina is repeated on an unfired sheet, and the sheet is then fired.

Further, in the green sheet lamination method, substrates created by the green sheet printing method are stacked and integrally fired.

The thick film method involves repeating the process of alternately printing conductor paste and dielectric paste on a fired ceramic substrate and firing them.

(Problem to be solved by the invention) By the way, the conventional multilayer wiring ceramic board does not have a built-in capacitor, so it is necessary to mount the capacitor on the board, which increases the board area. . Further, the capacitor network disclosed in Utility Model Application Publication No. 59-44031 does not have a multilayer wiring portion. However, recently, there has been a demand from consumers to add multilayer wiring to capacitor networks as well.

(Means for Solving the Problems) In view of the above points, the present invention incorporates a plurality of capacitors and multilayer wiring, and is capable of responding to the various demands of consumers and achieving miniaturization of external dimensions. The aim is to provide a laminated integrated circuit that can be obtained.

The present invention includes a multilayer wiring ceramic substrate in which a ceramic layer is interposed between inner conductors for wiring and a multilayer wiring ceramic substrate in which a ceramic layer is interposed between inner conductors for wiring is integrally formed with a multilayer capacitor network in which a plurality of capacitors are constructed by interposing a ceramic layer between western conductors for capacitors. This solves the above conventional problems.

(Function) In the 82-layer integrated circuit of the present invention, since the capacitor network and the multilayer wiring ceramic board are integrated, there is no need to mount the capacitor, which was required in the conventional multilayer wiring ceramic board, and the board size can be reduced. Miniaturization is possible. Furthermore, unlike a simple capacitor network, it has a multilayer wiring section, so it has the advantage of being able to meet the various demands of consumers. Furthermore, a laminated hybrid integrated circuit can be constructed by mounting a printed resistor or a pair of semiconductor chips (without an outer container) on the surface of the substrate.

(Example) Hereinafter, an example of a laminated integrated circuit according to the present invention will be described with reference to the drawings.

1 to 3 show a first embodiment of the present invention.

Figure f: 51 shows the lamination process and shows ceramic green sheets (30A to 30E) for constructing a laminated integrated circuit.
and valley inner conductor 31A to be printed on the green sheet surface
to 311 are shown. For example, if they are manufactured by a green sheet lamination method, a green sheet 30A printed with a conductive paste for the internal wiring conductor 31A and an internal wiring conductor 31B.

Green sheet 30B printed with 31C conductor paste
, a green sheet 30C printed with conductor paste for internal conductors 31D and 31E for capacitors, and internal conductors 31F, 31G, and 31H for capacitors.

Green sheet 30D printed with 311 conductor paste
However, printed green sheets) 30C and 30D are repeatedly stacked until the required capacitance is achieved), green sheets? OE and OE are superimposed (laminated) and fired together. As a result, the wiring internal conductors 31A and 31B are formed as shown in figure f53.

A ceramic layer as an insulating layer is interposed between the capacitor internal conductors 31D, 31E and 31F to 31C.
A capacitor network-based multilayer wiring board 32 is obtained in which a ceramic layer as a dielectric material is interposed between the layers. The external electrodes 1 to 12 are now 9 on the side surface of the multilayer substrate 32.
The printing of the 34-body paste is provided at predetermined intervals by et al.

External electrodes 1 to 12 formed on a multilayer substrate 32 in FIG.
The connection relationship between and internal capacitors and wiring is shown. Further, FIG. 3 is a sectional view taken along line III-iIII of FIG. 2.

According to the first embodiment, it is possible to obtain a capacitor network-based multilayer wiring board that incorporates a plurality of capacitors and multilayer wiring, and the external dimensions can be reduced by eliminating the need to mount the capacitors.

FIGS. 4 and 5 show a second embodiment of the present invention, in which fjS
FIG. 4 shows the connection relationships between the external electrodes 1 to 24 formed on the multilayer substrate 40, internal capacitors, wiring, and newly added resistors. Further, FIG. 5 is a sectional view taken along the line V--■ in FIG. 4. In this second embodiment, a printed resistor 41 and a surface conductor 42 are added to one side of a capacitor network-based multilayer wiring board 40 obtained in the same manner as in the first embodiment to construct a laminated hybrid integrated circuit. be. In this case, the printed resistor 41 is formed by printing and baking resistor paste, and the surface conductor 42
may be formed by printing and baking a conductive paste. Note that 31J is an internal conductor for a capacitor, and 31 is an internal conductor for wiring.

6 and 7 show a third embodiment of the invention.

In this case, in addition to the configuration of the second embodiment in which a printed resistor 41 and a surface conductor 42 are provided on one side of a capacitor network-based multilayer wiring board 40, a semiconductor pair chip 50 is mounted on the other side of the board 40. A surface conductor 51 is formed to constitute a laminated hybrid integrated circuit. Incidentally, in order to protect the paired chips 50, a protective cap 52 made of resin, alumina, etc. may be mounted on the substrate 40 as shown in FIG.

(Effects of the Invention) As explained above, according to the laminated integrated circuit of the present invention,
A multilayer wiring ceramic substrate with a ceramic layer interposed between wiring internal conductors is integrally formed with a multilayer capacitor network comprising a plurality of capacitors with ceramic layers interposed between capacitor internal conductors. It has built-in multiple capacitors and multilayer wiring, so it can meet the various demands of consumers, and it is also possible to reduce the external dimensions.

[Brief explanation of the drawing]

FIG. 1 is an exploded perspective view illustrating a first embodiment of a laminated integrated circuit according to the present invention, and FIG. 2 is a circuit diagram showing the connection relationship between the external electrode and the circuit inside the substrate in the first embodiment. 3 is a sectional view taken along line III-III in FIG. 2, FIG. 4 is a circuit diagram showing the connection relationship between the external electrode and the circuit inside the substrate in the second embodiment of the present invention, and FIG. ■−■ Cross section,
Figure 6 is a front sectional view showing a third embodiment of the present invention, and Figure 7 is a perspective view thereof. 1 to 24... External electrode, 30A to 30E... Green sheet, 31A to 311... Internal conductor, 32
．． 40...Multilayer board, 41...Printed resistor, 50...
・Semiconductor pair chip. Patent agent TDC Co., Ltd.

Claims (1)

[Claims] (1) A multilayer wiring ceramic substrate with a ceramic layer interposed between internal conductors for wiring is integrally formed with a multilayer capacitor network consisting of multiple capacitors with ceramic layers interposed between internal conductors for capacitors. Characteristics of stacked integrated circuits.