JPH10173307A - Circuit substrate - Google Patents
Circuit substrateInfo
- Publication number
- JPH10173307A JPH10173307A JP33231196A JP33231196A JPH10173307A JP H10173307 A JPH10173307 A JP H10173307A JP 33231196 A JP33231196 A JP 33231196A JP 33231196 A JP33231196 A JP 33231196A JP H10173307 A JPH10173307 A JP H10173307A
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- circuit
- circuit board
- upper conductive
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 16
- 238000010030 laminating Methods 0.000 claims abstract description 9
- 230000005540 biological transmission Effects 0.000 abstract description 2
- 239000003973 paint Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、抵抗とコンデンサ
を具備する回路基板に関する。[0001] The present invention relates to a circuit board provided with a resistor and a capacitor.
【０００２】[0002]
【従来の技術】今日、高性能でコンパクトな電気製品の
普及によって高密度実装が進み、ごく小さい基板により
多くの回路を集積する必要性が高まっている。殊にＣＲ
回路はその用途及び態様が極めて多彩であり、回路基板
上で搭載される頻度が極めて高い。2. Description of the Related Art Today, with the spread of high-performance and compact electric products, high-density mounting has progressed, and the need to integrate more circuits on a very small substrate has increased. Especially CR
Circuits are used in a wide variety of applications and modes, and are frequently mounted on circuit boards.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来
は、図４の如く各種素子を平面的に実装していたので、
各素子について電極や素子本体を形成する領域が個々に
必要となり、より一層の小形化を妨げる原因とされてい
た。However, conventionally, as shown in FIG. 4, various elements are mounted in a plane,
For each element, a region for forming an electrode and an element body is individually required, which has been a factor that hinders further miniaturization.
【０００４】本発明は、上記実情に鑑みてなされたもの
であって、少なくともフィルタ、発信回路、共振回路と
して定型化されているＣＲ回路の実装面積を縮小するこ
とによって実装密度をより高めることができる回路基板
の提供を目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is possible to further increase the mounting density by reducing the mounting area of at least a CR circuit that is standardized as a filter, a transmission circuit, and a resonance circuit. It is intended to provide a circuit board that can be used.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
に成された本発明による回路基板は、絶縁基板の表面
に、下位導電層、誘電体層、上位導電層の順で積層し、
前記上位導電層の上に抵抗体の一部を積層して成るＣＲ
回路部を設けたことを特徴とする。絶縁基板たる誘電体
層の上下面に、下位導電層及び上位導電層を形成し、下
位導電層又は上位導電層の少なくとも一方の上に抵抗体
の一部を積層して成るＣＲ回路部を設ける場合もあり、
それらの回路基板を、絶縁層を介して複数層に重合して
構成する場合もある。According to a first aspect of the present invention, there is provided a circuit board having a lower conductive layer, a dielectric layer, and an upper conductive layer stacked on a surface of an insulating substrate.
CR formed by laminating a part of a resistor on the upper conductive layer
A circuit portion is provided. On the upper and lower surfaces of a dielectric layer serving as an insulating substrate, a lower conductive layer and an upper conductive layer are formed, and a CR circuit portion formed by laminating a part of a resistor on at least one of the lower conductive layer or the upper conductive layer is provided. In some cases,
In some cases, these circuit boards are configured by being superimposed into a plurality of layers via an insulating layer.
【０００６】[0006]
【発明の実施の形態】以下、本発明による回路基板の実
施の形態を図面に基づき説明する。図１乃至図３は、本
発明による回路基板の第１の実施の形態を示したもので
ある。この回路基板は、エポキシ系樹脂やセラミック等
より成る絶縁基板１の表面に、回路パターン１４に繋が
り且つ銅泊或いは導電塗料を印刷焼成して成る下位導電
層２を形成し、その上へ誘電体層３、更にその上へ回路
パターン（図示せず）に繋がる導電塗料製の上位導電層
４を積層することによってコンデンサを形成すると共
に、更に前記上位導電層４の上に抵抗体５の一端部を積
層し、他端部を回路パターンに繋げて図３に示す回路に
相当するＣＲ回路部６を構成したものである。該ＣＲ回
路部６は、図３のａ，ｂ，ｃに相当する３つの端子が引
き出されており、各端子の接続の接続の仕方によって、
ローパスフィルタ又はハイパスフィルタのいずれの用途
にも利用できる。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a circuit board according to an embodiment of the present invention. 1 to 3 show a circuit board according to a first embodiment of the present invention. This circuit board has a lower conductive layer 2 formed on the surface of an insulating substrate 1 made of an epoxy resin, ceramics or the like, which is connected to the circuit pattern 14 and is printed and baked with a copper coating or a conductive paint. A capacitor is formed by laminating a layer 3 and an upper conductive layer 4 made of conductive paint connected to a circuit pattern (not shown) thereon, and further forming one end of a resistor 5 on the upper conductive layer 4. Are laminated and the other end is connected to a circuit pattern to form a CR circuit section 6 corresponding to the circuit shown in FIG. In the CR circuit section 6, three terminals corresponding to a, b, and c in FIG. 3 are drawn out, and depending on the connection method of each terminal.
It can be used for both low-pass and high-pass filters.
【０００７】図５は、本発明による回路基板の第２の実
施の形態を示したものである。この回路基板は、所定の
誘電率を持った硝子エポキシ系或いは紙フェノール等の
合成樹脂より成る誘電体層７を絶縁基板として具備し、
その上面に銅泊或いは導電塗料を印刷焼成して成る上位
導電層９を、下面に上位導電層９と同様の下位導電層８
をそれぞれ形成し、下位導電層８又は上位導電層９のい
ずれか一方の上に抵抗体１０の一端部を、抵抗塗料の印
刷焼成により積層することによって、前記図３に示す回
路に相当するＣＲ回路部１１を形成するものである。
尚、下位導電層８と上位導電層９それぞれについて抵抗
体の一端部を積層すれば図６に示すＣＲ回路が構成され
るが、抵抗体の中間部を積層すれば異なる回路構成とも
なる。FIG. 5 shows a circuit board according to a second embodiment of the present invention. This circuit board includes a dielectric layer 7 made of a synthetic resin such as glass epoxy or paper phenol having a predetermined dielectric constant as an insulating substrate.
An upper conductive layer 9 formed by printing and baking a copper coating or conductive paint is formed on the upper surface, and a lower conductive layer 8 similar to the upper conductive layer 9 is formed on the lower surface.
Are formed, and one end of the resistor 10 is laminated on one of the lower conductive layer 8 and the upper conductive layer 9 by printing and baking a resist paint, thereby forming a CR corresponding to the circuit shown in FIG. The circuit section 11 is formed.
Note that the CR circuit shown in FIG. 6 is formed by laminating one end of the resistor for each of the lower conductive layer 8 and the upper conductive layer 9, but a different circuit configuration is obtained by laminating an intermediate portion of the resistor.
【０００８】上記構成に基づき、例えば前記第１の実施
の形態に記載した回路基板を、絶縁基板の素材となる絶
縁層を介して複数層に重合することも可能である。この
構成は、前記第２の実施の形態でも可能であるし、第１
及び第２の実施の形態を織り混ぜて構成することも可能
である。この様に、両者を重ねたり繋いだりすることに
よって、電気回路を３次元的に構成でき、一枚のボード
における更なる高密度化が可能となる。Based on the above configuration, for example, the circuit board described in the first embodiment can be superimposed into a plurality of layers via an insulating layer serving as a material of the insulating substrate. This configuration is also possible in the second embodiment,
It is also possible to mix the second embodiment and the second embodiment. In this way, by overlapping or connecting the two, an electric circuit can be formed three-dimensionally, and a higher density can be achieved on one board.
【０００９】[0009]
【発明の効果】以上の如く本発明による回路基板を使用
すれば、定型化されたＣＲ回路の占有面積が縮小できる
ことで、より実装密度の高い回路基板の製造が可能とな
り、電子製品のコンパクト化に大きく寄与するものであ
る。As described above, when the circuit board according to the present invention is used, the area occupied by the standardized CR circuit can be reduced, so that a circuit board having a higher mounting density can be manufactured, and the size of electronic products can be reduced. It greatly contributes to
【図１】本発明による回路基板の一例を示す要部平面図
である。FIG. 1 is a plan view of a main part showing an example of a circuit board according to the present invention.
【図２】本発明による回路基板の一例を示す要部断面図
である。FIG. 2 is a sectional view of a main part showing an example of a circuit board according to the present invention.
【図３】本発明による回路基板の一例の回路図である。FIG. 3 is a circuit diagram of an example of a circuit board according to the present invention.
【図４】従来の回路基板の一例を示す要部断面図であ
る。FIG. 4 is a sectional view of a main part showing an example of a conventional circuit board.
【図５】本発明による回路基板の一例を示す要部断面図
である。FIG. 5 is a sectional view of a main part showing an example of a circuit board according to the present invention.
【図６】本発明による回路基板の一例の回路図である。FIG. 6 is a circuit diagram of an example of a circuit board according to the present invention.
１ 絶縁基板 ２，８ 下位導電層 ３，７ 誘電体 ４，９ 上位導電層 ５，１０ 抵抗体 ６，１１ ＣＲ回路部 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2,8 Lower conductive layer 3,7 Dielectric 4,9 Upper conductive layer 5,10 Resistor 6,11 CR circuit part
Claims (2)
（２）、誘電体層（３）、上位導電層（４）の順で積層
し、前記上位導電層（４）の上に抵抗体（５）の一部を
積層して成るＣＲ回路部（６）を設けた回路基板。1. A lower conductive layer (2), a dielectric layer (3), and an upper conductive layer (4) are laminated on a surface of an insulating substrate (1) in this order. A circuit board provided with a CR circuit section (6) formed by laminating a part of a resistor (5).
に、下位導電層（８）及び上位導電層（９）を形成し、
下位導電層（８）又は上位導電層（９）の少なくとも一
方の上に抵抗体（１０）の一部を積層して成るＣＲ回路
部（１１）を設けた回路基板。2. A lower conductive layer (8) and an upper conductive layer (9) are formed on upper and lower surfaces of a dielectric layer (7) as an insulating substrate,
A circuit board provided with a CR circuit portion (11) formed by laminating a part of a resistor (10) on at least one of a lower conductive layer (8) and an upper conductive layer (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33231196A JPH10173307A (en) | 1996-12-12 | 1996-12-12 | Circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33231196A JPH10173307A (en) | 1996-12-12 | 1996-12-12 | Circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10173307A true JPH10173307A (en) | 1998-06-26 |
Family
ID=18253552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33231196A Pending JPH10173307A (en) | 1996-12-12 | 1996-12-12 | Circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10173307A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006237446A (en) * | 2005-02-28 | 2006-09-07 | Toppan Printing Co Ltd | Multilayer wiring board and manufacturing method thereof |
-
1996
- 1996-12-12 JP JP33231196A patent/JPH10173307A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006237446A (en) * | 2005-02-28 | 2006-09-07 | Toppan Printing Co Ltd | Multilayer wiring board and manufacturing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20031211 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20050927 |
|
| A02 | Decision of refusal |
Effective date: 20060207 Free format text: JAPANESE INTERMEDIATE CODE: A02 |