JP7603914B2 - Semiconductor Device - Google Patents

Description

The present invention relates to a semiconductor device, and in particular to a semiconductor device that can increase the breakdown voltage of the outer periphery and its vicinity.

Trench-gate power MOSFETs are widely used as power semiconductor devices that perform switching operations of large currents. Patent Document 1 discloses a semiconductor device in which a field plate electrode is provided under the gate electrode in the gate trench of the MOSFET. This device can increase the impurity concentration in the drift region, thereby reducing the on-resistance. In addition, since a field electrode is provided under the gate electrode, the gate input charge Qg can be increased. Furthermore, a structure is disclosed in which a trench peripheral structure is provided in which a field electrode is provided in the trench in the peripheral region around the MOSFET.
The device disclosed in Patent Document 1 has a plurality of trenches 110 in a peripheral region 300, as shown in Fig. 1 of Patent Document 1. A field plate electrode 130 is provided inside the plurality of trenches 110. An auxiliary electrode 50 and a gate electrode 60 are provided inside the trench 100 provided in the active region 200.

Patent No. 6624370

However, in the device disclosed in Patent Document 1, the depletion layer in the P-type buried layer is difficult to expand, and there are cases where sufficient breakdown voltage cannot be ensured.

The present invention was made in consideration of the above circumstances, and its purpose is to provide a semiconductor device that can increase the breakdown voltage of the outer periphery and its vicinity.

In order to solve the above problem, a semiconductor device according to one or more embodiments includes a first semiconductor region of a first conductivity type including a first portion having a high impurity concentration and a second portion having a lower impurity concentration than the first portion and provided on the first portion, a second semiconductor region of a second conductivity type provided on an upper portion of the first semiconductor region, a third semiconductor region of the first conductivity type provided on an upper portion of the second semiconductor region, a first main electrode electrically connecting the first semiconductor region and the second semiconductor region, a plurality of first trenches formed in an active region to a depth below an interface between the first and second portions of the first semiconductor region and having the third semiconductor region on a side surface thereof, a second trench provided closest to the active region in a peripheral region outside the active region and to a depth below the interface between the first and second portions, and a third trench provided outside the second trench and to a depth below the interface between the first and second portions, the first insulating layer provided within the first trench, a second insulating layer provided within the second trench, a third insulating layer provided within the third trench, a first field plate provided within the first insulating layer of the first trench, a second field plate provided within the second insulating layer of the second trench, a third field plate provided within the third insulating layer of the third trench, a gate electrode provided within the first insulating layer above the first field plate, a second gate electrode provided within the second insulating layer above the second field plate, and a fourth semiconductor region of a second conductivity type provided in the mesa portion, wherein a second portion of the first semiconductor region is provided below the fourth semiconductor region.

The above configuration makes it possible to provide a semiconductor device that can increase the breakdown voltage of the outer periphery and its surroundings.

FIG. 1 is a cross-sectional view illustrating a portion of a semiconductor device according to one or more embodiments. FIG. 2 is a cross-sectional view illustrating a portion of a variation of a semiconductor device according to one or more embodiments.

One or more embodiments will be described in detail with reference to the drawings. In the following description of the drawings, the same or similar parts may be denoted by the same or similar reference numerals. The description of the drawings is schematic, and the relationship between thickness and dimensions, the ratio of thickness of each layer, etc. are merely examples and do not limit the technical idea of the invention. In addition, the relationship and ratio of dimensions may differ between the drawings. In the following embodiment, the first conductivity type is n-type and the second conductivity type is p-type as an example, but the conductivity types may be reversed and the first conductivity type may be p-type and the second conductivity type may be n-type. In the following description, when describing the positional relationship of the members, the terms "upper", "lower", "right side", "left side", etc. are used as necessary based on the orientation of the drawings to be referred to, but do not limit the technical idea of the invention. In addition, the terms "upper", "lower", "right side", "left side", etc. may be used even when the members are not in contact.

FIG. 1 is a cross-sectional view showing a part of a semiconductor device according to one or more embodiments. In this semiconductor device, a trench 101 is provided in an active region. Furthermore, in an outer peripheral region surrounding the active region, a trench 102 is provided in parallel with the trench 101, and a trench 103 is provided in parallel with the trench 102 outside the trench 102. The trenches 101, 102, and 103 may be made of the same material. In FIG. 1, three trenches 101 are arranged from the right side, one trench 102 is arranged on the left side of the trench 101, one trench 103 is arranged on the left side of the trench 102, and one trench 104 (described later) is arranged on the left side of the trench 103, but this is shown for convenience, and the number of each trench is not limited to that shown in FIG. 1.
The semiconductor device of the embodiment includes, in a plan view, an active region including some or all of the multiple trenches 101, and trenches 102 and 103 provided in parallel in a peripheral region surrounding the periphery of the active region. In addition, trench 103 is generally surrounded by a peripheral trench 104.

The semiconductor device shown in FIG. 1 has a drift region 113 provided on a drain region 116 electrically connected to a drain electrode 112. The drift region 113 has a first portion 113A of the drift region 113 having a lower impurity concentration than the drain region 116. Furthermore, a second portion 113B of the drift region 113 is provided on the first portion 113A and has a lower impurity concentration than the first portion 113A, and an interface 113C is provided between the first portion 113A and the second portion 113B.

A base region 114 is provided on the drift region 113. The bottoms of the trenches 101, 102, and 103 are provided below the interface 113C. An insulating layer 133 is filled inside these trenches. A field plate 135 and a gate electrode 137 spaced apart from the field plate 135 are provided inside the insulating layer 133 provided in the trenches 101 and 102. The field plate 135 is provided at the bottom of each trench 101 and 102, and the gate electrode 137 is provided at the top of each trench 101 and 102. The trench 101 penetrates the base region 114. A source region 115 is provided on the opening side of the trench 101. The source region 115 is not provided in the semiconductor region on the trench opening side between the trenches 101 and 102, but the base region 114 is provided, and the base region 114 is electrically connected to the source electrode 111.

A field plate 136 is provided inside the insulating layer 133 provided in the trench 103, but a gate electrode 137 is not provided in the upper part of the trench 103. In FIG. 1, the upper surface of the field plate 136 is depicted within a range from the upper surface of the field plate 135 to a certain height of the upper surface of the gate electrode 137, and the field plate 136 is provided so as to extend to the upper part as well as the lower part of the trench 103. However, the field plate 136 may be provided only in the lower part of the trench 103, similar to the field plate 135 of the trench 101, and in that case, the upper part of the trench 103 may be filled with the insulating layer 133 instead of the gate electrode 137.

A field plate 136 is provided inside the insulating layer 133 provided in the trench 104, but a gate electrode 137 is not provided in the upper part of the trench 104. In FIG. 1, the upper surface of the field plate 136 is described within a range from the upper surface of the field plate 135 to a certain height of the upper surface of the gate electrode 137, and the field plate 136 is provided so as to extend not only to the lower part but also to the upper part of the trench 103. However, the field plate 136 may be provided only in the lower part of the trench 103 like the field plate 135 of the trench 101, and in that case, the upper part of the trench 103 may be filled with the insulating layer 133 instead of the gate electrode 137. Although only one trench 104 is provided in the semiconductor device of FIG. 1, a plurality of trenches 104 and field plates 136 in the trench 104 may be provided.

The semiconductor region on the trench opening side between trench 102 and trench 103, and the semiconductor region on the trench opening side between trench 103 and trench 104 are provided with a breakdown voltage improvement region 120 having a lower impurity concentration than the base region 114. However, the breakdown voltage improvement region 120 between trench 102 and trench 103 and the breakdown voltage improvement region 120 between trench 103 and trench 104 do not have to be provided.

Here, the drift region 113 may be a first conductivity type semiconductor, the base region 114 may be a second conductivity type semiconductor, the source region 115 may be a first conductivity type semiconductor, the drain region 116 may be a first conductivity type semiconductor, and the breakdown voltage improvement region 120 may be a second conductivity type semiconductor. Note that the source region 115 is not provided between the trenches 102 and 103 and between the trenches 103 and 104.

In addition, it is desirable that the interface 113C between the first portion 113A and the second portion 113B of the drift region 113 is within the height range where the field plate 136 is provided. This makes it possible to provide a semiconductor device with low on-resistance and high breakdown voltage.

An interlayer insulating film 117 is provided on a portion of the drift region 113 where the base region 114 is not provided, on the field plate 136 in the trench 103, the gate electrode 137, and on the upper portion of the base region 114. A source electrode 111 is provided on the upper portion of the interlayer insulating film 117. Here, the source electrode 111 is electrically connected to the source region 115, the base region 114, and the field plate 135. The field plate 136 may be electrically connected to the source electrode 111, or may be at a floating potential. A protective film 119 is provided on the upper portion of the source electrode 111.

Here, a buried layer 118 is provided in the semiconductor region (mesa region 121) between trenches 102 and 103 to which source electrode 111 is not electrically connected. A buried layer 118 is also provided on the end of trench 104 of the semiconductor device (the side opposite trench 101 as viewed from trench 104; left side in FIG. 1). Buried layer 118 is at a floating potential and may be a second conductivity type semiconductor.

Second portion 113B of drift region 113 is provided below buried layer 118 in mesa region 121. This makes it easier for the depletion layer in buried layer 118 to spread when a reverse bias is applied to the semiconductor device, enhancing the electric field relaxation effect due to the PN junction between buried layer 118 and second portion 113B of drift region 113 provided below buried layer 118, thereby improving the breakdown voltage of the semiconductor device.

On the other hand, it is desirable that the upper surface of the buried layer 118 is lower than the height of the bottom of the gate electrode 137 so that the buried layer 118 is formed below the surface of the drift region 113. Furthermore, it is desirable that the bottom of the buried layer 118 is lower than the upper surface of the field plate 136. The depletion layer due to the PN junction between the buried layer 118 and the second portion 113B provided below the buried layer 118 spreads further downward, improving the breakdown voltage of the semiconductor device.

In FIG. 1, the second portion 113B of the drift region 113 is provided above the buried layer 118 of the mesa region 121, but instead of the second portion 113B of the drift region 113, a breakdown voltage improvement region 120 may be provided, and the buried layer 118 and the breakdown voltage improvement region 120 may be connected. In addition, when multiple trenches 102 or trenches 103 are provided adjacent to each other, the semiconductor region (mesa region 121) sandwiched between the trenches 102 and 103 may have a buried layer 118 in the same manner as the mesa region 103, in the semiconductor region (mesa region) sandwiched between the trenches 102 and 102, and in the semiconductor region (mesa region) sandwiched between the trenches 103 and 103.

Furthermore, the distance between the trenches 102 and 103 in contact with the buried layer 118 (the width of the mesa region 103) may be made wider than the distance between the trenches 101 in the active region.
Furthermore, when at least one of the trenches 102 and the trenches 103 is provided in a plurality of pieces, the interval between the trenches may be gradually increased toward the end of the semiconductor device.
In addition, when at least one of the trenches 102 and 103 is provided in a plurality of pieces, the width of the trench may be gradually narrowed and the depth of the trench may be gradually shallowed toward the end of the semiconductor device. In addition, the thickness or impurity concentration of the buried layer 118 may be gradually thinned toward the end of the semiconductor device. For example, the semiconductor device shown in FIG. 2 is an example of the trench 103 having two trenches, a trench 103A and a trench 103B having a narrower trench width and a shallower trench depth than the trench 103A. According to the semiconductor device shown in FIG. 2, the thickness of the buried layer 118A between the trench 102 and the trench 103A is thicker than the thickness of the buried layer 118B between the trench 103A and the trench 103B. Furthermore, the thickness of the buried layer 118B between the trench 103A and the trench 103B is thicker than the thickness of the buried layer 118C between the trench 103B and the trench 104. The impurity concentration of the buried layer 118A between the trench 102 and the trench 103A is higher than the impurity concentration of the buried layer 118B between the trench 103A and the trench 103B. Furthermore, the impurity concentration of the buried layer 118B between the trench 103A and the trench 103B is higher than the impurity concentration of the buried layer 118C between the trench 103B and the trench 104. This makes the depletion layer spreading in the semiconductor device gentle, thereby improving the breakdown voltage of the semiconductor device.
Moreover, no breakdown voltage improvement region 120 is provided on the upper part of the mesa region including the buried layer 118B. Similarly, the breakdown voltage improvement region 120 is provided in the mesa portion between the trench 102 and the trench 103A and in the mesa portion between the trench 103A and the trench 103B, but the second portion 113B may be formed instead of the breakdown voltage improvement region 120.

As described above, in one or more of the above embodiments, the breakdown voltage can be improved.

One or more of the above-described embodiments can be applied to semiconductor devices including MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulator Gate Bipolar Transistors).

Although the embodiments have been described above, the descriptions and drawings forming part of this disclosure do not limit the present invention, and various alternative embodiments, examples, and operation techniques will become apparent to those skilled in the art. Thus, the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is determined by the invention-specific matters relating to the scope of the claims that are appropriate from the above description.

The present invention is particularly applicable to power semiconductor devices.

101, 102, 103, 104 Trench 111 Source electrode 112 Drain electrode 113 Drift region 114 Base region 115 Source region 116 Drain region 117 Interlayer insulating film 118 Buried layer 119 Protective film 120 Voltage resistance improvement region 121 Mesa region 133 Insulating layers 135, 136 Field plate 137 Gate electrode

Claims (5)

a first semiconductor region of a first conductivity type including a first portion having a high impurity concentration and a second portion having a lower impurity concentration than the first portion and provided on the first portion;
a second semiconductor region of a second conductivity type provided on an upper portion of the first semiconductor region;
a third semiconductor region of the first conductivity type provided on an upper portion of the second semiconductor region;
a first main electrode electrically connected to the first semiconductor region and the second semiconductor region;
a plurality of first trenches formed in the active region to a depth below an interface between the first and second portions of the first semiconductor region and having the third semiconductor region on a side surface thereof;
a second trench having a depth below an interface between the first and second portions and provided in a peripheral region outside the active region closest to the active region;
a third trench provided outside the second trench and having a depth below an interface between the first and second portions;
a mesa portion including a semiconductor region between the second and third trenches and not connected to the first main electrode;
a first insulating layer disposed within the first trench;
a second insulating layer disposed within the second trench;
a third insulating layer disposed within the third trench;
a first field plate provided within the first insulating layer of the first trench;
a second field plate disposed within the second insulating layer of the second trench;
a third field plate provided within the third insulating layer of the third trench;
a gate electrode provided above the first field plate and within the first insulating layer;
a second gate electrode provided above the second field plate and within the second insulating layer;
a fourth semiconductor region of a second conductivity type provided in the mesa portion,
A semiconductor device comprising: a second portion of the first semiconductor region provided below the fourth semiconductor region. The semiconductor device according to claim 1, characterized in that the interface between the first and second portions is within a height range where the second field plate is located. The semiconductor device according to claim 1 or 2, characterized in that the upper surface of the fourth semiconductor region is lower than the height of the bottom of the gate electrode. The semiconductor device according to any one of claims 1 to 3, characterized in that the distance between the second and third trenches is wider than the distance between the first trenches. A plurality of peripheral trenches are provided outside the third trench,
5. The semiconductor device according to claim 1, wherein the widths of the plurality of peripheral trenches are gradually narrower and shallower.

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