KR102627999B1 - Method for manufacturing power semiconductor device - Google Patents

Abstract

A method of manufacturing a power semiconductor device according to an embodiment of the present invention includes forming a mask pattern on a semiconductor layer of silicon carbide (SiC) having a first conductivity type, using the mask pattern as an ion implantation barrier film to the semiconductor layer. Forming a sacrificial impurity region by implanting impurities of a second conductivity type opposite to the first conductivity type, forming a trench by etching a portion of the sacrificial impurity region using the mask pattern as an etch barrier film, and forming a recess gate buried in the trench.

Description

{Method for manufacturing power semiconductor device}

The present invention relates to semiconductor devices, and more particularly, to a method of manufacturing a power semiconductor device for switching power transmission.

Power semiconductor devices are semiconductor devices that operate in high voltage and high current environments. These power semiconductor devices are used in fields that require high-power switching, such as power conversion, power converters, and inverters. For example, power semiconductor devices include an insulated gate bipolar transistor (IGBT) and a power MOSFET (metal oxide semiconductor field effect transistor). These power semiconductor devices basically require withstand voltage characteristics against high voltages, and recently, additionally require high-speed switching operations.

Accordingly, power semiconductor devices using silicon carbide (SiC) instead of existing silicon (Si) are being researched. Silicon carbide (SiC) is a wide-gap semiconductor material with a higher bandgap than silicon, and can maintain stability even at higher temperatures than silicon. Furthermore, silicon carbide has a much higher dielectric breakdown field than silicon, so it can operate stably even at high voltages. Therefore, silicon carbide has a higher breakdown voltage than silicon, but has excellent heat dissipation, showing the ability to operate at high temperatures.

In order to increase the channel density of power semiconductor devices using silicon carbide, a trench-type gate structure with a vertical channel structure is being studied. In this trench-type gate structure, there is a problem that the electric field is concentrated at the edge of the trench.

An embodiment of the present invention seeks to provide a method of manufacturing a silicon carbide power semiconductor device that can increase channel density and reduce channel resistance while alleviating concentration of electric fields at the corners of the gate electrode. However, these tasks are illustrative and do not limit the scope of the present invention.

A method of manufacturing a power semiconductor device according to an embodiment of the present invention includes forming a mask pattern on a semiconductor layer of silicon carbide (SiC) having a first conductivity type, using the mask pattern as an ion implantation barrier film to the semiconductor layer. Forming a sacrificial impurity region by implanting impurities of a second conductivity type opposite to the first conductivity type, forming a trench by etching a portion of the sacrificial impurity region using the mask pattern as an etch barrier film, and forming a gate electrode layer buried in the trench.

Preferably, forming the sacrificial impurity region may include forming a lower region in the sacrificial impurity region to be wider than an upper region.

Preferably, forming the sacrificial impurity region may include forming the lower region to be wider than the trench.

Preferably, forming the trench may include etching a portion of the sacrificial impurity region so that an upper region of the sacrificial impurity region is removed and a lower region remains.

Preferably, forming the trench may include etching a portion of the sacrificial impurity region so that the remaining lower region of the sacrificial impurity region surrounds the lower region of the trench.

Preferably, forming the trench may include etching a portion of the sacrificial impurity region so that the bottom of the trench has a lower depth than the bottom of the sacrificial impurity region.

Preferably, forming the gate electrode layer may include forming a gate insulating layer on the bottom and side surfaces of the trench and forming a gate electrode material on the gate insulating layer to fill the trench. there is.

A power semiconductor device according to an embodiment of the present invention forms a sacrificial impurity region by injecting impurities of a second conductivity type opposite to the first conductivity type into a semiconductor layer of silicon carbide (SiC) having a first conductivity type. and forming a trench by etching the sacrificial impurity region so that an upper region is removed and a lower region remains in the sacrificial impurity region.

Preferably, the step of forming the sacrificial impurity region is such that the sacrificial impurity region is formed to extend from the surface of the semiconductor layer to a certain depth, and the width of the lower region is formed to be wider than the width of the upper region. It may include the step of injecting conductive impurities.

Preferably, forming the trench may include etching the sacrificial impurity region using a mask pattern used when injecting the second conductivity type impurities into the semiconductor layer as an etch mask.

Preferably, forming the trench may include etching the sacrificial impurity region so that the lower region of the trench is surrounded by the lower region of the sacrificial impurity region.

Preferably, the power semiconductor device manufacturing method may further include forming a gate insulating layer on the bottom and side surfaces of the trench and forming a gate electrode material on the gate insulating layer to fill the trench. there is.

According to the power semiconductor device manufacturing method according to an embodiment of the present invention, the concentration of electric fields at the corners of the gate electrode can be alleviated, the channel resistance can be lowered, and the channel density can be increased to increase integration.

Of course, these effects are illustrative, and the scope of the present invention is not limited by these effects.

1 is a perspective view schematically showing the recess gate structure of a power semiconductor device according to an embodiment of the present invention.
2 to 4 are diagrams schematically showing a method of manufacturing the power semiconductor device of FIG. 1.
Figure 5 is a perspective view schematically showing the structure of a power semiconductor device according to an embodiment of the present invention to which the structure of Figure 1 is applied.
FIG. 6 is a horizontal cross-sectional view exemplarily showing a structure cut along the AA′ cutting line in FIG. 5.
Figure 7 is a vertical cross-sectional view exemplarily showing a structure cut along the BB′ cutting line in Figure 6.
FIG. 8 is a vertical cross-sectional view exemplarily showing a structure cut along the CC′ cutting line in FIG. 6.
FIG. 9 is a vertical cross-sectional view exemplarily showing a structure cut along the DD′ cutting line in FIG. 6.
Figure 10 is a graph showing the electric field change according to the depth of the power semiconductor device.
Figure 11 is a perspective view schematically showing the structure of a power semiconductor device according to another embodiment of the present invention to which the structure of Figure 1 is applied.
FIG. 12 is a horizontal cross-sectional view exemplarily showing the structure of the plate gate in FIG. 11.
Figure 13 is a perspective view schematically showing the structure of a power semiconductor device according to another embodiment of the present invention to which the structure of Figure 1 is applied.
Figure 14 is a perspective view schematically showing the structure of a power semiconductor device according to another embodiment of the present invention to which the structure of Figure 1 is applied.
FIG. 15 is a horizontal cross-sectional view exemplarily showing a structure cut along the EE′ cutting line in FIG. 14.
FIG. 16 is a vertical cross-sectional view exemplarily showing a structure cut along the FF′ cutting line in FIG. 15.
FIG. 17 is a vertical cross-sectional view exemplarily showing a structure cut along the GG′ cutting line in FIG. 15.
Figures 18 to 22 are perspective views schematically showing a method of manufacturing the power semiconductor device of Figure 5.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. The examples below make the disclosure of the present invention complete, and provide those of ordinary skill in the art with the scope of the invention. It is provided to provide complete information. Additionally, for convenience of explanation, the size of at least some components may be exaggerated or reduced in the drawings. In the drawings, like symbols refer to like elements.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by a person of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for illustrative purposes and thus serve to illustrate the general structures of the present invention.

Identical reference signs indicate identical elements. It will be understood that when one component, such as a layer, region, or substrate, is referred to as being on another component, it may be directly on top of the other component, or other intervening components may also be present. On the other hand, when referring to one configuration as being “directly on” another configuration, it is understood that there are no intervening configurations.

1 is a perspective view schematically showing the recess gate structure of a power semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, the power semiconductor device may include a semiconductor layer 103, an insulating layer protection region 115, a gate insulating layer 118, and a gate electrode layer 120.

The semiconductor layer 103 may include one or more semiconductor material layers. The semiconductor layer 103 may include one or multiple epitaxial layers. For example, the semiconductor layer 103 may include a silicon carbide (SiC) substrate layer and at least one epitaxial layer of silicon carbide grown using the silicon carbide substrate layer as a seed layer.

Silicon carbide (SiC) has a wider bandgap than silicon, so it can maintain stability even at higher temperatures than silicon. Furthermore, silicon carbide has a much higher dielectric breakdown field than silicon, so it can operate stably even at high voltages. Therefore, a power semiconductor device using silicon carbide as the semiconductor layer 103 has a higher breakdown voltage and excellent heat dissipation characteristics compared to the case using silicon, and can exhibit stable operating characteristics even at high temperatures.

The semiconductor layer 103 may be formed by implanting impurities of the first conductivity type (N type) into silicon carbide. For example, the semiconductor layer 103 includes a silicon carbide substrate layer implanted with a high concentration of impurities of the first conductivity type (N+) and an epitaxial layer of silicon carbide implanted with a low concentration of impurities of the first conductivity type (N-). This may include a layered structure.

The semiconductor layer 103 may provide a path for current movement when operating power is applied to the gate electrode layer 120.

The insulating layer protection region 115 may be formed under the recess gate 120R within the semiconductor layer 103. Preferably, the insulating layer protection region 115 may be formed to surround the lower corner portion of the trench 116 where the recess gate 120R is formed. The insulating layer protection region 115 may include impurities of a second conductivity type (P type) opposite to the first conductivity type.

The gate insulating layer 118 may be formed at least on the inner surface (bottom surface and inner surface) of the trench 116 . For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116 and the semiconductor layer 103 outside the trench 116. The thickness of the gate insulating layer 118 may be uniform, or the portion formed on the bottom of the trench 116 may be thicker than the portion formed on the inner side in order to lower the electric field at the bottom of the trench 116. The gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stacked structure thereof. The gate insulating layer 118 may be formed to extend to the top surface of the semiconductor layer 103.

The gate electrode layer 120 may be formed on the gate insulating layer 118 to fill the trench 116 . Additionally, the gate electrode layer 120 may also be formed on the gate insulating layer 118 on the top surface of the semiconductor layer 103. For example, the gate electrode layer 120 is connected to the recess gate 120R and the recess gate 120R formed to be buried in the trench 116, and is formed in a flat form on the recess gate 120R and the semiconductor layer 103. It may include a plate gate 120P being formed.

The recess gate 120R may be formed to extend a certain length in the Y direction. The insulating layer protection area 115 may also be formed under the recess gate 120R to extend as long as the recess gate 120R in the Y direction. A plurality of recess gates 120R and insulating layer protection regions 115 may be formed along the X direction.

When an operating voltage is applied to the gate electrode layer 120, an electric field may be concentrated in the lower corner of the recess gate 120R, and when the electric field is concentrated, the gate insulating layer 118 in that area is severely stressed. As a result, insulation breakdown of the gate insulating layer 118 may occur. Therefore, in this embodiment, the lower region of the trench 116 in which the recess gate 120R is formed is surrounded by an impurity region 115 of a type opposite to that of the semiconductor layer 103, thereby forming a recess gate ( It is possible to prevent the gate insulating layer 118 from being destroyed by reducing the concentration of the electric field at the corner portion of 120R).

Figures 2 to 4 are diagrams schematically showing a method of manufacturing the power semiconductor device of Figure 1.

First, referring to FIG. 2, a mask pattern 203 defining an area where a trench for a recess gate is to be formed may be formed on the semiconductor layer 103 of silicon carbide (SiC) implanted with impurities of the first conductivity type. . At this time, the mask pattern 203 may include a photoresist film pattern. For example, after forming a photoresist film on the semiconductor layer 103, exposure and development processes are performed to form a mask pattern 203 that exposes the surface of the area where the trench for the recess gate is to be formed in the semiconductor layer 103. It can be.

Next, a sacrificial impurity region 115' may be formed within the semiconductor layer 103 by implanting impurities of the second conductivity type into the semiconductor layer 103 using the mask pattern 203 as an ion implantation barrier layer. The sacrificial impurity region 115' may be formed deeper than the gate trench to be formed in a subsequent process, and the lower region may be formed to be wider than the gate trench. For example, by adjusting the injection angle when injecting impurities, the sacrificial impurity region 115' can be formed so that the lower region of the sacrificial impurity region 115' has a larger width than the upper region, like a bulb shape.

Next, referring to FIG. 3, the gate trench 116 and the insulating layer protection region 115 can be formed by etching the semiconductor layer 103 to a certain depth using the mask pattern 203 as an etch barrier film. . At this time, the bottom surface of the trench 116 may be formed to be higher than the bottom surface of the sacrificial impurity region 115'.

For example, the semiconductor layer 103 is etched to a depth shallower than the bottom surface of the sacrificial impurity region 115' using the photoresist film pattern used as the ion implantation barrier film as an etch barrier film, thereby forming the sacrificial impurity region 115. ′), the area where the trench 116 is formed is removed and only the area surrounding the lower corner area of the trench 116 remains, thereby forming the insulating layer protection area 115.

When a trench is first formed in the semiconductor layer 103 and then impurities are injected into the lower part of the trench, impurities reflected from the inner surface of the trench may be injected around the sidewalls of the trench. That is, the impurity region of the second conductivity type is not only formed at the bottom of the trench, but also around the sidewalls of the trench, thereby severely hindering the movement of current. Therefore, in this embodiment, as described above, impurities are first injected into the semiconductor layer 103 and then the trench 116 is formed so that only a portion of the lower region remains in the corresponding impurity region.

Next, referring to FIG. 4 , a gate insulating layer 118 may be formed on the bottom and sides of the trenches 116 . The gate insulating layer 118 may also be formed on the semiconductor layer 105 outside the trenches 116 . The gate insulating layer 118 may be formed of an oxide obtained by oxidizing the semiconductor layer 103, or may be formed by depositing an insulating material such as oxide or nitride on the semiconductor layer 103. The gate insulating layer 118 may be formed to have a uniform thickness overall, or the portion formed on the bottom of the trench 116 may be thicker than the portion formed on the side surface in order to lower the electric field at the bottom of the trench 116.

Subsequently, a gate electrode material may be formed on the gate insulating layer 118 to fill the trenches 116, thereby forming the gate electrode layer 120. The gate electrode layer 120 may be formed by implanting impurities into polysilicon or may be formed to include a conductive metal or metal silicide.

Figure 5 is a perspective view schematically showing the structure of a power semiconductor device according to an embodiment of the present invention to which the structure of Figure 1 is applied. Figure 6 is a horizontal cross-sectional view exemplarily showing the structure cut along the A-A' cutting line in Figure 5, and Figures 7 to 9 are exemplary structures cut along the B-B', C-C', and D-D' cutting lines in Figure 6, respectively. This is a vertical cross-sectional view shown as .

5 to 9, the power semiconductor device 100 may include a semiconductor layer 105, a gate insulating layer 118, a gate electrode layer 120, an interlayer insulating layer 130, and a source electrode layer 140. You can. For example, the power semiconductor device 100 may include a power MOSFET structure.

The semiconductor layer 105 may include one or more semiconductor material layers. For example, the semiconductor layer 105 may include one or multiple epitaxial layers. Alternatively, the semiconductor layer 105 may include one or multiple epitaxial layers on a semiconductor substrate. For example, the semiconductor layer 105 may include silicon carbide (SiC). Alternatively, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

This semiconductor layer 105 may include a drift region (107). The drift region 107 may be formed of a first conductivity type (N-type), and may be formed by injecting impurities of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by injecting a low concentration of impurities of the first conductivity type (N-) into the epitaxial layer of silicon carbide.

The drift area 107 may provide a path for current movement when the power semiconductor device 100 operates. This drift region 107 is formed to extend in the horizontal direction from the lower portion of the semiconductor layer 105 and provides a horizontal movement path for current, and a horizontal portion 107a within the semiconductor layer 105. It may include a vertical part 107b that is connected to the part 107a and extends in the vertical direction (Z direction) to provide a vertical movement path for electric current. For example, in the drift area 107, the horizontal part 107a may correspond to an area located below the pillar area 111, and the vertical part 107b may correspond to the horizontal part 107a and the well area 110. ) and an area located in contact with the side of the pillar area 111 may correspond. The vertical portion 107b of the drift area 107 in this embodiment may correspond to the semiconductor layer 103 in FIG. 1 described above.

The vertical portion 107b may include regions divided into a plurality of regions by recess gates 120R. In the power semiconductor device 100 of this embodiment, each of the plurality of divided regions can be used as a vertical movement path for current.

The well region 110 may be formed in contact with the drift region 107 in the semiconductor layer 105 and may include impurities of the second conductivity type. For example, the well region 110 may be formed by implanting second conductivity type impurities into an epitaxial layer of silicon carbide.

The well area 110 may be formed to surround at least a portion of the drift area 107 . For example, the well region 110 may be formed to surround an upper portion of the vertical portion 107b in the drift region 107 . In FIG. 1 , the well area 110 is exemplarily shown divided into two areas spaced a certain distance apart in the Y direction by the vertical portion 107b, but may be modified in various other ways. For example, the well region 110 may be formed to entirely surround the side surfaces of the vertical portion 107b in an all-around shape.

A pillar region 111 may be formed in the semiconductor layer 105 below the well region 110 to be connected to the well region 110 . The pillar region 111 may be formed to contact the drift region 107 to form a super junction with the drift region 107 . For example, the pillar region 111 has its upper surface in contact with the well region 110, and its side and lower surfaces are in contact with the vertical portion 107b and the horizontal portion 107a of the drift region 107, respectively. ) can be placed below.

The pillar region 111 may be formed in the semiconductor layer 105 to have a conductivity type opposite to that of the drift region 107 to form a super junction with the drift region 107 . For example, the pillar region 111 may include impurities of a second conductivity type that is opposite to the drift region 107 and the same as that of the well region 110 . At this time, the impurity doping concentration of the pillar region 111 may be equal to or smaller than the impurity doping concentration of the well region 110.

In some embodiments, the pillar region 111 may be formed to have a width narrower than the width of the well region 110 in one direction (Y direction). For example, when the well region 110 and the pillar region 111 are formed to be spaced apart on both sides of the vertical portion 107b, the distance (distance in the Y direction) between the spaced apart pillar regions 111 is It may be formed to be larger than the distance between the well regions 110 (distance in the Y direction). To this end, in the vertical portion 107b of the drift region 107, the length (width) in the Y direction of the portion in contact with the well region 110 is formed to be smaller than the length in the Y direction of the portion in contact with the pillar region 111. You can.

In some embodiments, a plurality of pillar regions 111 and drift regions 107 may be alternately arranged so that their side surfaces contact each other to form a super junction structure. Furthermore, a plurality of pillar regions 111 and drift regions 107 may be alternately arranged under one well region 110 .

Source regions 112 are formed in the well region 110 and may be formed of a first conductivity type. For example, the source regions 112 may be formed between the recess gates 120R within the well region 110, and impurities of the first conductivity type may be injected into a portion of the well region 110. can be formed. The source regions 112 may be formed by implanting impurities of the first conductivity type at a higher concentration than the drift region 107 .

Channel regions 110a may be formed between the vertical portion 107b of the drift region 107 and the source regions 112. The channel regions 110a may include impurities of the second conductivity type. Because the channel regions 110a contain impurities of a second conductivity type opposite to that of the source regions 112 and the drift region 107, a diode junction junction is formed with the source regions 112 and the drift region 107. can be formed. Therefore, the channel regions 110a electrically separate the vertical portion 107b of the drift region 107 and the source regions 112 by not allowing charge movement when the power semiconductor device 100 is not operating. You can do it. On the other hand, when an operating voltage is applied to the gate electrode layer 120, an inversion channel is formed in the channel regions 110a to allow charge movement, thereby allowing the vertical portion of the drift region 107 ( 107b) and the source regions 112 may be electrically connected.

In FIG. 5 , the channel areas 110a are indicated with different reference numbers to distinguish them from the well area 110 , but the channel areas 110a may be part of the well area 110 . For example, the channel regions 110a are the area between the vertical portion 107b of the drift region 107 and the source region 112 of the well region 110 when the operating voltage is applied to the gate electrode layer 120. can be formed in The doping concentration of impurities of the second conductivity type in the channel regions 110a may be the same as that of the well region 110 or may be different to adjust the threshold voltage.

In some embodiments, the well region 110, pillar region 111, channel regions 110a, and source regions 112 are symmetrical in the Y direction with respect to the vertical portion 107b of the drift region 107. can be formed. For example, the well region 110, pillar region 111, channel regions 110a, and source regions 112 are each located on both sides of the vertical portion 107b of the drift region 107 in the Y direction. It may include a part and a second part. Each of the well region 110, pillar region 111, and source regions 112 may be separated from each other by a vertical portion 107b of the drift region 107, or a vertical portion 107b of the drift region 107. ) can also be connected to each other to surround the.

Additionally, the drain region 102 may be formed in the semiconductor layer 105 below the drift region 107 and may include impurities of the first conductivity type. For example, the drain region 102 may include impurities of the first conductivity type (N+) implanted at a higher concentration than the drift region 107.

In some embodiments, drain region 102 may be provided as a substrate of silicon carbide having a first conductivity type. In this case, the drain region 102 may be formed as part of the semiconductor layer 105 or may be formed as a separate substrate from the semiconductor layer 105.

At least one trench 116 may be formed by etching the semiconductor layer 105 from the surface (top surface) of the semiconductor layer 105 to an inside of the semiconductor layer 105 to a predetermined depth. At least one trench 116 may include a plurality of trenches spaced apart at regular intervals along the X direction. The trenches 116 may extend parallel to each other in the Y direction to penetrate the vertical portion 107b of the drift region 107 and the channel region 110a within the semiconductor layer 105 .

The channel regions 110a may be located between the trenches 116, and regions in contact with the well region 110 in the vertical portion 107b of the drift region 107 are formed into a plurality of regions by the trenches 116. It can be divided into fields. In one embodiment, the vertical portion 107b of the drift area 107 may be formed in the form of a partition between the trenches 116, and the partition-shaped vertical portions 107b may be formed on both sides (both sides in the Y direction). A channel area 110a may be located. Additionally, source regions 112 may be located on one side opposite to the channel regions 110a in the Y direction.

Gate insulating layer 118 may be formed on at least the inner surfaces of the trenches 116 . For example, the gate insulating layer 118 may be formed on the inner surface of the trenches 116 and the semiconductor layer 105 outside the trenches 116 . The thickness of the gate insulating layer 118 may be uniform, or the portion formed on the bottom of the trench 116 may be thicker than the portion formed on the sides to lower the electric field at the bottom of the trench 116.

The gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stacked structure thereof.

The gate electrode layer 120 may be formed on the gate insulating layer 118 to fill the trench 116 . Additionally, the gate electrode layer 120 may be formed on the gate insulating layer 118 on the semiconductor layer 105 to cover at least the channel region 110a. For example, the gate electrode layer 120 may include a plurality of recess gates 120R formed to be buried in the trench 116 and spaced at regular intervals along the X direction. In addition, the gate electrode layer 120 is a plate gate formed in a flat shape on the recess gates 120R and the semiconductor layer 105 to cover the channel regions 110a while connecting the plurality of recess gates 120R. (120P) may be included.

The power semiconductor device 100 according to this embodiment has a source region 112 along the Y direction, a channel region 110a, and a vertical region between the plurality of recess gates 120R below the plate gate 120P. Structures in which the portion 107b is connected may be formed. For example, between the plurality of recess gates 120R, a channel region 110a and a source region 112 may be formed to be connected to both walls of the vertical portion 107b in the Y direction. The vertical portion 107b, the channel region 110a, and the source region 112 of the drift region 107 connected in this way may become a path for current movement when the power semiconductor device 100 operates.

In this way, the power semiconductor device 100 according to the present embodiment has a vertical portion 107b of the drift region 107, a channel region 110a, and a source region 112 connected between the plurality of recess gates 120R. By including a multi-lateral channel structure that forms a current movement path, it allows more charges to move simultaneously. In addition, in each movement path, the gate electrode layer 120 is formed to surround three sides (both sides and top surface in the It allows charges to move. The gate electrode layer 120 may include a conductive material, such as polysilicon, metal, metal nitride, or metal silicide, or may include a stacked structure thereof.

The well region 110 may be formed deeper than the recess gates 120R to surround the side surfaces and bottom surfaces of the recess gates 120R.

The interlayer insulating layer 130 may be formed on the gate electrode layer 120. The interlayer insulating layer 130 may include an insulating material for electrical insulation between the gate electrode layer 120 and the source electrode layer 140, for example, an oxide layer, a nitride layer, or a stacked structure thereof.

The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be electrically connected to the source regions 112. The source electrode layer 140 may include a conductive material such as metal.

In the above-described embodiment, it has been described that the first conductivity type and the second conductivity type are N-type and P-type, respectively, but the reverse may also be possible. For example, when the power semiconductor device 100 is an N-type MOSFET, the drift region 107 is an N- region, the source region 112 and the drain region 102 are N+ regions, the well region 110, The pillar area 111 and the channel area 110a may be P- areas.

During operation of the power semiconductor device 100, current flows in the vertical direction from the drain region 102 along the vertical portions 107b of the drift region 107, and then through the channel region 110a to the source region 112. can flow.

In the power semiconductor device 100 described above, the recess gates 120R in the trench 116 may be densely arranged in parallel in a stripe type or line type, and the channel regions 110a may be a recess gate. Since each channel can be placed between the fields 120R, the channel density can be increased.

Additionally, the power semiconductor device 100 according to this embodiment may include second conductivity type insulating layer protection regions 115 surrounding the lower corner portion of the trench 116. These insulating layer protection areas 115 may correspond to the insulating layer protection areas 115 in FIG. 1 described above. As such, the power semiconductor device 100 of the present embodiment includes insulating layer protection regions 115 surrounding the lower corner regions of the recess gates 120R, so that an electric field is applied to the corner portions of the recess gates 120R. It is possible to prevent dielectric breakdown of the gate insulating layer 118 in the corresponding area due to concentration.

In this embodiment, for convenience of explanation, the insulating layer protection areas 115 are displayed separately from the well area 110 even within the well area 110. However, the well area 110 and the insulating layer protection areas 115 ) contains impurities of the same conductivity type, so the insulating layer protection regions 115 may not be displayed within the well region 110 .

In the power semiconductor device 100 according to this embodiment, since current flows through the vertical portions 107b of the drift region 107, when the insulating layer protection region 115 is formed, the current movement path is narrowed and the resistance (JFET resistance) may increase. However, in the power semiconductor device 100 according to this embodiment, JFET resistance can be reduced by using the drift region 107 and the pillar region 111 forming a super junction. For example, in this embodiment, the JFET resistance can be reduced by adjusting the amount of charge in the pillar region 111 and the amount of charge in the drift region 107, as shown in FIG. 10, which will be described later.

Figure 10 is a graph showing the electric field change according to the depth of the power semiconductor device.

Referring to FIG. 10, when the charge amount (Qp) of the pillar region 111 is made larger than the charge amount (Qn) of the drift region 107, the maximum electric field during operation of the power semiconductor device 100 is that of the pillar region 111. The breakdown voltage can be increased by forming the drift area 107 on the same line as the floor surface. In FIG. 10, the slope of the electric field intensity between positions A and B can be controlled by adjusting the charge amount (Qp) of the pillar region 111.

For example, the doping concentration of impurities of the second conductivity type in the pillar region 111 is made higher than the doping concentration of impurities of the first conductivity type in the drift region 107, so that the charge amount (Qp) of the pillar region 111 is By increasing the charge amount (Qn) of the drift region 107, the withstand voltage characteristics of the power semiconductor device 100 can be improved and the JFET resistance can be reduced.

FIG. 11 is a perspective view schematically showing the structure of a power semiconductor device according to another embodiment of the present invention to which the structure of FIG. 1 is applied, and FIG. 12 is a horizontal cross-sectional view exemplarily showing the structure of the plate gate in FIG. 11.

The power semiconductor device 100a according to this embodiment is a partial structure modified from the power semiconductor device 100 of FIGS. 5 to 9, and description of the overlapping structure is omitted.

Referring to FIGS. 11 and 12 , in the power semiconductor device 100a of this embodiment, the plate gate 120P′ is not formed in the form of a single plate, but may be formed in a separated form as shown in FIG. 12 .

For example, the plate gate 120P in FIG. 5 described above has a vertical portion 107b of the drift region 107 and channel regions 110a and source regions 112 on both sides of the vertical portion 107b. Although it is formed in the form of a single plate that covers all of the plate gate 120P' of this embodiment, the gate electrode layer may not be formed on the vertical portion 107b of the drift region 107. That is, the gate electrode layer 120 has a recess gate 120R present only on both sides of the vertical portion 107b of the drift region 107, and the channel regions 110a and For the source regions 112, the recess gate 120R and the plate gate 120P′ may be in a “∩” shape surrounding three sides of the channel regions 110a and the source regions 112. .

As such, in this embodiment, by not forming an electrode material (gate electrode layer) on the vertical portion 107b of the drift region 107, the parasitic capacitance caused by the electrode material can be reduced.

Figure 13 is a perspective view schematically showing the structure of a power semiconductor device according to another embodiment of the present invention to which the structure of Figure 1 is applied.

The power semiconductor device 100b according to this embodiment is a partial structure modified from the power semiconductor device 100 of FIGS. 5 to 9, and description of the overlapping structure is omitted.

Referring to FIG. 13, in the power semiconductor device 100b of this embodiment, source regions 112' may be formed to contact vertical portions 107b of the drift region 107. The source regions 112 ′ may include first conductivity type impurities in the same manner as the source regions 112 .

In the structure of the semiconductor layer 105 of silicon carbide, a potential barrier is formed in the current movement path due to negative charges generated as carbon clusters are formed in the gate insulating layer 118, thereby blocking the movement of current. Accordingly, as in the present embodiment, even if the source regions 112' are formed to contact the vertical portions 107b of the drift region 107, current flows only when an operating voltage is applied to the gate electrode layer 120. An accumulation channel may be formed that allows. At this time, the operating voltage may be significantly lower than the operating voltage for forming an inverted channel in the channel region 110a in FIG. 5.

In the power semiconductor device 100b of this embodiment, the plate gate 120P may be formed in the same shape as in FIG. 11.

Figure 14 is a schematic perspective view showing the structure of a power semiconductor device according to another embodiment of the present invention to which the structure of Figure 1 is applied. Figure 15 is a horizontal cross-sectional view exemplarily showing the structure cut along the E-E' cutting line in Figure 14, and Figures 16 and 17 are vertical cross-sectional views exemplarily showing the structure cut along the F-F' and G-G' cutting lines in Figure 15, respectively. This is a cross-sectional view.

The power semiconductor device 100c according to this embodiment uses or partially modifies the power semiconductor device 100 of FIG. 5, and therefore redundant description is omitted.

Referring to FIGS. 14 to 17 , the power semiconductor device 100c may include at least one gate region GR1 and GR2 and a contact region CR.

The gate regions GR1 and GR2 are regions including the gate electrode layer 120 and may include the structure of FIG. 5, 11, or 13 described above. FIG. 14 shows an embodiment in which the gate regions GR1 and GR2 include the structure of FIG. 5 . Therefore, detailed description of the gate regions GR1 and GR2 will be omitted.

The contact region CR is an area for connecting the source regions 112 of the gate regions GR1 and GR2 with the source electrode layer 140, and may be located on one side of the gate regions SR1 and SR2. The contact region CR may include a drift region 107a, a well region 110, a pillar region 111, a source contact region 112a, a well contact region 114, and a source electrode layer 140.

The drift region 107a, the well region 110, and the pillar region 111 of the contact region CR are the drift region 107a, the well region 110, and the pillar region 111 of the gate regions GR1 and GR2, respectively. ) can be formed integrally with. That is, for convenience of explanation, the gate regions (GR1, GR2), the drift region (107a), the well region (110), and the pillar region (111) of the contact region (CR) are divided, but each of them is an integrated unit. It can be formed into areas.

The source contact area 112a is an area for connecting the source areas 112 and the source electrode layer 140. The source contact region 112a may be located on one side of the gate regions GR1 and GR2 in the Y direction and may be formed integrally with the source regions 112. For example, the source regions 112 may extend to the contact region CR, and the extended source regions 112 may be integrally connected to the outside of the recess gates 120R. At this time, an area in the contact area CR among the areas connected in an integrated manner may become the source contact area 112a. Accordingly, the source contact region 112a may be a part of the source regions 112, and the source regions 112 may be electrically connected to the source electrode layer 140 through the source contact region 112a.

A well contact area 114 may be formed within the source contact area 112a. For example, the well contact region 114 may extend from the well region 110 to penetrate the source contact region 112 . One or more well contact regions 114 may be formed in the source contact region 112a.

The well contact region 114 may include impurities of the second conductivity type. Impurities of the second conductivity type may be injected into the well contact region 114 at a higher concentration than the well region 110 in order to lower contact resistance when connected to the source electrode layer 140. For example, the well contact region 114 may be a P+ region.

The source electrode layer 140 of the contact region CR may be formed to be integrally connected to the source electrode layer 140 of the gate regions GR1 and GR2. The source electrode layer 140 may be commonly connected to the source contact area 112a and the well contact area 114.

The plate gate 120P of the gate regions GR1 and GR2 may be formed to extend in the Y direction to the boundary area between the gate regions GR1 and GR2 and the contact region CR. For example, as shown in FIG. 17 , the plate gate 120P may be formed to extend closer to the contact region CR in the Y direction than the recess gates 120R. The recess gates 120R may be formed to extend to a portion of the well region 110 while penetrating the vertical portion 107b of the drift region 107 in the Y direction.

The source regions 112 formed between the recess gates 120R may be commonly connected to the source contact region 112a. Insulating layer protection regions 115 surrounding the lower corner portions of each of the recess gates 120R may be formed in the vertical portion 107b of the drift region 107 .

14 to 17 , the source contact region 112a and the well contact region 114 are shown as being formed only on one side of the vertical portions 107b of the drift region 107, but the source region 112 and the well region 110 ) is divided into a plurality of regions, the source contact region 112a and the well contact region 114 may be formed in each region. For example, when the source regions 112 on both sides of the vertical portion 107b are electrically connected to each other and the well regions 110 are electrically connected to each other, as shown in FIG. 14, the contact region (CR) may be formed only on one side of the vertical portion 107b. On the other hand, when the source regions 112 on both sides of the vertical portion 107b are electrically separated from each other and the well regions 110 are electrically separated from each other, the contact region CR is the vertical portion ( It can be formed on both sides of 107b).

The power semiconductor device 100c in FIG. 14 includes two gate regions GR1 and GR2 and one contact region CR formed between the gate regions GR1 and GR2, thereby forming one contact region CR. It is commonly connected to these two gate regions (GR1, GR2). However, the power semiconductor device 100b may include one gate region (GR1 or GR2) and one contact region (CR) formed on one side thereof. At this time, the contact region CR may be formed on one side of the gate region GR1 or GR2 in the Y or X direction.

Additionally, the power semiconductor device 100b may include a plurality of gate regions and a plurality of contact regions located between the gate regions. For example, the power semiconductor device 100b may include three or more gate regions arranged at regular intervals along the Y direction and a plurality of contact regions formed one by one between adjacent gate regions. At this time, the structure of adjacent gate regions and the contact region formed between them may be the same as the structure of FIGS. 14 to 17 described above.

Additionally, the plate gates 120P of the gate regions GR1 and GR2 may be formed in the same shape as shown in FIG. 11 .

Figures 18 to 22 are perspective views schematically showing a method of manufacturing the power semiconductor device of Figure 5.

Referring to FIG. 18, a drift region 107' having a first conductivity type may be formed in the semiconductor layer 105 of silicon carbide (SiC). For example, drift region 107' may be formed over drain region 102 having a first conductivity type. In some embodiments, the drain region 102 may be provided as a substrate of a first conductivity type, and the drift region 107' may be formed as one or more epitaxial layers on such a substrate.

Next, referring to FIG. 19 , the well region 110 and the pillar region 111 may be formed by implanting impurities of the second conductivity type into the drift region 107′. For example, after forming a mask pattern (photoresist film pattern) (not shown) to open the area where the well area 110 will be formed on the drift area 107', the mask pattern (photoresist film pattern) (not shown) is formed on the drift area 107' to a certain depth. The vertical portion 107b and the well region 110 may be formed by implanting impurities of type 2 conductivity.

The well region 110 may be formed on at least one side of the vertical portion 107b. For example, the well region 110 may be formed on both sides of the vertical portion 107b in the Y direction or may be formed to surround the vertical portion 107b.

Subsequently, impurities of the second conductivity type may be injected into the drift region 107′ below the well region 110 to form the pillar region 111. For example, the mask pattern used when forming the well region 110 is removed and a mask pattern (not shown) defining the pillar region 111 is formed above the drift region 107′ and then formed below the well region 110. The pillar region 111 may be formed by injecting impurities of the second conductivity type. At this time, the pillar area 111 may be formed so that a drift area 107a of a certain thickness exists below it. In this way, a super junction can be formed by forming the second conductivity type pillar region 111 so that its lower and side surfaces are in contact with the horizontal portion 107a and the vertical portion 107b of the drift region 107, respectively. The pillar region 111 may be formed such that its upper surface is in contact with the well region 110 .

In the above-described embodiment, the case where the well region 110 is formed first and the pillar region 111 is formed below it has been described. However, on the contrary, the pillar region 111 may be formed first and the well region 110 may be formed thereon. It may be possible.

Subsequently, a source region 112″ having a first conductivity type may be formed in the well region 110. For example, the source region 112″ may be formed by implanting impurities of the first conductivity type into the well region 110. The source region 112″ may be formed substantially at a certain depth from the surface of the semiconductor layer 105 and may be formed in a bar shape extending long in the X direction. The source region 112″ may be formed to be spaced apart from the vertical portion 107b by a certain distance. At this time, the area between the source area 112″ and the vertical portion 107b in the well area 110 may be the channel area 110a′. Alternatively, the source region 112″ may be formed to contact the vertical portion 107b, as shown in FIG. 13 .

Next, referring to FIG. 20, a mask pattern (not shown) is formed on the semiconductor layer 105 to open the area where the gate trench will be formed, and then the mask pattern is used as an ion implantation barrier film to form the semiconductor layer 105. A sacrificial impurity region 115' may be formed by injecting impurities of the second conductivity type. For example, by injecting impurities of the second conductivity type into the semiconductor layer 105 in the same manner as in FIG. 2 described above, the width of the lower region of the sacrificial impurity region 115′ is the width of the trench to be created in a subsequent process. It can be formed into a larger bulb shape.

Next, referring to FIG. 21, trenches 116 can be formed by etching the semiconductor layer 105 to a certain depth using the mask pattern used as the ion implantation barrier in FIG. 20 described above as an etch barrier film.

At this time, the depth of the trench 116 is formed to be smaller than the depth of the sacrificial impurity region 115'. That is, the sacrificial impurity region 115' is not completely removed by the trench 116, but remains only to an extent that covers the lower region of the trench 116. As such, in this embodiment, before forming the trench 116, impurities to form the insulating layer protection region 115 are first implanted to form the sacrificial impurity region 115′, and the sacrificial impurity region 115′ is formed using the same mask pattern. By etching 115' only to a certain depth, the insulating layer protection region 115 can be formed only in the lower region of the trench 116.

The trenches 116 are arranged at regular intervals in the It can be formed to extend to a transverse length.

The channel region 110a′ and the source region 112″ are divided into a plurality of regions by these trenches 116, thereby forming a plurality of channel regions 110a and a plurality of source regions 112. there is. Additionally, the vertical portion 107b may also be divided into a plurality of regions by trenches 116 . Each partition-shaped vertical portion 107b divided by the trenches 116 and the channel region 110a and source region 112 connected to the vertical portion 107b may serve as a path for current movement. That is, the power semiconductor device of this embodiment can allow more current to flow at once by including a plurality of current movement paths connected in parallel.

Next, referring to FIG. 22 , a gate insulating layer 118 may be formed on the bottom and sides of the trenches 116 . The gate insulating layer 118 may also be formed on the semiconductor layer 105 outside the trenches 116 . The gate insulating layer 118 may be formed of an oxide obtained by oxidizing the semiconductor layer 105, or may be formed by depositing an insulating material such as oxide or nitride on the semiconductor layer 105.

Subsequently, gate electrode layers 120R and 120P may be formed on the gate insulating layer 118 to fill the trenches 116. For example, the gate electrode layers 120R and 120P are a semiconductor layer to cover the channel regions 110a while connecting the recess gates 120R and the recess gates 120R formed to be buried in the trenches 116. (105) It may include a plate gate (120P) formed in the form of a plate on top. Accordingly, the plate gate 120P and the recess gate 120R have three sides (top surface) of the vertical portions 107b of the drift region, the source regions 112, and the channel regions 110a, like a “∩” shape. and both sides) can be a structure that surrounds the The gate electrode layer 120 may be formed by implanting impurities into polysilicon or may be formed to include a conductive metal or metal silicide.

The lower portion of the recess gates 120R is formed to be surrounded by the second conductive type insulating layer protection region 115, so that the electric field is concentrated on the corner portion of the recess gates 120R and It is possible to prevent the gate insulating layer 118 from being insulated.

Subsequently, an interlayer insulating layer 130 may be formed on the plate gate 120P, and a source electrode layer 140 may be formed on the interlayer insulating layer 130. For example, the source electrode layer 140 may include a conductive layer, such as a metal layer.

The present invention has been described with reference to the embodiments shown in the drawings, but these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the attached patent claims.

100, 100a, 100b: Power semiconductor device
102: drain area
103, 105: semiconductor layer
107: Drift area
110: well area
111: pillar area
112: Source area
115: Insulating layer protection area
118: Gate insulation layer
120: Gate electrode layer
130: Interlayer insulation layer
140: Source electrode layer

Claims (12)

Forming a mask pattern on a semiconductor layer of silicon carbide (SiC) having a first conductivity type;
forming a sacrificial impurity region by implanting impurities of a second conductivity type opposite to the first conductivity type into the semiconductor layer using the mask pattern as an ion implantation barrier layer;
forming a trench by etching a portion of the sacrificial impurity region by reusing the mask pattern used as the ion implantation barrier film as an etch barrier film; and
Including forming a gate electrode layer buried in the trench,
A power semiconductor device manufacturing method wherein the width of the lower region of the sacrificial impurity region is formed to be wider than the width of the upper region, and the width of the trench is formed to be narrower than the width of the lower region of the sacrificial impurity region. delete delete The method of claim 1, wherein forming the trench
A power semiconductor device manufacturing method comprising the step of etching a portion of the sacrificial impurity region so that an upper region of the sacrificial impurity region is removed and a lower region remains. The method of claim 4, wherein forming the trench
A power semiconductor device manufacturing method comprising the step of etching a portion of the sacrificial impurity region so that the remaining lower region of the sacrificial impurity region surrounds a lower region of the trench. The method of claim 1, wherein forming the trench
A power semiconductor device manufacturing method comprising the step of etching a portion of the sacrificial impurity region so that the bottom of the trench has a lower depth than the bottom of the sacrificial impurity region. The method according to claim 1, wherein forming the gate electrode layer
forming a gate insulating layer on the bottom and sides of the trench; and
A power semiconductor device manufacturing method comprising forming a gate electrode material on the gate insulating layer to fill the trench. delete delete delete delete delete

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