JP7537769B2 - Serial interface circuit, control method thereof, program, communication module, and communication device - Google Patents

Description

This disclosure relates to a serial interface circuit, a control method thereof, a program, a communication module, and a communication device.

Communication devices such as routers that mediate data communication between the communication line and the user device support multiple communication speeds, and there may be a difference in speed between the communication speed on the communication line side and the communication speed on the user device side.

In this case, conventionally, this speed difference is absorbed by buffers provided on both the transmitting and receiving sides of the communication device, making it possible to communicate data at different communication speeds (see, for example, Patent Document 1).

JP 2003-249954 A

The following analysis was performed by the inventor.

However, in particular in an interface used for high-speed serial communication such as an XFI interface, for example a serial interface including a sending side transmitter 11 that receives data from a user side device 15 as shown in FIG. 6, a sending side receiver 12 that receives data from the sending side transmitter 11 and transmits the data to a communication line 16, a receiving side transmitter 13 that receives data from the communication line 16, and a receiving side receiver 14 that receives data from the receiving side transmitter 13 and transmits the data to a user side device 15, when the communication speed (or communication protocol) on the communication line 16 side is changed from 10GBASE-T (10 Gbps) to 1000BASE-T (1 Gbps), the amount of data transmitted between the sending side transmitter 11 and the sending side receiver 12 may be excessively reduced below 1 Gbps, which is the maximum speed of 1000BASE-T.

This is thought to be due to the following: When the communication speed on the communication line 16 side is made slower than the communication speed between the sending side transmitting unit 11 and the sending side receiving unit 12, it is necessary to control the amount of data in packets from the sending side transmitting unit 11 to be equal to or lower than the communication speed on the communication line 16 side, so normally a control packet is sent between the receiving side transmitting unit 13 and the receiving side receiving unit 14 to avoid overflow; however, when this control packet is received, the sending side transmitting unit 11 continues transmitting without operating properly, causing an overflow in the buffer provided in the sending side receiving unit 12, which in turn causes the sending side transmitting unit 11 to suppress transmission more than is actually necessary. As a result, an excessive decrease in the amount of communication occurs compared to the communication speed on the communication line 16 side.

The objective of the present disclosure is to provide a serial interface circuit, a control method thereof, a program, a communication module, and a communication device that contribute to reducing the decrease in communication volume caused by a decrease in communication speed on the communication line side.

According to a first aspect of the present disclosure, there is provided a serial interface circuit including a data communication unit including a transmission-side transmitting unit that receives data from a user-side device, and a transmission-side receiving unit that receives data from the transmission-side transmitting unit and transmits the data to a communication line. In the serial interface circuit,
the data communication unit further includes a timing control unit provided between the transmission-side receiving unit and the transmission-side transmitting unit, and a timing control unit buffer connected to the timing control unit;
The timing control unit is configured to, when the communication speed on the communication line side is reduced, capture data from the sending-side transmitting unit into the timing control unit buffer, generate a trigger reference pulse for each predetermined data amount determined based on the communication speed on the user side device side, and transmit, using the timing of the reference pulse, data of a transmittable data amount determined based on the reduced communication speed on the communication line side and the communication speed on the user side device side from the timing control unit buffer to the sending-side receiving unit (form 1).
According to a second aspect of the present disclosure, there is provided a method for controlling a serial interface circuit, wherein the serial interface circuit includes a data communication unit including a sending-side transmitter unit that receives data from a user device, a sending-side receiver unit that receives data from the sending-side transmitter unit and transmits the data to a communication line, a timing control unit provided between the sending-side receiver unit and the sending-side transmitter unit, and a timing control unit buffer connected to the timing control unit.
The control method includes:
a step of capturing data from the transmitting section on the transmitting side into the buffer for the timing control section when the communication speed on the communication line side is reduced;
generating a reference pulse for triggering every predetermined amount of data determined based on a communication speed of the user device; and
a step of transmitting, using the timing of the reference pulse, a transmittable amount of data determined based on the reduced communication speed on the communication line side and the communication speed on the user side device side, from the buffer for timing control unit to the transmission-side receiving unit;
(Form 6).
According to a third aspect of the present disclosure, there is provided a program for causing a computer to execute the control method of the present invention (mode 7).
According to a fourth aspect of the present disclosure, there is provided a communication module including the serial interface circuit of the present invention (mode 8).
According to a fifth aspect of the present disclosure, there is provided a communication device including the communication module of the present invention (mode 9).
The above program can be recorded on a computer-readable (non-transient) storage medium. That is, the present invention is usually embodied by hardware, but can also be embodied as a computer program product. The program is input to the computer device from an input device or an external device via a communication interface, stored in a storage device, and drives the processor according to a predetermined step or process, and can display the processing result, including an intermediate state, at each stage via a display device as necessary, or can communicate with the outside via the communication interface. For example, a computer device for this purpose typically includes a processor, a storage device, an input device, a communication interface, and a display device as necessary, which are connectable to each other via a bus.

In the serial interface circuit of mode 1, the predetermined amount of data can correspond to the maximum amount of data per packet for the communication speed of the user side device (mode 2).
In the serial interface circuit of the first or second aspect, the transmittable data amount is:
W= _WMAX ×( _VN / _VU )
What is required in
Here, W can be the amount of data that can be transmitted, W _MAX can be the maximum amount of data per packet for the communication speed on the user side device side, V _N can be the communication speed on the lowered communication line side, and V _U can be the communication speed on the user side device side (form 3).
In the serial interface circuit of any of forms 1 to 3, the timing control unit may be further configured to assign one or more packets to one pulse within a range not exceeding the transmittable data amount (form 4).
In the serial interface circuit of any of forms 1 to 4, the data communication unit may further include a receiving-side transmitting unit that receives data from the communication line, and a receiving-side receiving unit that receives data from the receiving-side transmitting unit and transmits the data to a user-side device (form 5).
The communication device of aspect 9 may be configured as a router (aspect 10).

This disclosure and each of its aspects can contribute to reducing the decrease in communication volume caused by a decrease in communication speed on the communication line side.

1 shows an example of a configuration of an embodiment of a serial interface circuit according to the present disclosure. 4 is a flowchart illustrating an example of the operation of an embodiment of the serial interface circuit of the present disclosure. 4 is a timing diagram illustrating an example of the operation of an embodiment of a serial interface circuit according to the present disclosure. 13 is a timing diagram illustrating another example of the operation of the serial interface circuit according to the embodiment of the present disclosure. FIG. 2 is a block diagram illustrating an example of a configuration of hardware resources. 1 shows an example of the configuration of a serial interface circuit according to the prior art.

The following provides an overview of the present disclosure. The reference numerals in the drawings attached to this overview are intended solely to aid in the understanding of the present disclosure, and are not intended to limit the present disclosure to the illustrated embodiment. The connection lines between the blocks in each drawing include both bidirectional and unidirectional lines. One-way arrows are used to diagrammatically indicate the flow of signals, information, data, etc., and do not exclude bidirectionality. The connections between the blocks in each drawing can be wired or wireless. The program is executed via a computer device, which includes, for example, a processor, a storage device, an input device, a communication interface, and a display device as necessary, and the computer device is configured to be able to communicate with devices (including computers) within or outside the device via the communication interface, whether wired or wireless.

In this disclosure, "serial interface" includes any serial interface that can be used for high-speed serial communication, such as an XFI interface.

In addition, the "communication device" in this disclosure is typically, but is not limited to, a broadband router, a home gateway device, etc., and includes any communication device that is connected to a "communication line" such as the Internet on one side and to a "user side device" on the other side, mediates data communication between the "communication line" and the "user side device," and is capable of changing the communication speed or communication protocol at least on the "communication line" side.

Furthermore, the "user side device" in this disclosure is a relative concept in the sense that it is located on the user side of a communication device including a serial interface circuit or a communication module when viewed from the "communication line", and is typically, but is not limited to, a user device or user terminal such as a PC (Personal Computer), tablet, PDA (Personal Digital Assistant), or smartphone. For example, when the "communication device" is a wireless LAN (Local Area Network) device, a client or repeater may also be included in the "user side device".

Furthermore, in this disclosure, "connection" can include both wireless and wired methods.

(Embodiment)
1 shows an example of the configuration of an embodiment of a serial interface circuit according to the present disclosure. In this example, the serial interface circuit is embodied as hardware constituting a communication module incorporated in a communication device such as a router.

The serial interface circuit includes a data communication unit including a sending side transmitter 1 that receives data from a user side device 7, a sending side receiver 2 that receives data from the sending side transmitter 1 and transmits the data to a communication line 8, a timing control unit 3 that is provided between the sending side transmitter 1 and the sending side receiver 2 and connected to each of the sending side transmitter 1 and the sending side receiver 2, a timing control unit buffer 4 that is connected to the timing control unit 3, a receiving side transmitter 5 that receives data from the communication line 8, and a receiving side receiver 6 that is connected to the receiving side transmitter 5, receives data from the receiving side transmitter 5, and transmits the data to the user side device 7.

The transmitting side receiving unit 2 and the receiving side transmitting unit 5 can be configured, for example, as the same or separate PHY (PHYsical layer) devices or chips.

The transmitting side transmitter 1, timing control unit 3, and receiving side receiver 6 can be configured as separate processors, for example. However, the transmitting side transmitter 1 and receiving side receiver 6 can also be configured as the same processor. Note that the processor can be, for example, a CPU (Central Processing Unit), MPU (Micro Processor Unit), GPU (Graphics Processing Unit), etc.

Note that in FIG. 1, the components that are typically included in this type of serial interface circuit are omitted. For example, the internal buffer included in the transmitting side receiving unit 2 is omitted.

(Example of operation)
The operation of the present disclosure will be described below for an example in which the serial interface circuit is configured as an XFI interface circuit with reference to Figures 1 to 4. Figure 2 is a flowchart showing an example of the operation of an embodiment of the serial interface circuit of the present disclosure, Figure 3 shows a timing diagram of an example of the operation of an embodiment of the serial interface circuit of the present disclosure, and Figure 4 shows a timing diagram of another example of the operation of an embodiment of the serial interface circuit of the present disclosure.

In this example, the communication speed on the user device 7 side is 10GBASE-X (10 Gbps), and the reduced communication speed on the communication line 8 side is 1000BASE-T (1 Gbps).

In addition, in this example, the timing control unit 3 generates one pulse as a reference pulse for triggering for every maximum data amount of one 10GBASE-X packet (1518 bytes in the case of Ethernet (registered trademark)).

Furthermore, in this example, the memory size or capacity of the timing control unit buffer 4 is several packets to several tens of packets.

First, when the communication speed on the communication line 8 side is reduced to 1000BASE-T (1 Gbps) (see step S1 in FIG. 2), the timing control unit 3 takes the data from the sending side transmitter 1 (see FIG. 3(a) and FIG. 4(a)) into the timing control unit buffer 4 (see step S2 in FIG. 2, FIG. 3(b) and FIG. 4(b)).

Then, the timing control unit 3 determines the amount of data that can be transmitted based on the reduced communication speed of the communication line 8 and the communication speed of the user device 7 (see step S3 in Figure 2), and transmits this amount of data from the timing control unit buffer 4 to the transmitting side receiving unit 2 using the timing of the reference pulse (see step S4 in Figure 2, Figure 3(c), Figure 4(c)).

Here, the amount of data that can be transmitted is, for example,
W= _WMAX ×( _VN / _VU )
where W is the amount of data that can be transmitted, _WMAX is the maximum amount of data per packet for the communication speed on the user device 7 side, _VN is the communication speed on the lowered communication line 8 side, and _VU is the communication speed on the user device 7 side.

In this example, 1/10 of the amount of data between reference pulses (1 Gbps/10 Gbps) is the guideline for the amount of data that can be transmitted, and data is transmitted with one pulse as long as it does not exceed this amount of transmittable data (in this example, 1/10 of the amount of data between reference pulses), and if it exceeds this range, data transmission is halted until the next pulse.

Specifically, the amount of transmittable data corresponds to the transmittable data range between reference pulses (see Fig. 3(c) and Fig. 4(c)), and multiple packets buffered in the timing control unit buffer 4 are each assigned to one transmittable data range and transmitted in sequence to the transmitting side receiving unit 2 (see Fig. 3(c)). On the other hand, when a packet that is small relative to the transmittable data range is transmitted, multiple packets are assigned to one transmittable data range within a range that does not exceed the amount of data, and transmitted in sequence to the transmitting side receiving unit 2 (see Fig. 4(c)).

Note that in Figures 3(c) and 4(c), in order to better show the relationship between the amount of data that can be transmitted and the packets to be transmitted, the transmittable data area between the reference pulses is drawn to be longer than the non-transmittable data area, but in this example, the length of the former is actually 1/10 of the length of the latter.

In this way, according to the present disclosure, by adding a timing control unit and a timing control unit buffer connected to the timing control unit between the sending side transmitting unit and the sending side receiving unit to a serial interface circuit for high-speed serial communication, it is possible to suppress or improve the decrease in the amount of data communication caused by a decrease in the communication speed on the communication line side by controlling the transmission of data.

Depending on the pulse, the communication speed on the communication line 8 side may be temporarily exceeded. However, as described above, the transmitting-side receiving unit 2 usually has a receiving buffer for several to several tens of packets inside, so that overflow can be avoided. Even if the speed is temporarily exceeded, the amount of data to be transmitted by the next pulse can be reduced to less than the amount of data that can be transmitted (in this example, 1/10 of the amount of data between reference pulses), so that the total rate can be adjusted to the target rate when multiple pulses are taken into account together.

In addition, if the sending side transmitter 1 continues to transmit at a rate that exceeds the communication speed of the communication line 8, the receiving buffer of the sending side receiver 2 and the buffer 4 for the timing control unit will overflow. However, in this case, the timing control unit 3 can prevent these buffers from overflowing by sending an interrupt signal to the sending side transmitter 1 (a control device such as a CPU) and forcibly stopping data transmission from the sending side transmitter 1 temporarily.

The components related to the control in the above embodiment can be configured using so-called hardware resources (information processing device, computer), and a device having the configuration shown in FIG. 5 can be used. For example, the hardware resource 100 includes a processor 101, a memory 102, a network interface 103, etc., which are connected to each other by an internal bus 104.

Note that the configuration shown in FIG. 5 is not intended to limit the hardware configuration of the hardware resource 100. The hardware resource 100 may include hardware (e.g., an input/output interface) that is not shown. Furthermore, the number of units such as the processor 101 included in the device is not intended to be limited to the example shown in FIG. 5, and for example, multiple processors 101 may be included in the hardware resource 100. The processor 101 may be, for example, a CPU (Central Processing Unit), an MPU (Micro Processor Unit), a GPU (Graphics Processing Unit), etc.

Memory 102 may be, for example, a RAM (Random Access Memory), a ROM (Read Only Memory), a HDD (Hard Disk Drive), or a SSD (Solid State Drive).

The network interface 103 may be, for example, a LAN (Local Area Network) card, a network adapter, a network interface card, etc.

The functions of the hardware resource 100 can be realized by a processing module. The processing module is realized, for example, by the processor 101 executing a program stored in the memory 102. The program can be downloaded via a network or updated using a storage medium on which the program is stored. Furthermore, the processing module may be realized by a semiconductor chip. In other words, it is sufficient that the functions performed by the processing module can be realized by the execution of software in some kind of hardware.

Although the above describes the transmitting side of the data communication section of the serial interface circuit, the receiving side of the data communication section can be configured in a similar manner. Specifically, by providing a timing control section connected to a timing control section buffer between the receiving side transmitting section 5 and the receiving side receiving section 6 of the data communication section, when the communication speed of the user side device 7 becomes slower than the communication speed of the communication line 8, data or data packets from the receiving side transmitting section 5 can be input into the timing control section buffer in the same manner as above, thereby suppressing the decrease in communication speed on the user side device 7 side.

A part or all of the above-described embodiments can be described as, but is not limited to, the following supplementary notes.
[Supplementary Note 1] A serial interface circuit including a data communication unit including a transmission-side transmitting unit that receives data from a user-side device, and a transmission-side receiving unit that receives data from the transmission-side transmitting unit and transmits the data to a communication line.
The data communication section further includes a timing control section provided between the transmission-side receiving section and the transmission-side transmitting section, and a timing control section buffer connected to the timing control section.
The timing control unit is configured to, when the communication speed on the communication line side is reduced, particularly compared to the communication speed on the user side device side, capture data from the sending-side transmitting unit into the timing control unit buffer, generate a trigger reference pulse for each predetermined data amount determined based on the communication speed on the user side device side, and use the timing of the reference pulse to transmit data from the timing control unit buffer to the sending-side receiving unit, the transmittable data amount being determined based on the reduced communication speed on the communication line side and the communication speed on the user side device side.
[Note 2] In the above serial interface circuit, the predetermined amount of data corresponds to the maximum amount of data per packet for the communication speed of the user device.
[Additional Note 3] In the above serial interface circuit, the amount of data that can be transmitted is:
W= _WMAX ×( _VN / _VU )
where W is the amount of data that can be transmitted, _WMAX is the maximum amount of data per packet for the communication speed on the user side device side, _VN is the communication speed on the lowered communication line side, and _VU is the communication speed on the user side device side.
[Supplementary Note 4] In the above-mentioned serial interface circuit, the timing control section is further configured to allocate one or a plurality of packets to one pulse within a range not exceeding the transmittable data amount.
[Supplementary Note 5] In the above serial interface circuit, the data communication unit further includes a receiving-side transmitting unit that receives data from the communication line, and a receiving-side receiving unit that receives data from the receiving-side transmitting unit and transmits the data to a user-side device.
[Supplementary Note 6] A method for controlling a serial interface circuit including a data communication unit, the method including: a transmitting-side transmitting unit that receives data from a user-side device; a transmitting-side receiving unit that receives data from the transmitting-side transmitting unit and transmits the data to a communication line; a timing control unit provided between the transmitting-side receiving unit and the transmitting-side transmitting unit; and a buffer for the timing control unit connected to the timing control unit.
The control method includes:
a step of taking data from the transmitting side transmitter into the buffer for the timing control unit when the communication speed on the communication line side is lowered, particularly compared with the communication speed on the user side device side;
generating a reference pulse for triggering every predetermined amount of data determined based on a communication speed of the user device; and
a step of transmitting, using the timing of the reference pulse, a transmittable amount of data determined based on the reduced communication speed on the communication line side and the communication speed on the user side device side, from the buffer for timing control unit to the transmission-side receiving unit;
Includes.
[Supplementary Note 7] A program that causes a computer to execute the above control method.
[Appendix 8] A communication module including the above-mentioned serial interface circuit.
[Supplementary Note 9] A communication device including the above-mentioned communication module.
[Supplementary Note 10] The above communication device is configured as a router.
[Supplementary Note 11] In the above serial interface circuit, the transmitting side receiving section includes a receiving buffer therein.
[Supplementary Note 12] A serial interface circuit including a data communication unit including a receiving-side transmitting unit that receives data from a communication line, and a receiving-side receiving unit that receives data from the receiving-side transmitting unit and transmits the data to a user-side device.
The data communication section further includes a timing control section provided between the receiving side receiving section and the receiving side transmitting section, and a timing control section buffer connected to the timing control section.
The timing control unit is configured to, when the communication speed of the user device is reduced, particularly compared to the communication speed of the communication line, capture data from the receiving side transmitting unit into the timing control unit buffer, generate a trigger reference pulse for each predetermined data amount determined based on the communication speed of the communication line, and use the timing of the reference pulse to transmit data from the timing control unit buffer to the receiving side receiving unit, the transmittable data amount being determined based on the reduced communication speed of the user device and the communication speed of the communication line.
[Note 13] In the above serial interface circuit, the predetermined amount of data corresponds to the maximum amount of data per packet for the communication speed on the communication line side.
[Supplementary Note 14] In the above serial interface circuit, the amount of data that can be transmitted is:
W=W _MAX × (V _U /V _N )
where W is the amount of data that can be transmitted, _WMAX is the maximum amount of data per packet for the communication speed on the communication line side, _VN is the communication speed on the communication line side, and _VU is the reduced communication speed on the user side device side.
[Supplementary Note 15] In the above serial interface circuit, the timing control section is further configured to allocate one or a plurality of packets to one pulse within a range not exceeding the transmittable data amount.
[Supplementary Note 16] A method for controlling a serial interface circuit including a data communication unit, the method including: a receiving-side transmitting unit that receives data from a communication line; a receiving-side receiving unit that receives data from the receiving-side transmitting unit and transmits the data to a user-side device; a timing control unit provided between the receiving-side receiving unit and the receiving-side transmitting unit; and a buffer for the timing control unit connected to the timing control unit.
The control method includes:
a step of taking data from the receiving side transmitting unit into the buffer for the timing control unit when the communication speed of the user side device is lowered, particularly compared with the communication speed of the communication line;
generating a reference pulse for triggering for each predetermined amount of data determined based on a communication speed on the communication line; and
a step of transmitting, by utilizing the timing of the reference pulse, a transmittable amount of data determined based on the reduced communication speed of the user device and the communication speed of the communication line from the timing control unit buffer to the receiving unit on the receiving side;
Includes.
[Appendix 17] A program for causing a computer to execute the above control method.
[Supplementary Note 18] A communication module including the above-mentioned serial interface circuit.
[Supplementary Note 19] A communication device including the above communication module.
[Supplementary Note 20] The above communication device is configured as a router.
[Supplementary Note 21] In the above serial interface circuit, the receiving section on the receiving side includes a receiving buffer therein.
[Supplementary Note 22] A serial interface circuit including a data communication unit including a receiving unit that receives data from one of a communication line and a user-side device, and a transmitting unit that receives data from the receiving unit and transmits the data to the other of the communication line and the user-side device.
The data communication section further includes a timing control section provided between the receiving section and the transmitting section, and a timing control section buffer connected to the timing control section.
The timing control unit is configured to, when the communication speed on the transmitting unit side is reduced below the communication speed on the receiving unit side, capture data from the receiving unit into the timing control unit buffer, generate a trigger reference pulse for each predetermined amount of data determined based on the communication speed on the receiving unit side, and use the timing of the reference pulse to transmit data from the timing control unit buffer to the transmitting unit, the amount of data that can be transmitted being determined based on the reduced communication speed on the transmitting unit side and the communication speed on the receiving unit side.
[Supplementary Note 23] A method for controlling a serial interface circuit including a data communication unit, the method including: a receiving unit that receives data from one of a communication line and a user-side device; a transmitting unit that receives data from the receiving unit and transmits the data to the other of the communication line and the user-side device; a timing control unit provided between the receiving unit and the transmitting unit; and a buffer for the timing control unit connected to the timing control unit.
The control method includes:
a step of taking data from the receiving unit into the buffer for timing control unit when the communication speed of the transmitting unit is lowered to be lower than the communication speed of the receiving unit;
generating a reference pulse for triggering every predetermined amount of data determined based on a communication speed of the receiving unit; and
a step of transmitting, from the timing control unit buffer to the transmitting unit, a transmittable amount of data determined based on the reduced communication speed of the transmitting unit and the communication speed of the receiving unit, utilizing the timing of the reference pulse;
Includes.

Within the framework of the entire disclosure of the present invention (including the scope of the claims), modifications and adjustments to the embodiments and examples are possible, based on the basic technical ideas. Furthermore, within the framework of the entire disclosure of the present invention, various combinations and selections (including partial deletions) of the various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible. In other words, the present invention naturally includes various modifications and amendments that a person skilled in the art would be able to make in accordance with the entire disclosure, including the scope of the claims, and the technical ideas.

REFERENCE SIGNS LIST 1 Transmitting side transmitting section 2 Transmitting side receiving section 3 Timing control section 4 Buffer for timing control section 5 Receiving side transmitting section 6 Receiving side receiving section 7 User side device 8 Communication line

REFERENCE SIGNS LIST 11 Transmitting section on transmitting side 12 Transmitting section on transmitting side 13 Receiving section on receiving side 14 Receiving section on receiving side 15 User side device 16 Communication line

100 Hardware resources 101 Processor 102 Memory 103 Network interface 104 Internal bus

Claims (10)

A serial interface circuit including a data communication unit including a transmission side transmitting unit that receives data from a user side device, and a transmission side receiving unit that receives data from the transmission side transmitting unit and transmits the data to a communication line,
the data communication unit further includes a timing control unit provided between the transmission-side receiving unit and the transmission-side transmitting unit, and a timing control unit buffer connected to the timing control unit;
the timing control section is configured to, when the communication speed on the communication line side is reduced, capture data from the transmission side transmitting section into the timing control section buffer, generate a reference pulse for triggering for each predetermined amount of data determined based on the communication speed on the user side device side, and transmit, using the timing of the reference pulse, data of a transmittable amount determined based on the reduced communication speed on the communication line side and the communication speed on the user side device side from the timing control section buffer to the transmission side receiving section.
Serial interface circuit. 2. The serial interface circuit according to claim 1,
A serial interface circuit, wherein the predetermined amount of data corresponds to a maximum amount of data per packet for a communication speed on the side of the user side device. 3. The serial interface circuit according to claim 1,
The amount of data that can be transmitted is
W= _WMAX ×( _VN / _VU )
What is required in
where W is the amount of data that can be transmitted, _WMAX is the maximum amount of data per packet for the communication speed on the user side device side, _VN is the communication speed on the lowered communication line side, and _VU is the communication speed on the user side device side. 4. The serial interface circuit according to claim 1,
the timing control unit is further configured to assign one or a plurality of packets to one pulse within a range not exceeding the transmittable data amount. 5. The serial interface circuit according to claim 1,
the data communication unit further includes a receiving-side transmitting unit that receives data from the communication line, and a receiving-side receiving unit that receives data from the receiving-side transmitting unit and transmits the data to a user-side device. A method for controlling a serial interface circuit including a data communication unit, the serial interface circuit including a transmission side transmitting unit that receives data from a user side device, a transmission side receiving unit that receives data from the transmission side transmitting unit and transmits the data to a communication line, a timing control unit provided between the transmission side receiving unit and the transmission side transmitting unit, and a buffer for timing control unit connected to the timing control unit,
a step of capturing data from the transmitting section on the transmitting side into the buffer for the timing control section when the communication speed on the communication line side is reduced;
generating a reference pulse for triggering every predetermined amount of data determined based on a communication speed of the user device; and
a step of transmitting, using the timing of the reference pulse, a transmittable amount of data determined based on the reduced communication speed on the communication line side and the communication speed on the user side device side, from the buffer for timing control unit to the transmission-side receiving unit;
Including,
Control methods. A program for causing a computer to execute the control method described in claim 6. A communication module including a serial interface circuit according to any one of claims 1 to 5. A communication device including the communication module according to claim 8. The communication device according to claim 9, configured as a router.

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