JP7476765B2 - Switching element drive circuit - Google Patents

Description

The present invention relates to a switching element drive circuit that drives the gate of a switching element.

Switching element drive circuits that drive the gates of switching elements such as IGBTs (insulated gate bipolar transistors) and MOSFETs (metal oxide semiconductor field effect transistors) require reduced switching loss and suppression of switching noise.

19 is an explanatory diagram showing the changes in gate-source voltage V _gs , drain-source voltage V _ds , and drain current I _d caused by switching of an n-type MOSFET. When a positive voltage gate signal is applied (ON) to the gate of an n-type MOSFET, electrons are attracted to the drain-source voltage V gs facing the insulating layer made of silicon oxide directly below the gate, and the drain-source voltage V gs becomes conductive. As a result, as the gate-source voltage V _gs increases beyond the gate threshold, the drain current (device current) I _d , which is the current between the drain and source, increases and then becomes constant after passing through a maximum surge current P1.

As the drain current _Id increases, the drain-source voltage (voltage between the input and output terminals) _Vds, which is the potential difference between the drain and source, starts to decrease, and at the same time, the mirror period begins in which the gate-source voltage _Vgs becomes constant. During the mirror period, the drain-source voltage _Vds decreases to a minimum value and becomes constant.

19, the period from when the drain current _Id begins to increase as a result of the gate-source voltage _Vgs exceeding the gate threshold until the gate-source voltage _Vgs enters the mirror period, in other words, from when the gate-source voltage _Vgs exceeds the gate threshold until just before the drain-source voltage _Vds begins to decrease, is referred to as the current transition period. The mirror period during which the gate-source voltage _Vgs remains constant is also the period from when the drain-source voltage _Vds begins to decrease until it reaches a minimum value, and so this period is referred to as the voltage transition period. The period consisting of the current transition period and the voltage transition period is referred to as the turn-on period, and switching loss occurs in a switching element such as a MOSFET during this turn-on period.

When the gate signal of a positive voltage applied to the gate of the n-type MOSFET is turned OFF, the gate-source voltage V _gs starts to decrease, and the electrons attracted between the drain and source are dispersed, so that the drain and source gradually become insulated. When the mirror period in which the gate-source voltage V _gs becomes constant starts, the drain-source voltage V _ds , which was a minimum value, increases, passes through a maximum value of surge voltage P2, and then becomes constant. Then, when the mirror period ends, the drain current I _d starts to decrease, and when the gate-source voltage V _gs reaches the gate threshold, the drain current I _d decreases to a minimum value and becomes constant.

19, the mirror period during which the gate-source voltage V _gs drops to a constant value is called the voltage transition period. The voltage transition period is also the period from when the drain-source voltage V _ds starts to increase to when the drain current I _d starts to drop. The current transition period is the period during which the gate-source voltage V _gs reaches the gate threshold after the mirror period has elapsed, in other words, until the drain current I _d starts to drop and reaches a minimum value. The period consisting of the current transition period and the voltage transition period is called the turn-off period, and switching losses occur in switching elements such as MOSFETs during this turn-off period as well.

Since switching losses are proportional to the length of each of the turn-on and turn-off periods, shortening each of the turn-on and turn-off periods is desirable in order to reduce switching losses.

In order to shorten each of the turn-on and turn-off periods, it is effective to increase the current slew rate, which is the rate of change of the drain current _Id during the current transition period, and the voltage slew rate, which is the rate of change of the drain-source voltage _Vds during the voltage transition period. In order to increase the current and voltage slew rate at the time of turn-on, it is possible to increase the gate charge current when the gate signal is ON. In addition, it is possible to increase the gate discharge current at the time of turn-off, it is possible to increase the current and voltage slew rate at the time of turn-on.

Therefore, in order to reduce switching losses and suppress switching noise, feedback control of the voltage slew rate and current slew rate during switching is being considered.

However, with this feedback control, if the voltage slew rate and current slew rate during switching increase, electromagnetic noise increases, and there is a risk that EMC standards will not be met, so it is necessary to adjust the voltage slew rate and current slew rate during switching so that the EMC standards are met.

Conventionally, the gate resistance value was set to ensure that the voltage slew rate and current slew rate were within the allowable range, taking into account the individual variations in MOSFETs, and a margin was set to prevent high slew rates from causing large noise, which resulted in large switching losses.

The following Patent Document 1 discloses an invention that measures the load voltage during a first switching cycle and generates a profile to be driven in a second switching cycle based on that information.

U.S. Pat. No. 9,374,081

However, the invention in Patent Document 1 has the problem that the processing load of the detected information increases because the waveform is detected at multiple different points in time during one cycle.

The present invention was created in consideration of the above problems, and aims to obtain a switching element drive circuit that can monitor the current slew rate and voltage slew rate while suppressing the processing load of detection information.

In order to achieve the above object, the switching element drive circuit of the present invention includes a control terminal and an input/output terminal, and includes a voltage detection unit (24U) that detects voltage time series information indicating a change in voltage over time at the input/output terminal of a switching element (44U) in which the input/output terminals are switched in response to an electrical signal applied to the control terminal, a current detection unit (26U) that detects current time series information indicating a change in element current over time of the switching element (44U), and a first voltage time series information detected by the voltage detection unit (24U) during the first switching of the switching element and a current time series information indicating a change in element current over time of the switching element (44U). and a control unit (30U) that controls the current value of the electrical signal based on either a voltage slew rate that is derived based on second voltage time series information detected by the voltage detection unit during a second switching different from the first switching and indicates the voltage change rate between the input and output terminals, or a current slew rate that is derived based on first current time series information detected by the current detection unit (26U) during the first switching and second current time series information detected by the current detection unit (26U) during the second switching and indicates the change rate of the element current.

By configuring it in this way, multiple pieces of time information related to the calculation of the voltage slew rate and current slew rate can be detected when switching at different timings, and the load on the switching element drive circuit related to the detection of changes in the control terminal voltage, etc. using a threshold value can be reduced.

In addition, by controlling the current of the electrical signal applied to the control terminal of the switching element (44U) based on the calculated voltage slew rate and current slew rate, it is possible to suppress the occurrence of surge voltages and the like and reduce the switching loss of the switching element (44U).

1 is a block diagram showing an example of an inverter including a switching element drive circuit according to a first embodiment; FIG. 2 is a block diagram showing an example of a configuration of a gate driver provided at the gate of a switching element. FIG. 4 is a block diagram showing an example of a specific configuration of a control unit. FIG. 11 is an explanatory diagram for calculating a voltage slew rate. FIG. 11 is an explanatory diagram for calculating a current slew rate. 1 is an explanatory diagram showing the relationship between a voltage slew rate and a current slew rate, and the influence on a gate current. FIG. 4 is an explanatory diagram of a general slew rate calculation in the present embodiment. FIG. 13 is an explanatory diagram of a case where low threshold detection is limited to the first time. 13 is a flowchart showing an example of a process in the case where low threshold detection is limited to the first time. 13 is a flowchart for calculating a slew rate and controlling a gate current when a difference occurs between a high threshold detection and a previous high threshold detection. FIG. 11 is an explanatory diagram of slew rate calculation by comparing four or more threshold values. 11 is an explanatory diagram of a case where low threshold detection and high threshold detection are performed when the motor phase currents are approximately the same. FIG. 11 is an explanatory diagram of a case where low threshold detection and high threshold detection are performed when the motor phase currents are substantially the same in the same electrical angle period. FIG. FIG. 13 is an explanatory diagram of a case where a thinning section is provided between low threshold detection and high threshold detection. 13 is an explanatory diagram of a case where a thinning section in which threshold detection is not performed is provided after gate current control. FIG. FIG. 11 is a block diagram showing an example of a configuration of a gate driver provided at the gate of a switching element according to a second embodiment. FIG. 11 is an explanatory diagram showing an overview of slew rate detection based on a control terminal voltage. 10A and 10B are explanatory diagrams showing an example of calculation of a voltage slew rate and a current slew rate based on a control terminal voltage, and control of a gate current. 4 is an explanatory diagram showing changes in gate-source voltage, drain-source voltage, and drain current due to switching of an n-type MOSFET. FIG.

[First embodiment]
Hereinafter, the present embodiment will be described with reference to the drawings. Fig. 1 is a block diagram showing an example of an inverter 10 including a switching element drive circuit according to the present embodiment. The inverter 10 is a three-phase inverter that converts a DC voltage supplied from a DC power source 80, such as an on-board battery, into a three-phase AC voltage of, for example, U-phase, V-phase, and W-phase, and outputs the three-phase AC voltage to a motor 12.

As shown in FIG. 1, the inverter 10 according to this embodiment includes switching elements 42U, 42V, 42W, 44U, 44V, and 44W such as MOSFETs, and generates the power to be supplied to the coils of the stator of the motor 12 by switching the switching elements 42U, 42V, 42W, 44U, 44V, and 44W on and off. For example, the switching elements 42U and 44U switch the power to be supplied to the U-phase coil, the switching elements 42V and 44V switch the power to be supplied to the V-phase coil, and the switching elements 42W and 44W switch the power to be supplied to the W-phase coil.

The drains of the switching elements 42U, 42V, and 42W are connected to the positive pole (+) of the DC power supply 80, and the sources of the switching elements 42U, 42V, and 42W are connected to the drains of the switching elements 44U, 44V, and 44W. The sources of the switching elements 44U, 44V, and 44W are connected to the negative pole (-) of the DC power supply 80.

Node 46U, which connects the source of switching element 42U and the drain of switching element 44U, is connected to the U-phase coil of motor 12. As an example, when switching element 42U is turned on and switching element 44U is turned off, power from DC power supply 80 is supplied to the U-phase coil of motor 12 via node 46U. At the same time, as an example, when switching element 42W is turned off and switching element 44W is turned on, the current flowing through the U-phase coil flows through the W-phase coil via the neutral point of the coil of motor 12. The current flows to the negative pole (-) of DC power supply 80 via node 46W, which connects the source of switching element 42W and the drain of switching element 44W, and switching element 44W. When the U-phase coil and W-phase coil are energized, a magnetic field is generated in the U-phase coil and W-phase coil.

Node 46V, where the source of switching element 42V and the drain of switching element 44V are connected, is connected to the V-phase coil of motor 12. As an example, when switching element 42V is turned on and switching element 44V is turned off, power from DC power supply 80 is supplied to the V-phase coil of motor 12 via node 46V. At the same time, as an example, when switching element 42U is turned off and switching element 44U is turned on, the current flowing through the V-phase coil flows through the U-phase coil via the neutral point of the coil of motor 12. The current flows to the negative pole (-) of DC power supply 80 via node 46U and switching element 44U. When the V-phase coil and the U-phase coil are energized, a magnetic field is generated in the V-phase coil and the U-phase coil.

As another example, when switching element 42W is turned on and switching element 44W is turned off, power from DC power supply 80 is supplied to the W-phase coil of motor 12 via node 46W. At the same time, as an example, when switching element 42V is turned off and switching element 44V is turned on, the current flowing through the W-phase coil flows through the V-phase coil via the neutral point of the coil of motor 12. The current flows to the negative pole (-) of DC power supply 80 via node 46V and switching element 44V. When the W-phase coil and the V-phase coil are energized, a magnetic field is generated in the W-phase coil and the V-phase coil.

As described above, by switching the switching elements 42U, 42V, 42W, 44U, 44V, and 44W (hereafter abbreviated as "switching elements 42U to 44W") to switch the phase in which a magnetic field is generated in the coils of the motor 12, a so-called rotating magnetic field is generated in the coils of the motor 12, which rotates a rotor (rotor) composed of a permanent magnet or the like. In actual motor rotation control, a three-phase AC-like voltage is generated and applied to the coils of each phase of the motor 12 by PWM (pulse width modulation) control that turns each of the switching elements 42U to 44W on and off in short increments.

The switching of the switching elements 42U to 44W may generate parasitic inductances 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, and 72 as shown in FIG. 1. The parasitic inductances 50 to 72 may contribute to the generation of surge voltages. In this embodiment, by appropriately controlling the slew rate (current slew rate and voltage slew rate), it is possible to suppress the generation of surge voltages due to the switching of the switching elements 42U to 44W, which may ultimately offset the effects of the parasitic inductances 50 to 72.

As described above, an n-type MOSFET is turned on by applying a gate signal of positive voltage to the gate. As shown in FIG. 1, in this embodiment, gate drivers 20U, 20V, 20W, 22U, 22V, and 22W (hereinafter abbreviated as "gate drivers 20U to 22W") that control the current value of the gate signal are connected to each of the switching elements 42U to 44W. Each of the gate drivers 20U to 22W is also connected to a higher-level control device (not shown) such as a vehicle ECU (Electronic Control Unit). Each of the gate drivers 20U to 22W amplifies the gate signal input from the higher-level control device, and applies the amplified gate signal to the gate of each of the switching elements 42U to 44W after adjusting the current value with a variable resistor.

Figure 2 is a block diagram showing an example of the configuration of gate driver 22U provided at the gate of switching element 44U. As described above, gate drivers 20U to 22W are provided for each of switching elements 42U to 44W, but gate driver 22U will be explained as a representative example and explanations of the other gate drivers will be omitted.

2, the gate driver 22U includes an input/output terminal voltage detection unit 24U that detects an input/output terminal voltage (drain-source voltage V _ds ), which is the voltage at the input/output terminals of the switching element 44U, in association with time information, an element current detection unit 26U that detects an element current (drain current I _d ) of the switching element 44U in association with time information, a detection processing unit 28U that converts the detection signals of the input/output terminal voltage detection unit 24U and the element current detection unit 26U into signals in a format processable by a control unit 30U described later, a control unit 30U that performs control calculation of a gate signal to be applied to the gate of the switching element 44U based on a slew rate target value input from a higher-level control device and the output of the detection processing unit 28U, and an operation unit 32U that changes the gate drive capability. Each of the input/output terminal voltage detection unit 24U and the element current detection unit 26U detects time information using, for example, a control clock of the control unit 30U.

The element current detection unit 26U may, for example, detect the current value based on the potential difference between both ends of the shunt resistor, or may calculate the current value based on an induced current generated by the passage of current between the source of the switching element 44U and the ground region.

The detection processing unit 28U is a circuit that includes a type of A/D converter that converts the detection signals of the input/output terminal voltage detection unit 24U and the element current detection unit 26U, for example, into digital signals that can be processed by the control unit 30U when the detection signals are analog signals.

Operation unit 32U is a variable resistor that changes its resistance under control of control unit 30U to change the current value of the gate signal applied to the gate of switching element 44U. Operation unit 32U includes variable resistor 32UO that changes the current value of the positive voltage gate signal applied to the gate of switching element 44U, and variable resistor 32UF that changes the current value of the negative voltage gate signal applied to the gate of switching element 44U.

A gate signal is input to the operation unit 32U from a higher-level control device via an amplifier 34U and a complementary MOS 36U, which is a type of inversion circuit. The gate signal input from the higher-level control device is amplified by the amplifier, and then the positive and negative sides are inverted by the complementary MOS 36U. Depending on the positive and negative sides of the gate signal input from the higher-level control device, the complementary MOS 36U may be omitted.

Figure 3 is a block diagram showing an example of a specific configuration of the control unit 30U. The control unit 30U is a type of computer, and includes a CPU (Central Processing Unit) 30UB, a ROM (Read Only Memory) 30UA, a RAM (Random Access Memory) 30UC, and an input/output port 30UD.

In the control unit 30U, the CPU 30UB, ROM 30UA, RAM 30UC, and input/output port 30UD are connected to each other via various buses such as an address bus, a data bus, and a control bus. The input/output port 30UD is connected to various input/output devices such as the detection processing unit 28U, the operation unit 32U, and the higher-level control device 400.

ROM 30UA is installed with a calculation program that calculates the slew rate and a control command program that generates commands to operate operation unit 32U based on the calculated slew rate. In this embodiment, CPU 30UB executes the calculation program to calculate the slew rate. CPU 30UB also generates commands to operate operation unit 32U using the control command program. RAM 30UC is a storage unit that temporarily stores data, and holds, for example, data input from detection processing unit 28U.

Next, various functions that are realized by the CPU 30UB of the control unit 30U executing the calculation program and the control command program will be described. By the CPU 30UB executing the calculation program and the control command program, the CPU 30UB functions as a calculation unit 300A that calculates the slew rate and a control command unit 300B that generates commands to operate the operation unit 32U, as shown in FIG. 3.

Figure 4 is an explanatory diagram of how the voltage slew rate is calculated. There are two types of voltage slew rate: the turn-off voltage slew rate, which is detected when the gate signal is turned off, and the turn-on voltage slew rate, which is detected when the gate signal is turned on.

The calculation of the turn-off voltage slew rate will now be described. To calculate the turn-off voltage slew rate, a time _{Tsr_off_v1} from when the gate signal is turned off until the voltage between the input/output terminals detected by the input/output terminal voltage detection unit 24U reaches the first threshold voltage _Vth1 is detected. In this embodiment, the period from when the gate signal is turned on until when it is turned off again after detecting the time _{Tsr_off_v1} from when the gate signal is turned off until the voltage between the input/output terminals reaches the first threshold voltage _Vth1 is referred to as the low threshold detection section.

A time _{Tsr_off_v2} from when the gate signal is turned off again until the voltage between the input/output terminals detected by the input/output terminal voltage detection unit 24U reaches a second threshold voltage _Vth2 higher than the first threshold voltage _Vth1 is detected. In this embodiment, the period from when the gate signal is turned on until when it is turned off again after detecting the time _{Tsr_off_v2} from when the gate signal is turned off until it reaches the second threshold voltage _Vth2 is referred to as the high threshold detection section.

The section following the high threshold detection section is a dv/dt calculation & control calculation section in which the turn-off voltage slew rate is calculated using the detected _{Tsr_off_v1} and time _{Tsr_off_v2} , and the gate current, which is the current value of the gate signal, is controlled based on the calculated turn-off voltage slew rate. In the dv/dt calculation & control calculation section, the turn-off voltage slew rate is calculated by the following formula (1).

Next, calculation of the turn-on voltage slew rate will be described. To calculate the turn-on voltage slew rate, a time T _{sr_on_v1} from when the gate signal is turned on in the low threshold detection section until the input/output terminal voltage detected by the input/output terminal voltage detection unit 24U drops to the first threshold voltage V _th1 is detected.

In the high threshold detection section following the low threshold detection section, the time T sr_on_v2 from when the gate signal is _turned on until the input/output terminal voltage detected by the input/output terminal voltage detection unit 24U drops to a second threshold voltage V _th2 higher than the first threshold voltage V _th1 is detected.

In the dv/dt calculation & control calculation section following the high threshold detection section, the turn-on voltage slew rate is calculated using the detected times _{Tsr_on_v1} and _{Tsr_on_v2} , and the gate current, which is the current value of the gate signal, is controlled based on the calculated turn-on voltage slew rate. In the dv/dt calculation & control calculation section, the turn-on voltage slew rate is calculated by the following formula (2).

In the operation section following the dv/dt calculation & control operation section, the gate current, which is the current value of the gate signal, is controlled based on the calculated turn-off voltage slew rate dv _off /dt and turn-on voltage slew rate dv _on /dt.

For example, when the absolute value of the turn-off voltage slew rate dv _off /dt is low, the gate current of the gate signal, which is a negative voltage, is increased in the turn-off operation section 90 of the operation section to promote the dispersion of electrons attracted between the drain and source of the switching element 44U. Also, when the absolute value of the turn-off voltage slew rate dv _off /dt is high, the gate current of the gate signal, which is a negative voltage, is decreased in the turn-off operation section 90 of the operation section to suppress the dispersion of electrons attracted between the drain and source of the switching element 44U.

For example, when the absolute value of the turn-on voltage slew rate dv _on /dt is low, the gate current of the gate signal, which is a positive voltage, is increased in the turn-on operation section 92 of the operation section to promote the concentration of electrons between the drain and source of the switching element 44U. Also, when the absolute value of the turn-on voltage slew rate dv _on /dt is high, the gate current of the gate signal, which is a positive voltage, is decreased in the turn-on operation section 92 of the operation section to suppress the concentration of electrons between the drain and source of the switching element 44U.

Figure 5 is an explanatory diagram for calculating the current slew rate. There are two types of current slew rate: the turn-on current slew rate, which is detected when the gate signal is turned on, and the turn-off current slew rate, which is detected when the gate signal is turned off.

The calculation of the turn-on current slew rate will be described. To calculate the turn-on current slew rate, a time T _{sr_on_i1} from when the gate signal is turned on until the device current detected by the device current detection unit _26U reaches the first threshold current I _th1 is detected. In this embodiment, the period from when the gate signal is turned on until when the device current reaches the first threshold current I _th1 is detected until the gate signal is turned off and turned on again is referred to as the low threshold detection section.

The time _{Tsr_on_i2} from when the gate signal turns on again until the device current detected by the device current detection unit 26U reaches a second threshold current _Ith2 higher than the first threshold current _Ith1 is detected. In this embodiment, the period from when the gate signal turns on and when the device current reaches the second _threshold current _Ith2 is detected to when the gate signal turns off and turns on again is referred to as the high threshold detection section.

The section following the high threshold detection section is a dv/dt calculation & control calculation section in which the turn-on current slew rate is calculated using the detected _{Tsr_on_i1} and time _{Tsr_on_i2} , and the gate current, which is the current value of the gate signal, is controlled based on the calculated turn-on current slew rate. In the dv/dt calculation & control calculation section, the turn-on current slew rate is calculated by the following formula (3).

Next, the calculation of the turn-off current slew rate will be described. To calculate the turn-off current slew rate, a time T _{sr_off_i1} from when the gate signal is turned off in the low threshold detection section until the device current detected by the device current detection unit 26U decreases to the first threshold current I _th1 is detected.

In the high threshold detection section following the low threshold detection section, the time T sr_off_i2 from when the gate signal is turned _off until the device current detected by the device current detection unit 26U drops to a second threshold current I _th2 higher than the first threshold current I _th1 is detected.

In the dv/dt calculation & control calculation section following the high threshold detection section, the turn-off current slew rate is calculated using the detected _{Tsr_off_i1} and time _{Tsr_off_i2} , and the gate current, which is the current value of the gate signal, is controlled based on the calculated turn-off current slew rate. In the dv/dt calculation & control calculation section, the turn-off current slew rate is calculated by the following equation (4).

In the operation section following the dv/dt calculation & control operation section, the gate current, which is the current value of the gate signal, is controlled based on the calculated turn-on current slew rate di _on /dt and turn-off current slew rate di _off /dt.

For example, when the absolute value of the turn-on current slew rate di _on /dt is low, the gate current of the gate signal, which is a positive voltage, is increased in the turn-on operation section 94 of the operation section to promote concentration of electrons between the drain and source of the switching element 44U. On the other hand, when the absolute value of the turn-on current slew rate di _on /dt is high, the gate current of the gate signal, which is a positive voltage, is decreased in the turn-on operation section 94 of the operation section to suppress concentration of electrons between the drain and source of the switching element 44U.

For example, when the absolute value of the turn-off current slew rate di _off /dt is low, the gate current of the gate signal, which is a negative voltage, is increased in the turn-off operation section 96 of the operation section to promote the dispersion of electrons attracted between the drain and source of the switching element 44U. Also, when the absolute value of the turn-off current slew rate di _off /dt is high, the gate current of the gate signal, which is a negative voltage, is decreased in the turn-off operation section 96 of the operation section to suppress the dispersion of electrons attracted between the drain and source of the switching element 44U.

Figure 6 is an explanatory diagram showing the relationship between the voltage slew rate and the current slew rate, and the effect on the gate current, combining the above-mentioned Figures 4 and 5 into one figure. As shown in Figure 6, the input/output terminal voltage waveform and the element current waveform have a complementary relationship in that if one increases, the other decreases, and if one increases, the other increases.

In addition, in the operation section, the timing when the voltage between the input and output terminals starts to increase is earlier than the timing when the element current starts to decrease, and the timing when the element current that has decreased to a minimum value starts to increase again is earlier than the timing when the voltage between the input and output terminals starts to decrease. Therefore, by dividing the operation section into four sections, such as the first section 98, the second section 100, the third section 102, and the fourth section 104 as shown in FIG. 6, it becomes possible to control the turn-off voltage slew rate in the first section 98, the turn-off current slew rate in the second section 100, the turn-on current slew rate in the third section 102, and the turn-on voltage slew rate in the fourth section 104 to be changed individually.

As described above, according to this embodiment, the current slew rate and voltage slew rate can be monitored while suppressing the processing load of the detection information.

In this embodiment, one cycle is defined as a period from when the gate signal turns off to when it turns on and immediately before it turns off again, or when the gate signal turns on to when it turns off and immediately before it turns on again. One cycle is defined as a low threshold detection section, and the cycle following the low threshold detection section is defined as a high threshold detection section. Detection using the first threshold voltage V _th1 or the first threshold current I _th1 is performed in the low threshold detection section, and detection using the second threshold voltage V _th2 or the second threshold current I _th2 is performed in the high threshold detection section, thereby reducing the load on the gate drivers 20U to 22W involved in detecting changes in the control terminal voltage, etc., using thresholds.

In addition, by controlling the gate current based on the calculated turn-on voltage slew rate, turn-off voltage slew rate, turn-on current slew rate, and turn-off current slew rate, it is possible to suppress the occurrence of surge voltages and reduce the switching losses of the switching elements 42U to 44W.

Figure 7 is an explanatory diagram of a typical slew rate calculation in this embodiment. In the case shown in Figure 7, a series of cycles consisting of low threshold detection, which is a threshold comparison using a low threshold shown in Figures 4 to 6, high threshold detection, which is a threshold comparison using a high threshold, control calculation to calculate the slew rate, and gate current operation based on the calculated slew rate are repeated in principle. However, depending on the temperature of the inverter 10, the motor phase current, and the power supply voltage of the DC power supply 80, the series of cycles of low threshold detection, high threshold detection, control calculation, and operation, or any of the low threshold detection, high threshold detection, control calculation, and operation included in such a series of cycles, may be interrupted to reduce the load on the gate drivers 20U to 22W. Modifications of this embodiment are described below.

[First Modification]
8 is an explanatory diagram of the case where the low threshold detection is limited to the first time. The low threshold detection is performed at least once while the motor 12 is being driven, and the result of the low threshold detection is stored in the RAM 30UC or the like, which is a storage unit of the control unit 30U. After that, the high threshold detection, the control calculation, and the operation are performed as a series of cycles, and in the control calculation, the voltage slew rate or the current slew rate is calculated using the stored result of the low threshold detection and the newly detected result of the high threshold detection, and in the subsequent operation, the gate current is controlled based on the calculated voltage slew rate or the current slew rate.

Figure 9 is a flow chart showing an example of processing when the low threshold detection shown in Figure 8 is limited to the first detection. In step 800, it is determined whether or not it is the first low threshold detection, and if it is the first detection, the procedure proceeds to step 802, and if it is not the first detection, the procedure proceeds to step 806.

In step 802, low-threshold detection is performed using a low threshold, and the detection result is retained. In steps 804 and 806, high-threshold detection is performed using a high threshold.

In step 808, the voltage slew rate or current slew rate is calculated using the held detection result of the low threshold detection and the detection result of the high threshold detection detected in step 804 or step 806. Then, in step 810, the gate current is controlled based on the calculated voltage slew rate or current slew rate, and the process ends.

In this modified example, low threshold detection is limited to the first time, simplifying the series of processes related to gate current control and reducing the load on gate drivers 20U to 22W.

[Second Modification]
10 is a flow chart for calculating the slew rate and controlling the gate current when a difference occurs between the high threshold detection and the previous high threshold detection. In this modification, when the voltage slew rate or current slew rate is calculated in the control calculation section, the detection result of the high threshold detection is stored in the RAM 30UC, which is the storage unit of the control unit 30U, and then the low threshold detection and the high threshold detection are newly performed, and when the difference between the detection result of the newly performed high threshold detection and the detection result of the stored high threshold detection is equal to or greater than a predetermined value, the gate current is controlled based on the voltage slew rate or current slew rate calculated from the detection result of the newly detected low threshold detection and the detection result of the newly detected high threshold detection. The predetermined value is a value at which a significant change is observed in the voltage slew rate or current slew rate, and is specifically determined through experiments, etc.

Figure 10 shows a process in which the detection results of high threshold detection are stored in advance. In step 900, low threshold detection is performed using a low threshold. In step 902, high threshold detection is performed using a high threshold.

In step 904, the detection result of the high threshold detection detected in step 902 is compared with the detection result of the high threshold detection that is held, and it is determined whether the difference between the two is equal to or greater than a predetermined value. If the difference between the two is equal to or greater than the predetermined value in step 904, the procedure proceeds to step 906, and if the difference between the two is not equal to or greater than the predetermined value, the procedure proceeds to step 902, and high threshold detection is performed.

In step 906, the voltage slew rate or current slew rate is calculated using the detection result of the low threshold detection detected in step 900 and the detection result of the high threshold detection detected in step 902. Then, in step 908, the gate current is controlled based on the calculated voltage slew rate or current slew rate, and the process ends.

In this modified example, if a difference is found between the newly acquired high threshold detection result and the previous value, the voltage slew rate or current slew rate is calculated and the gate current is controlled, simplifying the series of processes related to gate current control and reducing the load on the inverter 10 or gate drivers 20U to 22W.

[Third Modification]
11 is an explanatory diagram of slew rate calculation by comparing four or more thresholds. In this modification, when detecting a voltage slew rate, a difference between adjacent threshold voltages for each of a plurality of different threshold voltages is divided by the difference in time from when the gate signal changes from on to off or from off to on until the voltage detected by the input/output terminal voltage detection unit 24U reaches a threshold voltage related to the difference between the threshold voltages, to calculate a plurality of voltage slew rates. Then, the gate current is controlled based on the rate of change in the time series of the calculated plurality of voltage slew rates.

11, four threshold voltages are set: V _th1a , V _th2a , V _th3a , and V _th4a . The combinations of adjacent threshold voltages are V _th1a and V _th2a , V _th2a and V _th3a , and V _th3a and V _th4a . In this modification, the difference V _th2a -V _th1a between V _th2a and V _th1a is divided by T ₂ -T ₁ which is the difference between the times T ₁ and T ₂ required for the voltage detected by the input/output terminal voltage detection unit 24U to reach the threshold voltages V _th1a and V _th2a , respectively, to calculate the initial slew rate below.

In addition, in this modified example, the difference V _th3a - V _th2a between V _th3a and V _th2a is divided by T ₃ - T ₂ which is the difference between the times T ₂ and T ₃ taken for the voltage detected by the input/output terminal voltage detection unit 24U to reach the threshold voltages V _th2a and V _th3a , respectively, to calculate the medium-term slew rate as follows:

Furthermore, in this modified example, the difference V _th4a - V _th3a between V _th4a and V _th3a is divided by T _{- T3 ,} which is the difference between the times T and T taken for the voltage detected by the input/output terminal voltage detection unit _24U to reach the threshold voltages V _th3a and _{V th4a} , respectively, to calculate the following later slew rate.

In this modified example, by calculating the rate of change of the initial slew rate, the middle slew rate, and the late slew rate calculated as described above, it is possible to grasp the change in the slew rate from the beginning to the end of the rising edge of the waveform of the voltage between the input and output terminals when the gate current is the same. As an example of the rate of change of the initial slew rate, the middle slew rate, and the late slew rate, the difference between the initial slew rate and the middle slew rate, and the difference between the middle slew rate and the late slew rate are calculated, respectively. Furthermore, the rate of change of the slew rate may be grasped by calculating the difference between the initial slew rate and the middle slew rate, and the difference between the middle slew rate and the late slew rate.

11 shows the case where the voltage slew rate is calculated, but the procedure is similar when the current slew rate is calculated. When the current slew rate is calculated, four threshold currents I _th1a , I _th2a , I _th3a , and I _th4a are set. The combinations of adjacent threshold currents are I _th1a and I _th2a , I _th2a and I _th3a , and I _th3a and I _th4a . In this modification, the initial slew rate is calculated by dividing the difference I _th2a -I _th1a between I _th2a and I _th1a by T ₂ -T ₁ , which is the difference between the times T ₁ and T ₂ until the current detected by the element current detection unit 26U reaches the threshold currents I _th1a and I _th2a , respectively.

Similarly, the mid-term slew rate is calculated by dividing the difference I _th3a -I _th2a between I _th3a and I _th2a by T ₃ -T ₂ , which is the difference between the times T ₂ and T ₃ until the current detected by the element current detection unit 26U reaches the threshold currents I _th2a and I _th3a , _{respectively, and the late slew rate is calculated by dividing the difference I th4a -I th3a between I th4a and I th3a by T 4 -T 3} , which is the difference between the times T ₃ and T ₄ until the current detected by the element current detection unit 26U reaches the threshold currents I _th3a and I _th4a , respectively.

Then, the rate of change of the calculated initial slew rate, mid-slew rate, and late slew rate is calculated in the same way as for the voltage slew rate.

[Fourth Modification]
FIG. 12 is an explanatory diagram of the case where low threshold detection and high threshold detection are performed when the motor phase current is approximately the same. As described above, in the actual motor rotation control, a three-phase AC-like voltage is generated and applied to the coils of each phase of the motor 12 by PWM control that turns on and off each of the switching elements 42U to 44W in short bursts, so that the motor phase current supplied to the motor 12 changes approximately in a sinusoidal shape as shown in the middle part of FIG. 12. When the motor phase current is different, the V _ds waveform, which is the waveform of the voltage between the input and output terminals, also differs. The V _ds waveform at the timing when the motor phase current is high tends to be steep as shown in the upper part of FIG. 12. Also, the V _ds waveform at the timing when the motor phase current is low tends to be gentler than the V _ds waveform at the timing when the motor phase current is high as shown in the lower part of FIG. 12.

As shown in Fig. 12, when the motor phase currents are different, the _Vds waveforms differ. In this modification, low threshold detection and high threshold detection are performed at the timing when the motor phase currents appear in each electrical angle cycle are substantially the same, and the voltage slew rate is calculated. Since the _Vds waveforms are substantially the same at the timing when the motor phase currents are substantially the same, the voltage slew rate can be calculated with high accuracy, and as a result, highly accurate gate current control is possible. As an example, the timing when the motor phase currents are substantially the same is detected as the same timing within the electrical angle cycle by counting the control clock of the control unit 30U.

In addition, by detecting the timing at which the motor phase currents become approximately the same for each electrical angle period and performing low threshold detection and high threshold detection, the load on the gate drivers 20U to 22W can be reduced.

In this modified example, the voltage slew rate is calculated, but the current slew rate can also be calculated using the same procedure.

[Fifth Modification]
13 is an explanatory diagram of a case where low threshold detection and high threshold detection are performed when the motor phase current is substantially the same in the same electrical angle period. The motor phase current, which changes in a substantially sinusoidal manner, will have the same value twice in the same electrical angle period unless it is a maximum or minimum value. In this modification, low threshold detection and high threshold detection are performed at substantially the same timing for the motor phase current that appears twice in the same electrical angle period, and the voltage slew rate is calculated. As described above, the _Vds waveform is substantially the same at the timing when the motor phase current is substantially the same, so the voltage slew rate can be calculated with high accuracy, and as a result, highly accurate gate current control is possible.

The timing at which the motor phase currents become approximately the same within the same electrical angle period is detected, for example, by counting the control clock of the control unit 30U within the electrical angle period.

In addition, the timing at which the motor phase currents become approximately the same within the same electrical angle period is longer than the switching period of the switching elements 42U to 44W under PWM control, so the frequency of low threshold detection and high threshold detection per unit time can be reduced, and as a result, the load on the gate drivers 20U to 22W can be reduced.

In this modified example, the voltage slew rate is calculated, but the current slew rate can also be calculated using the same procedure.

[Sixth Modification]
Fig. 14 is an explanatory diagram of a case where a thinning interval is provided between low threshold detection and high threshold detection. In this embodiment, as shown in Fig. 7, low threshold detection, high threshold detection, control calculations for calculating a voltage slew rate or a current slew rate, and gate current manipulation are performed for each switching of the switching elements 42U to 44W under PWM control. However, such operations pose a problem in terms of the load on the gate drivers 20U to 22W.

In this modified example, as shown in FIG. 14, after low threshold detection, a thinning-out section is provided in which high threshold detection is not performed, and high threshold detection is performed following the thinning-out section. The thinning-out section is performed, for example, by the control unit 30U outputting an operation stop signal to each of the input/output terminal voltage detection unit 24U and the element current detection unit 26U. After high threshold detection, a control calculation is performed through the thinning-out section, and after the control calculation, an operation is performed through the thinning-out section. Then, after the operation, low threshold detection is performed again through the thinning-out section. The thinning-out section is a section that includes at least one switching operation, and may extend to multiple switching operations.

As shown in FIG. 14, by providing a thinning section in which no detection, calculation, or operation is performed, the load on the gate drivers 20U to 22W can be reduced.

[Seventh Modification]
Fig. 15 is an explanatory diagram of a case where a thinning-out section is provided in which threshold detection is not performed after controlling the gate current. As shown in Fig. 15, by providing a thinning-out section in which detection, calculation, and manipulation are not performed for at least one switching operation after the gate current is manipulated, the load on the gate drivers 20U to 22W can be reduced.

Second Embodiment
16 is a block diagram showing an example of the configuration of a gate driver 122U provided at the gate of the switching element 44U according to this embodiment. The gate driver 122U according to this embodiment differs from the gate driver 22U according to the first embodiment in that it performs slew rate detection based on the control terminal voltage of the switching element 44U. In addition, the gate driver according to this embodiment includes other gate drivers provided at each of the switching elements 42U to 44W, like the gate driver 120U, but the gate driver 122U will be described as a representative example and the description of the other gate drivers will be omitted.

As shown in FIG. 16 , the gate driver 122U according to this embodiment includes a control terminal voltage detection unit 124U that detects the control terminal voltage (gate-source voltage V _gs ) of the switching element 44U in association with time information, a load current detection unit 132U that is provided between the node 46U and the motor 12 and detects a load current IL in a state in which the element current (drain current I _d ) is constant at a high level, and a power supply voltage detection unit 134U that detects the power supply voltage VH of the DC power supply 80. The detection processing unit 128U converts the detection signals of the control terminal voltage detection unit 124U, the load current detection unit 132U and the power supply voltage detection unit 134U into signals in a format that can be processed by a control unit 130U described later, and the control unit 130U differs from the first embodiment in that the control unit 130U performs a control calculation for a gate signal to be applied to the gate of the switching element 44U based on a slew rate target value input from a higher-level control device and the output of the detection processing unit 128U. However, the other configurations are denoted by the same reference numerals as in the first embodiment and detailed description thereof will be omitted. The configuration of the control unit 130U is also substantially the same as that of the control unit 30U shown in Fig. 3, and therefore a detailed description thereof will be omitted. Furthermore, the control terminal voltage detection unit 124U detects time information using, for example, the control clock of the control unit 130U.

As an example, the load current detection unit 132U may detect the current value based on the potential difference between both ends of the shunt resistor, or may calculate the current value based on an induced current generated by the passage of current between the node 46U and the motor 12. In this embodiment, the element current detection unit 26U of the first embodiment may be provided instead of the load current detection unit 132U. This is because the load current IL is an element current that is detected when the switching element 44U is turned on. In addition, since the load current IL is a value specific to the switching element 44U, it may be a constant specific to the switching element 44U instead of the value detected by the load current detection unit 132U.

The detection processing unit 128U is a circuit that includes a type of A/D converter that converts the detection signals of the control terminal voltage detection unit 124U, the load current detection unit 132U, and the power supply voltage detection unit 134U, for example, into digital signals that can be processed by the control unit 130U when the respective detection signals are analog signals.

Instead of the power supply voltage detection unit 134U, the input/output terminal voltage detection unit 124U of the first embodiment may be provided. This is because the power supply voltage VH is the voltage between the input/output terminals that is detected when the switching element 44U is turned off. In addition, since the power supply voltage VH is a value according to the specifications of the DC power supply 80, when the output of the DC power supply 80 is stable, the nominal voltage of the DC power supply 80 may be used as the power supply voltage VH instead of the detection value by the power supply voltage detection unit 134U or the like.

Figure 17 is an explanatory diagram showing an overview of slew rate detection using the control terminal voltage. Figure 17 shows the time series changes in the gate signal, control terminal voltage, voltage between the input/output terminals, and element current in the same manner as Figure 19 described above. In this embodiment, the slew rate is detected by utilizing the appearance of the following information (1) and (2) in the control terminal voltage.

(1) A drain current transition period T1 from when the control terminal voltage reaches the gate threshold voltage to when it reaches the mirror voltage and becomes constant.
(2) A drain-source voltage transition period T2 corresponding to the mirror period.

In this embodiment, three thresholds of the control terminal voltage are set: a first cycle threshold V _th1c , a second cycle threshold V _th2c , and a third cycle threshold V _th3c . The first cycle threshold V _th1c is the gate threshold voltage V _th itself. The second cycle threshold V _th2c is a value that is close to the mirror voltage _Vm but smaller than the mirror voltage _Vm , and the third cycle threshold V _th3c is a value that is close to the mirror voltage _Vm but larger than the mirror voltage _Vm .

The mirror voltage is calculated by the following formula: In the formula, _Vth is the gate threshold voltage, IL is the load current at which the element current becomes constant at the high level, and gm is the mutual conductance (change in element current with respect to change in control terminal voltage).
_Vm = _Vth + IL/gm

In this embodiment, the load current IL is divided by the drain current transition period T1 to derive the current slew rate di/dt, and the power supply voltage VH is divided by the drain-source voltage transition period T2 to derive the voltage slew rate dv/dt.

As explained using FIG. 19, when the gate signal is turned off, the voltage between the input and output terminals increases and the element current decreases during the turn-off period. As with the turn-on period, the current slew rate di/dt during the turn-off period can be derived from the drain current transition period T1 and the load current IL, and the voltage slew rate dv/dt can be derived from the drain-source voltage transition period T2 and the power supply voltage VH.

17 shows an example in which three control terminal voltage thresholds, a first cycle threshold V _th1c , a second cycle threshold V _th2c , and a third cycle threshold V _th3c , are applied when one gate signal is turned on or off. However, in such a case, it is necessary to perform detection using three thresholds in a short period of time, which may increase the load on the gate drivers 20U to 22W. Therefore, in this embodiment, as will be described later with reference to FIG. 18, detection using each of the first cycle threshold V _th1c , second cycle threshold V _th2c , and third cycle threshold V _th3c is performed when the gate signal is turned on or off at different timings.

Figure 18 is an explanatory diagram showing an example of calculation of the voltage slew rate and current slew rate based on the control terminal voltage, and control of the gate current. In this embodiment, one cycle is defined as the period from when the gate signal turns off to when it turns on and immediately before it turns off again. One cycle is defined as the first threshold detection interval, the cycle following the first threshold detection interval is defined as the second threshold detection interval, and the cycle following the second threshold detection interval is defined as the third threshold detection interval.

In the first threshold detection section, the time _{Tsr_off_1} from when the gate signal is turned off until the control terminal voltage reaches the first cycle threshold _Vth1c is detected, and in the same manner in the first threshold detection section, the time _{Tsr_on_1} from when the gate signal is turned on until the control terminal voltage reaches the first cycle threshold _Vth1c is detected.

In the second threshold detection section, the time _{Tsr_off_2} from when the gate signal is turned off until the control terminal voltage reaches the second cycle threshold _Vth2c is detected, and in the second threshold detection section, the time _{Tsr_on_2} from when the gate signal is turned on until the control terminal voltage reaches the second cycle threshold _Vth2c is detected.

In the third threshold detection section, the time _{Tsr_off_3} from when the gate signal is turned off until the control terminal voltage reaches the third cycle threshold _Vth3c is detected, and similarly in the third threshold detection section, the time _{Tsr_on_3} from when the gate signal is turned on until the control terminal voltage reaches the third cycle threshold _Vth3c is detected.

In the slew rate calculation and control operation section, the turn-off voltage slew rate, turn-on voltage slew rate, turn-off current slew rate, and turn-on current slew rate are calculated using the time detected in each of the first threshold detection section, the second threshold detection section, and the third threshold detection section, the power supply voltage VH detected by the power supply voltage detection unit 134U, and the load current IL detected by the load current detection unit 132U.

The turn-off voltage slew rate is calculated using the following formula (5). The denominator of formula (5) corresponds to the drain-source voltage transition period T2 mentioned above.

The turn-on voltage slew rate is calculated by the following formula (6): The denominator of formula (6) corresponds to the above-mentioned drain-source voltage transition period T2, but since the power supply voltage VH is a positive value and the turn-on voltage slew rate is a negative value, the denominator is made negative by subtracting the time _{Tsr_on_3} from the time _{Tsr_on_2} .

The turn-off current slew rate is calculated by the following formula (7): The denominator of formula (7) corresponds to the above-mentioned drain current transition period T1, but since the load current IL is a positive value and the turn-off current slew rate is a negative value, the denominator is made negative by subtracting the time _{Tsr_off_1} from the time _{Tsr_off_2} .

The turn-on current slew rate is calculated using the following equation (8). The denominator of equation (8) corresponds to the drain current transition period T1 mentioned above.

In the operation section, the gate current, which is the current value of the gate signal, is controlled based on the calculated turn-off voltage slew rate, turn-on voltage slew rate, turn-off current slew rate, and turn-on current slew rate. The manner in which the gate current is controlled is the same as in the first embodiment, so a detailed description is omitted.

As described above, according to this embodiment, the turn-off voltage slew rate, the turn-on voltage slew rate, the turn-off current slew rate, and the turn-on current slew rate can be calculated based on the power supply voltage VH and the load current IL, which have constant detection values and can be stably detected.

The respective times for calculating the turn-off voltage slew rate, the turn-on voltage slew rate, the turn-off current slew rate, and the turn-on current slew rate are detected by applying three thresholds of the control terminal voltage, namely, the first cycle threshold V _th1c , the second cycle threshold V _th2c , and the third cycle threshold V _th3c . In this embodiment, one cycle is defined as a period from when the gate signal is turned off to when it is turned on and immediately before it is turned off again. Then, one cycle is defined as the first threshold detection section, the cycle following the first threshold detection section is defined as the second threshold detection section, and the cycle following the second threshold detection section is defined as the third threshold detection section. Then, the timing for detecting the change in the control terminal voltage using the first cycle threshold V _th1c is defined as the first threshold detection section, the timing for detecting the change in the control terminal voltage using the second cycle threshold V _th2c is defined as the second threshold detection section, and the timing for detecting the change in the control terminal voltage using the third cycle threshold V _th3c is defined as the third threshold detection section, thereby suppressing the load on the gate drivers 20U to 22W related to the detection of the change in the control terminal voltage using the thresholds.
<Additional Notes>
The features of the present invention are as follows.
(Appendix 1)
a voltage detection unit (24U) that detects voltage time series information indicating a time change in voltage of the input/output terminal of a switching element (44U) that includes a control terminal and an input/output terminal and switches between the input/output terminals in response to an electrical signal applied to the control terminal;
a current detection unit (26U) for detecting current time series information indicating a time change of an element current of the switching element (44U);
a control unit (30U) that controls a current value of the electric signal based on either a voltage slew rate that is derived based on first voltage time series information detected by the voltage detection unit (24U) during a first switching of the switching element (44U) and second voltage time series information detected by the voltage detection unit (24U) during a second switching different from the first switching and indicates a voltage change rate between the input/output terminals, or a current slew rate that is derived based on first current time series information detected by the current detection unit (26U) during the first switching and second current time series information detected by the current detection unit (26U) during the second switching and indicates a change rate of the element current;
A switching element drive circuit including:
(Appendix 2)
The control unit (30U) calculates the voltage slew rate by dividing a voltage difference between a first threshold voltage and a second threshold voltage greater than the first threshold voltage by a time difference between a first voltage time extracted from the first voltage time series information, the first voltage time being a time from the time when the electrical signal changes until the voltage of the input/output terminal reaches the first threshold voltage, and a second voltage time extracted from second voltage time series information, the second voltage time being a time from the time when the electrical signal changes until the voltage of the input/output terminal reaches the second threshold voltage.
(Appendix 3)
The control unit (30U) calculates the current slew rate by dividing a current difference between a first threshold current and a second threshold current greater than the first threshold current by a time difference between a first current time extracted from the first current time series information, the first current time being a time from the time the electrical signal changes until the element current reaches the first threshold current, and a second current time extracted from the second current time series information, the second current time being a time from the time the electrical signal changes until the element current reaches the second threshold current.
(Appendix 4)
The control unit (30U) stores the first voltage time in a memory unit (30UC), and then detects the second voltage time a plurality of times, and calculates a plurality of the voltage slew rates using each of the second voltage times detected a plurality of times and the first voltage time stored in the memory unit (30UC).
(Appendix 5)
The control unit (30U) stores the first current time in a memory unit (30UC), and then detects the second current time a plurality of times, and calculates a plurality of the current slew rates using each of the second current times detected a plurality of times and the first current time stored in the memory unit (30UC).
(Appendix 6)
The control unit (30U) stores the second voltage time related to the calculation of the voltage slew rate in a memory unit (30UC), and then newly detects a first voltage time and a second voltage time, and when a difference between the newly detected second voltage time and the second voltage time stored in the memory unit (30UC) is equal to or greater than a predetermined value, controls the current value of the electrical signal based on the voltage slew rate calculated using the newly detected first voltage time and second voltage time.
(Appendix 7)
The control unit (30U) stores the second current time related to the calculation of the current slew rate in the memory unit (30UC), and then newly detects the first current time and the second current time, and when the difference between the newly detected second current time and the second current time stored in the memory unit (30UC) is equal to or greater than a predetermined value, controls the current value of the electrical signal based on the current slew rate calculated using the newly detected first current time and the second current time.
(Appendix 8)
The control unit (30U) extracts, from each of a plurality of voltage time series information detected during each of different switching of the switching element (44U), a time from when the electrical signal changes until it reaches each of the plurality of different threshold voltages, corresponding to each of a plurality of different threshold voltages, calculates a plurality of voltage slew rates by dividing the difference between threshold voltages having adjacent values by the difference in each of the times from when the electrical signal changes until it reaches the adjacent threshold voltage, and controls a current value of the electrical signal based on the rate of change in the time series of the plurality of voltage slew rates.
(Appendix 9)
The control unit (30U) extracts, from each of a plurality of current time series information detected in each of different switching of the switching element (44U), a time from the timing when the electrical signal changes until the respective different threshold currents are reached, corresponding to a plurality of different threshold currents, calculates a plurality of current slew rates by dividing the difference between threshold currents having adjacent values by the difference in each time from the timing when the electrical signal changes until the respective values reach adjacent threshold currents, and controls the current value of the electrical signal based on the rate of change in the time series of the plurality of current slew rates.
(Appendix 10)
The switching element drive circuit according to any one of claims 1 to 3, wherein the second switching is switching subsequent to the first switching.
(Appendix 11)
The switching element drive circuit according to any one of appendices 1 to 3, wherein the second switching is switching at a timing that occurs at each electrical angle period during which the current supplied from the switching element (44U) to the power load (12) is substantially the same as the current supplied from the switching element (44U) to the power load (12) during the first switching.
(Appendix 12)
The switching element drive circuit according to any one of Appendices 1 to 3, wherein the second switching is performed at a timing when a current supplied from the switching element (44U) to the power load (12) becomes substantially the same as a current supplied from the switching element (44U) to the power load (12) during the first switching, in the same electrical angle period.
(Appendix 13)
The switching element drive circuit according to any one of claims 1 to 3, further comprising a thinning-out section for stopping detection by each of the voltage detection unit (24U) and the current detection unit (26U) for at least one switching operation after the first switching operation.
(Appendix 14)
A switching element drive circuit as described in any one of appendices 1 to 3, wherein after calculation of the voltage slew rate and the current slew rate, a thinning-out section is provided for at least one switching operation, in which detection by each of the voltage detection unit (24U) and the current detection unit (26U) and calculation of the voltage slew rate and the current slew rate by the control unit (30U) are stopped.
(Appendix 15)
a control terminal voltage detection unit (124U) that detects control terminal voltage time series information indicating a time change in a voltage of a control terminal of a switching element (44U) that includes a control terminal and an input/output terminal and switches between the input/output terminals in response to an electrical signal applied to the control terminal;
a control unit (130U) that controls a current value of the electrical signal based on either a current slew rate that is derived based on a drain current transition period during which the voltage of the control terminal extracted from the control terminal voltage time-series information reaches a mirror voltage from a gate threshold voltage of the switching element (44U) and indicates a rate of change of an element current of the switching element (44U), or a voltage slew rate that is derived based on a mirror period during which the voltage of the control terminal extracted from the control terminal voltage time-series information becomes the mirror voltage and indicates a rate of change of voltage between the input/output terminals;
A switching element drive circuit including:
(Appendix 16)
The control unit (130U) determines as the drain current transition period a difference between a first time from a first timing at which the electrical signal changes from on to off or off to on until the voltage of the control terminal reaches the gate threshold voltage and a second time from a second timing at which the electrical signal changes from on to off or off to on after the first timing until the voltage of the control terminal reaches a control terminal threshold voltage that is greater than the gate threshold voltage and smaller than the mirror voltage and approximates the mirror voltage, and calculates the current slew rate by dividing the load current of the switching element (44U) by the drain current transition period.
(Appendix 17)
The control unit (130U) determines as the mirror period a difference between the second time and a third time from a third timing at which the electrical signal changes from on to off or from off to on after the second timing until the voltage of the control terminal reaches another control terminal threshold voltage that is greater than the mirror voltage and approximates the mirror voltage, and calculates the voltage slew rate by dividing a power supply voltage by the mirror period.

10 inverter, 12 motor, 22U gate driver, 24U input/output terminal voltage detection unit, 26U element current detection unit, 30U control unit, 32U operation unit, 32UF, 32UO variable resistor, 44U switching element, 90 turn-off operation section, 92 turn-on operation section, 94 turn-on operation section, 96 turn-off operation section, 122U gate driver, 124U control terminal voltage detection unit, 124U input/output terminal voltage detection unit, 130U control unit, 132U load current detection unit, 134U power supply voltage detection unit, _Id drain current, _Ith1 first threshold current, _Ith2 second threshold current, _{Ith1a Ith2a} , _Ith3a , _Ith4a threshold current, IL load current, T1 drain current transition period, T2 drain-source voltage transition period, _T1 , _T2 , T ₃ , _T4 , _{Tsr_off_1} , _{Tsr_off_2} , Tsr_off_3, _{Tsr_on_1} , _{Tsr_on_2} , _{Tsr_on_3} , Tsr_off_v1, _{Tsr_off_v2} , _{Tsr_on_v1} , _{Tsr_on_v2} , _{Tsr_off_i1} , _{Tsr_off_i2} , _{Tsr_on_i1} , _{Tsr_on_i2} time, _Vds drain-source voltage, _{Vgs gate} -source voltage, _{Vm mirror} voltage, _Vth gate threshold voltage, _Vth1 first threshold voltage, _Vth2 second threshold voltage, _Vth1a , _Vth2a , _Vth3a , _Vth4a threshold voltage, _Vth1c first cycle threshold, _Vth2c Second cycle threshold, V _th3c Third cycle threshold, VH Power supply voltage

Claims (14)

a voltage detection unit (24U) that detects voltage time series information indicating a time change in voltage of the input/output terminal of a switching element (44U) that includes a control terminal and an input/output terminal and switches between the input/output terminals in response to an electrical signal applied to the control terminal;
a current detection unit (26U) for detecting current time series information indicating a time change of an element current of the switching element (44U);
a control unit (30U) that controls a current value of the electric signal based on either a voltage slew rate that is derived based on first voltage time series information detected by the voltage detection unit ( 24U) during a first switching of the switching element (44U ) and second voltage time series information detected by the voltage detection unit (24U) during a second switching different from the first switching and indicates a voltage change rate between the input/output terminals, or a current slew rate that is derived based on first current time series information detected by the current detection unit (26U) during the first switching and second current time series information detected by the current detection unit (26U) during the second switching and indicates a change rate of the element current;
A switching element drive circuit including: The control unit (30U) calculates the voltage slew rate by dividing the voltage difference between the first threshold voltage and a second threshold voltage greater than the first threshold voltage by a time difference between a first voltage time extracted from the first voltage time series information, the first voltage time being the time from when the electrical signal changes until the voltage of the input/output terminal reaches the first threshold voltage, and a second voltage time extracted from the second voltage time series information, the second voltage time being the time from when the electrical signal changes until the voltage of the input/output terminal reaches the second threshold voltage. The switching element drive circuit of claim 1. The control unit (30U) calculates the current slew rate by dividing the current difference between the first threshold current and a second threshold current greater than the first threshold current by the time difference between a first current time extracted from the first current time series information, the first current time from the time when the electrical signal changes until the element current reaches the first threshold current, and a second current time extracted from the second current time series information, the second current time from the time when the electrical signal changes until the element current reaches the second threshold current. The switching element drive circuit of claim 1. The switching element drive circuit according to claim 2, wherein the control unit (30U) detects the second voltage time multiple times after storing the first voltage time in the memory unit (30UC), and calculates multiple voltage slew rates using each of the multiple detected second voltage times and the first voltage time stored in the memory unit (30UC). The switching element drive circuit according to claim 3, wherein the control unit (30U) detects the second current time multiple times after storing the first current time in the memory unit (30UC), and calculates multiple current slew rates using each of the multiple detected second current times and the first current time stored in the memory unit (30UC). The control unit (30U) stores the second voltage time related to the calculation of the voltage slew rate in the memory unit (30UC), and then newly detects the first voltage time and the second voltage time, and when the difference between the newly detected second voltage time and the second voltage time stored in the memory unit (30UC) is equal to or greater than a predetermined value, controls the current value of the electrical signal based on the voltage slew rate calculated from the newly detected first voltage time and the second voltage time. The switching element drive circuit of claim 2. The control unit (30U) stores the second current time related to the calculation of the current slew rate in the memory unit (30UC), and then newly detects the first current time and the second current time, and when the difference between the newly detected second current time and the second current time stored in the memory unit (30UC) is equal to or greater than a predetermined value, controls the current value of the electrical signal based on the current slew rate calculated from the newly detected first current time and the second current time. The switching element drive circuit of claim 3. 2. The switching element drive circuit according to claim 1, wherein the control unit (30U) extracts, from each of a plurality of pieces of voltage time series information detected during each of different switching of the switching element (44U) , a time from when the electrical signal changes until it reaches each of the plurality of different threshold voltages , corresponding to each of a plurality of different threshold voltages, and calculates a plurality of voltage slew rates by dividing a difference between threshold voltages having adjacent values by a difference in each of the times from when the electrical signal changes until it reaches the adjacent threshold voltage, and controls a current value of the electrical signal based on a rate of change in the time series of the plurality of voltage slew rates. 2. The switching element drive circuit according to claim 1, wherein the control unit (30U) extracts, from each of a plurality of current time series information detected in each of different switching of the switching element (44U) , a time from when the electrical signal changes until the respective different threshold currents are reached, corresponding to a plurality of different threshold currents , and calculates a plurality of current slew rates by dividing a difference between threshold currents having adjacent values by a difference in each time from when the electrical signal changes until the respective values reach adjacent threshold currents, and controls a current value of the electrical signal based on a rate of change in the time series of the plurality of current slew rates. The switching element drive circuit according to any one of claims 1 to 3, wherein the second switching is switching subsequent to the first switching. The switching element drive circuit according to any one of claims 1 to 3, wherein the second switching occurs at a timing that occurs every electrical angle period when the current supplied from the switching element (44U) to the power load (12) is substantially the same as the current supplied from the switching element (44U) to the power load (12) during the first switching. The switching element drive circuit according to any one of claims 1 to 3, wherein the second switching is performed at a timing when the current supplied from the switching element (44U) to the power load (12) during the same electrical angle period is substantially the same as the current supplied from the switching element (44U) to the power load (12) during the first switching. The switching element drive circuit according to any one of claims 1 to 3, wherein after the first switching, a thinning-out section is provided for at least one switching in which detection by each of the voltage detection unit (24U) and the current detection unit (26U) is stopped. The switching element drive circuit according to any one of claims 1 to 3, wherein after the calculation of the voltage slew rate and the current slew rate, a thinning-out section is provided for at least one switching operation in which detection by the voltage detection unit (24U) and the current detection unit (26U) and calculation of the voltage slew rate and the current slew rate by the control unit (30U) are stopped.