JP2022077362A - Switching element driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a switching element drive circuit capable of monitoring a current slew rate and a voltage slew rate while suppressing a processing load of detection information.
SOLUTION: A control unit 30U detects a first voltage time series information in a first switching of a switching element 44U and a second voltage time detected in a second switching different from the first voltage time series information. The voltage through rate indicating the voltage change rate between the input / output terminals of the switching element 44U derived based on the series information, the first current time series information detected in the first switching, and the detection in the second switching. The current value of the gate signal applied to the gate of the switching element 44U based on one of the current through rate, which is the rate of change of the element current of the switching element 44U derived based on the second current time series information. Control.
[Selection diagram] Fig. 2

Description

The present invention relates to a switching element drive circuit that drives the gate of the switching element.

Switching element drive circuits that drive the gates of switching elements such as IGBTs (insulated gate bipolar transistors) and MOSFETs (metal oxide semiconductor field effect transistors) are required to reduce switching loss and suppress switching noise.

FIG. 19 is an explanatory diagram showing changes in the gate-source voltage V _gs , the drain-source voltage V _ds , and the drain current I _d due to switching of the n-type MOSFET. When a positive voltage gate signal is applied (ON) to the gate of the n-type MOSFET, electrons are attracted between the drain sources facing the insulating layer made of silicon oxide directly under the gate, and the drain sources are in a conductive state. become. As a result, as the gate-source voltage V _gs exceeds the gate threshold value, the drain current (element current) _Id , which is the current between the drain sources, increases and becomes constant via the surge current P1 which is the maximum value.

As the drain current I _d increases, the drain-source voltage (voltage between input / output terminals) V _ds , which is the potential difference between the drain sources, begins to decrease, and at the same time, the mirror period becomes constant when the gate-source voltage V _gs becomes constant. During the mirror period, the drain-source voltage V _ds drops to a minimum value and becomes constant.

In FIG. 19, since the gate-source voltage V _gs exceeds the gate threshold value, the drain current _{Id starts to increase until the gate-source voltage V gs reaches} the mirror period, in other words, the gate-source voltage. The period from when V _g s exceeds the gate threshold to immediately before the drain-source voltage V _d s begins to decrease is referred to as a current transition period. Further, the mirror period in which the gate-source voltage V _gs is constant is also a period from the time when the drain-source voltage V _ds starts to decrease to the time when the minimum value is reached. Therefore, the period is referred to as a voltage transition period. The period composed of the current transition period and the voltage transition period is referred to as a turn-on period, and a switching loss in a switching element such as a MOSFET occurs in the turn-on period.

When the positive gate signal applied to the gate of the n-type MOSFET is turned off, the gate-source voltage V _gs begins to decrease, the electrons attracted between the drain sources are dispersed, and the drain source gradually disperses. It becomes insulated. When the mirror period in which the gate-source voltage V _gs becomes constant begins, the drain-source voltage V _ds , which was the minimum value, increases and becomes constant via the surge voltage P2, which is the maximum value. Then, at the timing when the mirror period ends, the drain current I _d begins to decrease, and when the gate-source voltage V _gs reaches the gate threshold value, the drain current I _d decreases to a minimum value and becomes constant.

In FIG. 19, the mirror period in which the gate-source voltage V _gs decreases and becomes a constant value is referred to as a voltage transition period. The voltage transition period is also the period from the time when the drain-source voltage V _ds starts to increase to the time when the drain current I _d starts to decrease. Further, the period until the gate-source voltage V _gs reaches the gate threshold value after the mirror period elapses, in other words, the drain current _Id starts to decrease and reaches the minimum value is referred to as a current transition period. The period composed of the current transition period and the voltage transition period is referred to as a turn-off period, and switching loss in a switching element such as a MOSFET occurs even in such a turn-off period.

Since the switching loss is proportional to the length of each of the turn-on period and the turn-off period, it is desirable to shorten each of the turn-on period and the turn-off period in order to reduce the switching loss.

To shorten each of the turn-on period and turn-off period, the current slew rate, which is the rate of change of the drain current _{Id during the current transition period, and the voltage slew rate, which is the rate of change of the drain-source voltage V ds during} the voltage transition period. It is effective to increase each. Increasing the turn-on current and voltage slew rate can be achieved by increasing the gate charge current when the gate signal is ON. Further, the turn-off can be achieved by increasing the gate discharge current when the gate is turned off.

Therefore, in order to reduce the switching loss and suppress the switching noise, feedback control of the voltage slew rate and the current slew rate at the time of switching has been studied.

However, in such feedback control, if the voltage slew rate and the current slew rate during switching increase, electromagnetic noise may increase and the EMC standard may not be satisfied. The current slew rate needs to be adjusted.

Conventionally, the gate resistance value is set so that the voltage slew rate and the current slew rate are within the allowable values in consideration of the variation in MOSFET differences, and a margin is taken so that noise does not become large due to the high slew rate. Therefore, there is a problem that the switching loss becomes large.

The following Patent Document 1 discloses an invention in which a load voltage is measured during a first switching cycle and a profile driven in the second switching cycle is generated based on the information.

US Pat. No. 9,374,081

However, the invention according to Patent Document 1 has a problem that the processing load of the detection information increases because the waveforms at a plurality of different time points in one cycle are detected.

The present invention has been created in view of the above problems, and an object of the present invention is to obtain a switching element drive circuit capable of monitoring a current slew rate and a voltage slew rate while suppressing a processing load of detection information.

In order to achieve the above object, the switching element drive circuit according to the present invention includes a control terminal and an input / output terminal, and the switching element (switching between the input / output terminals is switched according to an electric signal applied to the control terminal). The voltage detection unit (24U) for detecting the time-series information indicating the time change of the voltage of the input / output terminal of the 44U) and the current time-series information indicating the time change of the element current of the switching element (44U) are detected. The current detection unit (26U), the first voltage time series information detected by the voltage detection unit (24U) in the first switching of the switching element, and the voltage in the second switching different from the first switching. The current detection unit (26U) detects the voltage through rate, which is derived based on the second voltage time series information detected by the detection unit and indicates the rate of change in voltage between the input / output terminals, and the first switching. A current through that is derived based on the first current time-series information obtained and the second current time-series information detected by the current detection unit (26U) in the second switching and indicates the rate of change of the element current. It includes a control unit (30U) that controls the current value of the electric signal based on either one of the rates.

With this configuration, a plurality of time information related to the calculation of the voltage slew rate and the current slew rate can be detected at the time of switching at different timings, and related to the detection of changes in the control terminal voltage and the like using the threshold value. The load on the switching element drive circuit can be suppressed.

Further, by controlling the current of the electric signal applied to the control terminal of the switching element (44U) based on the calculated voltage slew rate and current slew rate, the generation of surge voltage and the like is suppressed, and the switching element (44U) is used. ) Switching loss can be reduced.

It is a block diagram which showed an example of the inverter which provided the switching element drive circuit which concerns on 1st Embodiment. It is a block diagram which showed an example of the structure of the gate driver provided in the gate of a switching element. It is a block diagram which shows an example of the specific structure of a control part. It is explanatory drawing at the time of voltage slew rate calculation. It is explanatory drawing at the time of current slew rate calculation. It is explanatory drawing which showed the relationship between the voltage slew rate and the current slew rate, and the influence on the gate current. It is explanatory drawing of the general slew rate calculation in this embodiment. It is explanatory drawing when the low threshold value detection is limited to the first time. It is a flowchart which showed an example of the processing when the low threshold value detection was limited to the first time. It is a flowchart when the slew rate is calculated and the gate current is controlled when the difference from the previous high threshold value detection occurs in the high threshold value detection. It is explanatory drawing of the slew rate calculation by the comparison of four or more thresholds. It is explanatory drawing in the case of performing each of low threshold value detection and high threshold value detection when the motor phase current is substantially the same. It is explanatory drawing in the case of performing each of low threshold value detection and high threshold value detection when the motor phase current is substantially the same in the same electric angle cycle. It is explanatory drawing in the case of providing the thinning-out section between the low threshold value detection and the high threshold value detection. It is explanatory drawing in the case of providing the thinning section which does not perform the threshold value detection after the control of a gate current. It is a block diagram which showed an example of the structure of the gate driver provided in the gate of the switching element which concerns on 2nd Embodiment. It is explanatory drawing which showed the outline of the slew rate detection by a control terminal voltage. It is explanatory drawing which showed the calculation of the voltage slew rate and the current slew rate by the control terminal voltage, and an example of the control of a gate current. It is explanatory drawing which showed the change of the gate-source voltage, the drain-source voltage, and the drain current by switching of an n-type MOSFET.

[First Embodiment]
Hereinafter, this embodiment will be described with reference to the drawings. FIG. 1 is a block diagram showing an example of an inverter 10 provided with a switching element drive circuit according to the present embodiment. The inverter 10 is a three-phase inverter that converts a DC voltage supplied from a DC power source 80, which is an in-vehicle battery, into, for example, a U-phase, V-phase, and W-phase three-phase AC voltage and outputs the DC voltage to the motor 12. ..

As shown in FIG. 1, the inverter 10 according to the present embodiment includes switching elements 42U, 42V, 42W, 44U, 44V, 44W such as MOSFETs, and supplies electric power supplied to the coil of the stator of the motor 12 to the switching elements. It is generated by switching to turn 42U, 42V, 42W, 44U, 44V, 44W on and off. For example, the switching elements 42U and 44U switch the power to be supplied to the U-phase coil, the switching elements 42V and 44V to the V-phase coil, and the switching elements 42W and 44W to the W-phase coil.

The drains of the switching elements 42U, 42V and 42W are connected to the positive electrode (+) of the DC power supply 80, and the sources of the switching elements 42U, 42V and 42W are the respective sources of the switching elements 44U, 44V and 44W. It is connected to the drain. Further, each source of the switching element 44U, 44V, 44W is connected to the negative electrode (−) of the DC power supply 80.

The node 46U to which the source of the switching element 42U and the drain of the switching element 44U are connected is connected to the U-phase coil of the motor 12. As an example, when the switching element 42U is turned on and the switching element 44U is turned off, the power of the DC power supply 80 is supplied to the U-phase coil of the motor 12 via the node 46U. At the same time, as an example, when the switching element 42W is turned off and the switching element 44W is turned on, the current flowing through the U-phase coil flows through the W-phase coil through the neutral point of the coil of the motor 12. The current flows to the negative electrode (-) of the DC power supply 80 via the node 46W to which the source of the switching element 42W and the drain of the switching element 44W are connected and the switching element 44W. When the U-phase coil and the W-phase coil are energized, a magnetic field is generated in the U-phase coil and the W-phase coil.

The node 46V to which the source of the switching element 42V and the drain of the switching element 44V are connected is connected to the V-phase coil of the motor 12. As an example, when the switching element 42V is turned on and the switching element 44V is turned off, the power of the DC power supply 80 is supplied to the V-phase coil of the motor 12 via the node 46V. At the same time, as an example, when the switching element 42U is turned off and the switching element 44U is turned on, the current flowing through the V-phase coil flows through the U-phase coil through the neutral point of the coil of the motor 12. The current flows to the negative electrode (−) of the DC power supply 80 via the node 46U and the switching element 44U. When the V-phase coil and the U-phase coil are energized, a magnetic field is generated in the V-phase coil and the U-phase coil.

Further, as an example, when the switching element 42W is turned on and the switching element 44W is turned off, the power of the DC power supply 80 is supplied to the W phase coil of the motor 12 via the node 46W. At the same time, as an example, when the switching element 42V is turned off and the switching element 44V is turned on, the current flowing through the W-phase coil flows through the V-phase coil through the neutral point of the coil of the motor 12. The current flows to the negative electrode (-) of the DC power supply 80 via the node 46V and the switching element 44V. When the W-phase coil and the V-phase coil are energized, a magnetic field is generated in the W-phase coil and the V-phase coil.

As described above, by switching the phase in which a magnetic field is generated in the coil of the motor 12 by switching the switching elements 42U, 42V, 42W, 44U, 44V, 44W (hereinafter, abbreviated as "switching elements 42U to 44W"), A so-called rotating magnetic field that rotates a rotor (rotor) composed of a permanent magnet or the like is generated in the coil of the motor 12. In the actual rotation control of the motor, a three-phase alternating current-like voltage is generated and applied to the coils of each phase of the motor 12 by PWM (pulse width modulation) control in which each of the switching elements 42U to 44W is turned on and off in small steps.

The switching of the switching elements 42U to 44W may generate parasitic inductances 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72 as shown in FIG. The parasitic inductances 50 to 72 can contribute to the generation of surge voltage. In the present embodiment, by appropriately controlling the slew rate (current slew rate and voltage slew rate), it is possible to suppress the generation of surge voltage due to switching of the switching elements 42U to 44W, so that the parasitic inductance 50 to 72 is used. In some cases, the effects can be offset as a result.

As described above, the n-type MOSFET is turned on by applying a positive voltage gate signal to the gate. As shown in FIG. 1, in the present embodiment, each of the switching elements 42U to 44W has gate drivers 20U, 20V, 20W, 22U, 22V, 22W (hereinafter, "gate driver") for controlling the current value of the gate signal. 20U-22W ”) are connected to each other. Further, each of the gate drivers 20U to 22W is connected to a higher-level control device (not shown) such as a vehicle ECU (Electronic Control Unit). Each of the gate drivers 20U to 22W amplifies the gate signal input from the upper control device, and applies the amplified gate signal to each gate of the switching elements 42U to 44W by adjusting the current value with a variable resistor. do.

FIG. 2 is a block diagram showing an example of the configuration of the gate driver 22U provided at the gate of the switching element 44U. As described above, the gate drivers 20U to 22W are provided in each of the switching elements 42U to 44W, but the gate driver 22U will be described as a typical example, and the description of other gate drivers will be omitted.

As shown in FIG. 2, the gate driver 22U detects the input / output terminal voltage (drain / source voltage V _ds ), which is the voltage of the input / output terminals of the switching element 44U, in association with the time information. Each of the voltage detection unit 24U, the element current detection unit 26U that detects the element current (drain current Id) of the switching element _44U in association with the time information, and the input / output terminal voltage detection unit 24U and the element current detection unit 26U, respectively. The switching element 44U is based on the detection processing unit 28U that converts the detection signal of the above into a signal in a format that can be processed by the control unit 30U described later, the through rate target value input from the upper control device, and the output of the detection processing unit 28U. It is provided with a control unit 30U that performs a control calculation of a gate signal applied to the gate of the above, and an operation unit 32U that changes the gate drive capability. Each of the input / output terminal voltage detection unit 24U and the element current detection unit 26U detects time information using, for example, the control clock of the control unit 30U.

As an example, the element current detection unit 26U may detect a current value based on the potential difference between both ends of the shunt resistor, or based on the induced current generated by energization between the source and the ground region of the switching element 44U. The current value may be calculated.

For example, when the detection signals of the input / output terminal voltage detection unit 24U and the element current detection unit 26U are analog signals, the detection processing unit 28U is a kind of A / that converts them into digital signals that can be processed by the control unit 30U. It is a circuit including a D converter.

The operation unit 32U is a variable resistor that changes the resistance value under the control of the control unit 30U to change the current value of the gate signal applied to the gate of the switching element 44U. The operation unit 32U has a variable resistor 32UO that changes the current value of the positive voltage gate signal applied to the gate of the switching element 44U, and a variable resistor 32UO that changes the current value of the negative voltage gate signal applied to the gate of the switching element 44U. Includes a resistor 32UF.

A gate signal is input to the operation unit 32U from a higher-level control device via an amplifier 34U and a complementary MOS 36U which is a kind of inverting circuit. The gate signal input from the upper control device is amplified by the amplifier, and then the positive and negative are inverted by the complementary MOS36U. The complementary MOS 36U may be omitted depending on the positive / negative mode of the gate signal input from the upper control device.

FIG. 3 is a block diagram showing an example of a specific configuration of the control unit 30U. The control unit 30U is a kind of computer, and includes a CPU (Central Processing Unit) 30UB, a ROM (Read Only Memory) 30UA, a RAM (Random Access Memory) 30UC, and an input / output port 30UD.

In the control unit 30U, the CPU 30UB, ROM 30UA, RAM 30UC, and input / output port 30UD are connected to each other via various buses such as an address bus, a data bus, and a control bus. As various input / output devices, a detection processing unit 28U, an operation unit 32U, a higher-level control device 400, and the like are connected to the input / output port 30UD, respectively.

A calculation program for calculating the slew rate, a control command program for generating a command for operating the operation unit 32U based on the calculated slew rate, and the like are installed in the ROM 30UA. In this embodiment, the slew rate is calculated by the CPU 30UB executing a calculation program. Further, the CPU 30UB generates a command for operating the operation unit 32U by the control command program. The RAM 30UC is a storage unit that temporarily stores data, and holds, for example, data input from the detection processing unit 28U.

Next, various functions realized by the CPU 30UB of the control unit 30U executing the arithmetic program and the control command program will be described. When the CPU 30UB executes an arithmetic program and a control command program, the CPU 30UB serves as a control command unit 300B for generating commands for operating the arithmetic unit 300A for calculating the slew rate and the operation unit 32U, as shown in FIG. Function.

FIG. 4 is an explanatory diagram when calculating the voltage slew rate. The voltage slew rate includes a turn-off voltage slew rate detected when the gate signal is turned off and a turn-on voltage slew rate detected when the gate signal is turned on.

The calculation of the turn-off voltage slew rate will be described. To calculate the turn-off voltage slew rate, set the time T _{sr_off_v1} from when the gate signal is turned off until the voltage between the input / output terminals detected by the input / output terminal voltage detection unit 24U reaches the first threshold voltage V _th1 . To detect. In the present embodiment, the time until the gate signal is turned off and the voltage between the input / output terminals reaches the first threshold voltage V _th1 After detecting T _{sr_off_v1} , the period until the gate signal is turned on and turned off again. Is referred to as a low threshold detection section.

The time from when the gate signal is turned off again until the voltage between the input / output terminals detected by the input / output terminal voltage detection unit 24U reaches the second threshold voltage V _th2 , which is higher than the first threshold voltage V _th1 , T _{sr_off_v2} . To detect. In the present embodiment, the time until the gate signal is turned off and the voltage between the input / output terminals reaches the second threshold voltage V _th2 . After detecting T _{sr_off_v2} , the period until the gate signal is turned on and turned off again. Is referred to as a high threshold detection section.

In the section following the high threshold detection section, the turn-off voltage slew rate is calculated using the detected T _{sr_off_v1} and time T _{sr_off_v2} , and the gate current, which is the current value of the gate signal, is controlled based on the calculated turn-off voltage slew rate. This is the dv / dt calculation & control calculation section to be performed. In the dv / dt calculation & control calculation section, the turn-off voltage slew rate is calculated by the following equation (1).

Next, the calculation of the turn-on voltage slew rate will be described. To calculate the turn-on voltage slew rate, the voltage between the input / output terminals detected by the input / output terminal voltage detection unit 24U drops to the first threshold voltage V _th1 after the gate signal is turned on in the low threshold detection section. Time until T _{sr_on_v1} is detected.

In the high threshold detection section following the low threshold detection section, the voltage between the input / output terminals detected by the input / output terminal voltage detection unit 24U after the gate signal is turned on is higher than the first threshold voltage V _th1 . The time T _{sr_on_v2} until the threshold voltage drops to V _th2 is detected.

In the dv / dt calculation & control calculation section following the high threshold detection section, the turn-on voltage slew rate is calculated using the detected time T _{sr_on_v1} and time T _{sr_on_v2} , and the gate signal is based on the calculated turn-on voltage slew rate. Controls the gate current, which is the current value. In the dv / dt calculation & control calculation section, the turn-on voltage slew rate is calculated by the following equation (2).

In the operation section following the dv / dt calculation & control calculation section, the gate current, which is the current value of the gate signal, is controlled based on the calculated turn-off voltage slew rate dv _off / dt and turn-on voltage slew rate dv _on / dt. ..

For example, when the absolute value of the turn-off voltage slew rate dv _off / dt is low, the gate current of the gate signal, which is a negative voltage, is increased in the turn-off operation section 90 of the operation section to attract it between the drain sources of the switching element 44U. Promotes the dispersion of the generated electrons. When the absolute value of the turn-off voltage slew rate dv _off / dt is high, the gate current of the gate signal, which is a negative voltage, is reduced in the turn-off operation section 90 of the operation section to attract the switch element 44U between the drain sources. It suppresses the dispersion of the generated electrons.

For example, when the absolute value of the turn-on voltage slew rate dv _on / dt is low, the gate current of the gate signal, which is a positive voltage, is increased in the turn-on operation section 92 of the operation section to the drain source of the switching element 44U. Encourage the concentration of electrons. When the absolute value of the turn-on voltage slew rate dv _on / dt is high, the gate current of the gate signal, which is a positive voltage, is reduced in the turn-on operation section 92 of the operation section to the drain source of the switching element 44U. Suppress the concentration of electrons.

FIG. 5 is an explanatory diagram when calculating the current slew rate. The current slew rate includes a turn-on current slew rate detected when the gate signal is turned on and a turn-off current slew rate detected when the gate signal is turned off.

The calculation of the turn-on current slew rate will be described. To calculate the turn-on current slew rate, the time T _{sr_on_i1} from when the gate signal is turned on until the element current detected by the element current detection unit 26U reaches the first threshold current I _th1 is detected. In the present embodiment, the time until the gate signal is turned on and the element current reaches the first threshold current It _th1 is _detected , and then the period until the gate signal is turned off and turned on again is a low threshold value. It is called the detection section.

The time T _{sr_on_i2} from when the gate signal is turned on again until the element current detected by the element current detection unit 26U reaches the second threshold current I _th2 , which is higher than the first threshold current I _th1 is detected. In the present embodiment, the time until the gate signal is turned on and the element current reaches the second threshold current I _th2 is _detected , and then the period until the gate signal is turned off and turned on again is a high threshold value. It is called the detection section.

In the section following the high threshold detection section, the turn-on current slew rate is calculated using the detected T _{sr_on_i1} and the time T _{sr_on_i2} , and the gate current, which is the current value of the gate signal, is controlled based on the calculated turn-on current slew rate. This is the dv / dt calculation & control calculation section to be performed. In the dv / dt calculation & control calculation section, the turn-on current slew rate is calculated by the following equation (3).

Next, the calculation of the turn-off current slew rate will be described. To calculate the turn-off current through rate, set the time T _{sr_off_i1} from when the gate signal is turned off in the low threshold value detection section until the element current detected by the element current detection unit 26U drops to the first threshold current It _th1 . To detect.

In the high threshold detection section following the low threshold detection section, after the gate signal is turned off, the element current detected by the element current detection unit 26U drops to the second threshold current I _th2 , which is higher than the first threshold current I _th1 . Time to do T _{sr_off_i2} is detected.

In the dv / dt calculation & control calculation section following the high threshold detection section, the turn-off current slew rate is calculated using the detected T _{sr_off_i1} and time T _{sr_off_i2} , and the current of the gate signal is calculated based on the calculated turn-off current slew rate. Controls the gate current, which is the value. In the dv / dt calculation & control calculation section, the turn-off current slew rate is calculated by the following equation (4).

In the operation section following the dv / dt calculation & control calculation section, the gate current, which is the current value of the gate signal, is controlled based on the calculated turn-on current slew rate di _on / dt and turn-off current slew rate di _off / dt. ..

For example, when the absolute value of the turn- _on current slew rate dio / dt is low, the gate current of the gate signal, which is a positive voltage, is increased in the turn-on operation section 94 of the operation section to the drain source of the switching element 44U. Encourage the concentration of electrons. When the absolute value of the turn- _on current slew rate dio / dt is high, the gate current of the gate signal, which is a positive voltage, is reduced in the turn-on operation section 94 of the operation section to the drain source of the switching element 44U. Suppress the concentration of electrons.

For example, when the absolute value of the turn-off current slew rate di _off / dt is low, the gate current of the gate signal, which is a negative voltage, is increased in the turn-off operation section 96 of the operation section to attract the current to the drain source of the switching element 44U. Promotes the dispersion of the generated electrons. When the absolute value of the turn-off current slew rate di _off / dt is high, the gate current of the gate signal, which is a negative voltage, is reduced in the turn-off operation section 96 of the operation section to attract the current to the drain source of the switching element 44U. It suppresses the dispersion of the generated electrons.

FIG. 6 is an explanatory diagram showing the relationship between the voltage slew rate and the current slew rate and the influence on the gate current, and is a combination of FIGS. 4 and 5 described above in one figure. As shown in FIG. 6, the voltage waveform between the input / output terminals and the element current waveform have a complementary relationship in that when one increases, the other decreases, and when one increases, the other increases.

Further, in the operation section, the timing when the voltage between the input / output terminals starts to increase is earlier than the timing when the element current starts to decrease, and the timing when the element current decreased to the minimum value starts to increase again is the timing between the input / output terminals. It is earlier than the timing to start the decrease. Therefore, as shown in FIG. 6, the operation section is divided into four sections such as the first section 98, the second section 100, the third section 102, and the fourth section 104, and the turn-off voltage slew rate is set in the first section 98. , The turn-off current slew rate in the second section 100, the turn-on current slew rate in the third section 102, and the turn-on voltage slew rate in the fourth section 104 can be individually changed.

As described above, according to the present embodiment, the current slew rate and the voltage slew rate can be monitored while suppressing the processing load of the detection information.

In the present embodiment, one unit cycle is from when the gate signal is turned off to when it is turned on and immediately before it is turned off again or until when the gate signal is turned on and then turned off and immediately before it is turned on again. The cycle 1 is defined as the low threshold detection section, and the cycle following the low threshold detection section is defined as the high threshold detection section. Detection by the first threshold voltage V _th1 or the first threshold current I _th1 is performed in the low threshold detection section, and detection by the second threshold voltage V _th2 or the second threshold current I _th2 is performed in the high threshold detection section. It is possible to suppress the load of the gate drivers 20U to 22W related to the detection of changes in the control terminal voltage and the like used.

Further, by controlling the gate current based on the calculated turn-on voltage slew rate, turn-off voltage slew rate, turn-on current slew rate, and turn-off current slew rate, the generation of surge voltage and the like is suppressed, and the switching elements 42U to 44W are used. Switching loss can be reduced.

FIG. 7 is an explanatory diagram of general slew rate calculation in the present embodiment. In the case shown in FIG. 7, the low threshold value detection, which is the threshold value comparison based on the low threshold value shown in FIGS. 4 to 6, the high threshold value detection, which is the threshold value comparison based on the high threshold value, the control calculation for calculating the slew rate, and the calculated slew rate are used. In principle, it repeats a series of cycles consisting of gate current operations based on it. However, depending on the temperature of the inverter 10, the motor phase current, and the power supply voltage of the DC power supply 80, a series of cycles of low threshold detection, high threshold detection, control calculation and operation, or a low threshold included in such a series of cycles. The load on the gate drivers 20U to 22W may be reduced by interrupting any of the detection, the high threshold detection, the control calculation and the operation. Hereinafter, a modified example of the present embodiment will be described.

[First modification]
FIG. 8 is an explanatory diagram when the low threshold value detection is limited to the first time. The low threshold value detection is performed at least once while the motor 12 is being driven, and the result of the low threshold value detection is held in the RAM 30UC or the like which is the storage unit of the control unit 30U. After that, high threshold detection, control calculation and operation are performed as a series of cycles, and in the control calculation, the voltage slew rate or current is used by using the held low threshold detection result and the newly detected high threshold detection result. The slew rate is calculated, and in subsequent operations, the gate current is controlled based on the calculated voltage slew rate or current slew rate.

FIG. 9 is a flowchart showing an example of processing when the low threshold value detection shown in FIG. 8 is limited to the first time. In step 800, it is determined whether or not the low threshold value is detected for the first time, and if it is the first detection, the procedure is shifted to step 802, and if it is not the first detection, the procedure is shifted to step 806.

In step 802, low threshold detection using a low threshold is performed, and the detection result is retained. In step 804 and step 806, high threshold value detection using a high threshold value is performed.

In step 808, the voltage slew rate or the current slew rate is calculated using the retained low threshold detection detection result and the high threshold detection detection result detected in step 804 or 806. Then, in step 810, the gate current is controlled based on the calculated voltage slew rate or current slew rate, and the process is terminated.

In this modification, by limiting the low threshold detection to the first time, it is possible to simplify a series of processes related to the control of the gate current and reduce the load on the gate drivers 20U to 22W.

[Second modification]
FIG. 10 is a flowchart in the case where the slew rate is calculated and the gate current is controlled when a difference from the previous high threshold value detection occurs in the high threshold value detection. In this modification, when the voltage slew rate or the current slew rate is calculated in the control calculation section, the detection result of the high threshold value detection is held in the RAM 30UC or the like which is the storage unit of the control unit 30U, and then the low threshold value detection and the high threshold value are newly detected. When the difference between the newly performed high threshold value detection detection result and the retained high threshold value detection detection result is equal to or greater than a predetermined value, the newly detected low threshold value detection detection result and the newly detected detection result are performed. The gate current is controlled based on the voltage slew rate or the current slew rate calculated based on the detection result of the high threshold value detection. The predetermined value is a value to which a significant change is observed in the voltage slew rate or the current slew rate, and is specifically determined through experiments or the like.

FIG. 10 shows a process in which the detection result of high threshold value detection is held in advance. In step 900, low threshold detection using a low threshold is performed. In step 902, high threshold detection using a high threshold is performed.

In step 904, the detection result of the high threshold value detection detected in step 902 is compared with the detection result of the held high threshold value detection, and it is determined whether or not the difference between the two is equal to or greater than a predetermined value. In step 904, if the difference between the two is greater than or equal to the predetermined value, the procedure is shifted to step 906, and if the difference between the two is not greater than or equal to the predetermined value, the procedure is shifted to step 902 to perform high threshold detection.

In step 906, the voltage slew rate or the current slew rate is calculated using the detection result of the low threshold value detection detected in step 900 and the detection result of the high threshold value detection detected in step 902. Then, in step 908, the gate current is controlled based on the calculated voltage slew rate or current slew rate, and the process is terminated.

In this modification, the gate current is controlled by calculating the voltage slew rate or current slew rate and controlling the gate current when the detection result of the newly acquired high threshold detection is different from the previous value. The series of processes can be simplified and the load on the inverter 10 or the gate driver 20U to 22W can be reduced.

[Third variant]
FIG. 11 is an explanatory diagram of slew rate calculation by comparing four or more threshold values. In this modification, when detecting the voltage through rate, the difference between the adjacent threshold voltages at a plurality of different threshold voltages is changed from the timing when the gate signal changes from on to off or from off to on, and the voltage between the input / output terminals. A plurality of voltage through rates are calculated by dividing the voltage detected by the detection unit 24U by the difference in time until the voltage detected by the detection unit 24U reaches the threshold voltage related to the difference between the threshold voltages. Then, the gate current is controlled based on the rate of change of the calculated plurality of voltage slew rates in time series.

In the example shown in FIG. 11, four threshold voltages V _th1a , V _th2a , V _th3a , and V _th4a are set. Adjacent threshold voltage combinations are V _th1a and V _th2a , V _th2a and V _th3a , and V _th3a and V _th4a . In this modification, the time until the voltage detected by the input / output terminal voltage detection unit 24U reaches the threshold voltages V _th1a and V _th2a , _respectively , for the difference V _th2a -V _th1a between V th2a and V _th1a , T ₁ and T ₂ . The following initial slew rate is calculated by dividing by T ₂ -T ₁ , which is the difference between.

Further, in this modification, the time T ₂ until the voltage detected by the input / output terminal voltage detection unit 24U reaches the threshold voltages V _th2a and V _th3a , respectively, for the difference V _th3a -V _th2a between V _th3a and V _th2a . Divide by T ₃ − T ₂ , which is the difference of T ₃ , to calculate the following medium-term slew rate.

Further, in this modification, the time until the voltage detected by the input / output terminal voltage detection unit 24U reaches the threshold voltages V _th3a and V _{th4a ,} respectively, for the difference V _th4a -V _th3a between V _th4a and V _th3a . Divide by T ₄ -T ₃ , which is the difference of T ₄ , to calculate the following late slew rate.

In this modification, by calculating the rate of change of the initial slew rate, the middle slew rate, and the late slew rate calculated as described above, from the initial stage of the rising edge of the voltage waveform between the input / output terminals when the gate current is the same. You can grasp the change in the slew rate until the end. As an example, the initial slew rate, the medium-term slew rate, and the late slew rate change rate are calculated as, for example, the difference between the initial slew rate and the medium-term slew rate, and the difference between the medium-term slew rate and the late slew rate. Further, the rate of change of the slew rate may be grasped by calculating the difference between the initial slew rate and the medium-term slew rate and the difference between the medium-term slew rate and the late slew rate.

Although FIG. 11 shows a case where the voltage slew rate is calculated, the procedure is the same when calculating the current slew rate. When calculating the current slew rate, four threshold currents, It _th1a , It _th2a , _{It th3a} , and It th _4a , are set. Adjacent threshold current combinations are I _th1a and I _th2a , I _th2a and It _th3a , and It _{th 3a} and It _{th 4a} . In this modification, the difference between I _th2a and I _th1a is the difference _between T ₁ and T ₂ in which the current detected by the element current detection unit 26U reaches the threshold currents I _th1a and I _th2a , respectively _. Divide by a certain T ₂ -T ₁ to calculate the initial through rate.

Similarly, the difference between I _th3a and I _th2a is the difference _between T ₂ and T ₃ in which the current detected by the element current detection unit 26U reaches the threshold currents I _th2a and I _{th 3a ,} respectively. The medium-term through rate is calculated by dividing by T ₃ -T ₂ , and the currents detected by the element current detector 26U for the difference I _th4a -I _th3a between I _th4a and I _th3a are the threshold currents I _th3a and I _th4a , respectively. The late through rate is calculated by dividing by T ₄ -T ₃ , which is the difference between T ₃ and T ₄ and the time until it is reached.

Then, the calculated initial slew rate, medium-term slew rate, and late-stage slew rate change rate are calculated in the same manner as in the case of the voltage slew rate.

[Fourth variant]
FIG. 12 is an explanatory diagram when each of low threshold value detection and high threshold value detection is performed when the motor phase currents are substantially the same. As described above, in the actual motor rotation control, a three-phase AC-like voltage is generated and applied to the coils of each phase of the motor 12 by PWM control that turns each of the switching elements 42U to 44W on and off in small steps. , The motor phase current supplied to the motor 12 changes in a substantially sinusoidal shape as shown in the middle stage of FIG. When the motor phase current is different, the V _ds waveform, which is the waveform of the voltage between the input / output terminals, is also different. The V _ds waveform at the timing when the motor phase current is high tends to be steep as shown in the upper part of FIG. Further, as shown in the lower part of FIG. 12, the V _ds waveform at the timing when the motor phase current is low tends to be gentler than the V _ds waveform at the timing when the motor phase current is high.

As shown in FIG. 12, when the motor phase currents are different, the V _ds waveforms are different. In this modification, the voltage slew rate is calculated by performing low threshold value detection and high threshold value detection at the timing when the motor phase currents appearing in each electric angle cycle are substantially the same. Since the V _ds waveform becomes almost the same at the timing when the motor phase currents are substantially the same, the voltage slew rate can be calculated accurately, and as a result, the gate current can be controlled with high accuracy. As an example, the timing at which the motor phase currents are substantially the same is detected as the same timing within the electrical angular cycle by counting the control clock of the control unit 30U.

Further, the load on the gate drivers 20U to 22W can be reduced by detecting the timing at which the motor phase currents are substantially the same for each electric angle cycle and performing low threshold value detection and high threshold value detection.

In this modification, the case where the voltage slew rate is calculated is shown, but the case where the current slew rate is calculated can also be calculated by the same procedure.

[Fifth variant]
FIG. 13 is an explanatory diagram when each of low threshold value detection and high threshold value detection is performed when the motor phase currents are substantially the same in the same electric angle cycle. As for the motor phase current that changes in a substantially sinusoidal shape, the same value appears twice in the same electric angle period unless it is a maximum value or a minimum value. In this modification, the voltage slew rate is calculated by performing low threshold value detection and high threshold value detection at substantially the same timing of the motor phase currents that appear twice in the same electric angle cycle. As described above, since the V _ds waveforms are almost the same at the timing when the motor phase currents are substantially the same, the voltage slew rate can be calculated accurately, and as a result, the gate current can be controlled with high accuracy.

As an example, the timing at which the motor phase currents are substantially the same within the same electric angle cycle is detected by counting the control clock of the control unit 30U within the electric angle cycle.

Further, since the timing at which the motor phase currents are substantially the same within the same electric angle cycle is longer than the switching cycle of the switching elements 42U to 44W in PWM control, the frequency of low threshold value detection and high threshold value detection per unit time is increased. It can be suppressed, and as a result, the load of the gate driver 20U to 22W can be reduced.

In this modification, the case where the voltage slew rate is calculated is shown, but the case where the current slew rate is calculated can also be calculated by the same procedure.

[Sixth variant]
FIG. 14 is an explanatory diagram when a thinning section is provided between the low threshold value detection and the high threshold value detection. In the present embodiment, as shown in FIG. 7, a control calculation for calculating a low threshold detection, a high threshold detection, a voltage slew rate or a current slew rate, and a gate for each switching of the switching elements 42U to 44W by PWM control. The current is operated, but the load of the gate driver 20U to 22W becomes a problem in such an operation.

In this modification, as shown in FIG. 14, after the low threshold value detection, a thinning section in which the high threshold value detection is not performed is provided, and the high threshold value detection is performed following the thinning section. The thinning section is performed, for example, by the control unit 30U outputting an operation stop signal to each of the input / output terminal voltage detection unit 24U and the element current detection unit 26U. After the high threshold value is detected, the control calculation is performed via the thinning section, and after the control calculation, the operation is performed via the thinning section. Then, after the operation, the low threshold value is detected again through the thinning section. The thinning section is a section including at least one switching, and may extend to a plurality of switchings.

As shown in FIG. 14, the load of the gate drivers 20U to 22W can be reduced by providing a thinning section in which detection, calculation, and operation are not performed.

[7th variant]
FIG. 15 is an explanatory diagram when a thinning section is provided in which threshold value detection is not performed after controlling the gate current. As shown in FIG. 15, the load on the gate drivers 20U to 22W can be reduced by providing a thinning section in which detection, calculation, and operation are not performed during at least one switching after the operation of the gate current. can.

[Second Embodiment]
FIG. 16 is a block diagram showing an example of the configuration of the gate driver 122U provided at the gate of the switching element 44U according to the present embodiment. The gate driver 122U according to the present embodiment is different from the gate driver 22U according to the first embodiment in that the slew rate is detected based on the control terminal voltage of the switching element 44U. Further, as the gate driver according to the present embodiment, there are other gate drivers provided in each of the switching elements 42U to 44W, such as the gate driver 120U. However, the gate driver 122U will be described as a typical example, and other gate drivers will be described. The description of the gate driver will be omitted.

As shown in FIG. 16, the gate driver 122U according to the present embodiment has a control terminal voltage detection unit 124U and a node that detect the control terminal voltage (gate-source voltage V _gs ) of the switching element 44U in association with time information. The load current detection unit 132U, which is provided between the _46U and the motor 12 and detects the load current IL in a state where the element current (drain current Id) is constant at a high level, and the power supply voltage VH of the DC power supply 80 are detected. The detection processing unit 128U includes the power supply voltage detection unit 134U, and the detection processing unit 128U can process the detection signals of the control terminal voltage detection unit 124U, the load current detection unit 132U, and the power supply voltage detection unit 134U by the control unit 130U described later. First, the control unit 130U performs a control calculation of the gate signal applied to the gate of the switching element 44U based on the through rate target value input from the upper control device and the output of the detection processing unit 128U after converting to a signal. Although it is different from the embodiment of the above, the other configurations are designated by the same reference numerals as those of the first embodiment and detailed description thereof will be omitted. Since the configuration of the control unit 130U is substantially the same as that of the control unit 30U shown in FIG. 3, detailed description thereof will be omitted. Further, the control terminal voltage detection unit 124U detects time information using, for example, the control clock of the control unit 130U.

As an example, the load current detection unit 132U may detect the current value based on the potential difference between both ends of the shunt resistance, or may detect the current value based on the induced current generated by the energization between the node 46U and the motor 12. It may be calculated. In the present embodiment, the element current detection unit 26U of the first embodiment may be provided instead of the load current detection unit 132U. This is because the load current IL is the element current detected when the switching element 44U is turned on. Further, since the load current IL is a value peculiar to the switching element 44U, it may be a constant peculiar to the switching element 44U instead of the value detected by the load current detecting unit 132U.

For example, when the detection signals of the control terminal voltage detection unit 124U, the load current detection unit 132U, and the power supply voltage detection unit 134U are analog signals, the detection processing unit 128U converts them into digital signals that can be processed by the control unit 130U. It is a circuit including a kind of A / D converter.

Instead of the power supply voltage detection unit 134U, the input / output terminal voltage detection unit 124U of the first embodiment may be provided. This is because the power supply voltage VH is the voltage between the input / output terminals detected when the switching element 44U is turned off. Further, since the power supply voltage VH is a value according to the specifications of the DC power supply 80, when the output of the DC power supply 80 is stable, the nominal voltage of the DC power supply 80 is used instead of the value detected by the power supply voltage detection unit 134U or the like. The power supply voltage may be VH.

FIG. 17 is an explanatory diagram showing an outline of slew rate detection by the control terminal voltage. FIG. 17 shows changes in the gate signal, the control terminal voltage, the voltage between the input / output terminals, and the element current in time series in the same manner as in FIG. 19 described above. In the present embodiment, the slew rate is detected by utilizing the appearance of the following information (1) and (2) in the control terminal voltage.

(1) The drain current transition period T1 from when the control terminal voltage reaches the gate threshold voltage to when the mirror voltage reaches the mirror voltage and becomes constant.
(2) Drain-source voltage transition period T2 corresponding to the mirror period.

In the present embodiment, the threshold values of the three control terminal voltages of the first cycle threshold value V _th1c , the second cycle threshold value V _th2c , and the third cycle threshold value V _th3c are set. The first cycle threshold value V _th1c is the gate threshold voltage V _th itself. The second cycle threshold V _th2c is close to the mirror voltage V _m but smaller than the mirror voltage V _m , and the third cycle threshold V _th3c is close to the mirror voltage V _m but larger than the mirror voltage V _m . be.

The mirror voltage is calculated by the following formula. In the following equation, V _th is the gate threshold voltage, IL is the load current at which the element current is constant at a high level, and gm is the mutual conductance (change in the element current with respect to the change in the control terminal voltage).
V _m = V _th + IL / gm

In this embodiment, the load current IL is divided by the drain current transition period T1 to derive the current slew rate di / dt, and the power supply voltage VH is divided by the drain-source voltage transition period T2 to obtain the voltage slew rate dv / dt. Derived.

As described with reference to FIG. 19, when the gate signal is turned off, the voltage between the input / output terminals increases and the element current decreases, which is a turn-off period. The turn-off period is also the drain current transition as in the turn-on period. The current slew rate di / dt can be derived from the period T1 and the load current IL, and the voltage slew rate dv / dt can be derived from the drain-source voltage transition period T2 and the power supply voltage VH.

FIG. 17 shows an example in which three control terminal voltage thresholds of the first cycle threshold value V _th1c , the second cycle threshold value V _th2c , and the third cycle threshold value V _th3c are applied when the gate signal of 1 is turned on or off. .. However, in such a case, it is necessary to perform detection using the three threshold values in a short time, and the load of the gate drivers 20U to 22W may increase. Therefore, in this embodiment, FIG. 18 will be used later. As described above, the detection using the respective threshold values of the first cycle threshold value V _th1c , the second cycle threshold value V _th2c , and the third cycle threshold value V _th3c is performed when the gate signal is turned on or off at different timings.

FIG. 18 is an explanatory diagram showing an example of calculation of voltage slew rate and current slew rate by control terminal voltage and control of gate current. In the present embodiment, one unit cycle is from when the gate signal is turned off to when it is turned on and immediately before it is turned off again. The cycle 1 is defined as the first threshold value detection section, the cycle following the first threshold value detection section is defined as the second threshold value detection section, and the cycle following the second threshold value detection section is defined as the third threshold value detection section.

In the first threshold value detection section, the time T _{sr_off_1} from when the gate signal is turned off until the control terminal voltage reaches the threshold value V _th1c in the first cycle is detected, and in the first threshold value detection section, the gate signal is turned on. The time T _{sr_on_1} until the control terminal voltage reaches the threshold value V _th1c in the first cycle is detected.

In the second threshold value detection section, the time T _{sr_off_2} from when the gate signal is turned off until the control terminal voltage reaches the second cycle threshold value V _th2c is detected, and in the second threshold value detection section, the gate signal is turned on. Detects the time T _{sr_on_2} from when the voltage becomes to the time when the control terminal voltage reaches the threshold value V _th2c in the second cycle.

In the third threshold value detection section, the time T _{sr_off_3} from when the gate signal is turned off until the control terminal voltage reaches the third cycle threshold value V _th3c is detected, and in the third threshold value detection section, the gate signal is turned on. The time T _{sr_on_3} until the control terminal voltage reaches the threshold value V _th3c in the third cycle is detected.

In the slew rate calculation & control calculation section, the time detected in each of the first threshold detection section, the second threshold detection section, and the third threshold detection section, the power supply voltage VH detected by the power supply voltage detection unit 134U, and the load current. The turn-off voltage slew rate, turn-on voltage slew rate, turn-off current slew rate, and turn-on current slew rate are calculated using the load current IL detected by the detection unit 132U.

The turn-off voltage slew rate is calculated by the following equation (5). The denominator of the equation (5) corresponds to the above-mentioned drain-source voltage transition period T2.

The turn-on voltage slew rate is calculated by the following equation (6). The denominator of the equation (6) corresponds to the above-mentioned drain-source voltage transition period T2, but since the power supply voltage VH is a positive value and the turn-on voltage slew rate is a negative value, the time T _{sr_on_2} to the time T The denominator is set to a negative value by subtracting _{sr_on_3} .

The turn-off current slew rate is calculated by the following equation (7). The denominator of the equation (7) corresponds to the above-mentioned drain current transition period T1, but since the load current IL is a positive value and the turn-off current slew rate is a negative value, the time T _{sr_off_2} is changed to the time T _{sr_off_1} . By subtracting, the denominator is set to a negative value.

The turn-on current slew rate is calculated by the following equation (8). The denominator of the equation (8) corresponds to the above-mentioned drain current transition period T1.

In the operation section, the gate current, which is the current value of the gate signal, is controlled based on the calculated turn-off voltage slew rate, turn-on voltage slew rate, turn-off current slew rate, and turn-on current slew rate. Since the mode of controlling the gate current is the same as that of the first embodiment, detailed description thereof will be omitted.

As described above, according to the present embodiment, the turn-off voltage slew rate, turn-on voltage slew rate, and turn-off current slew rate are based on the power supply voltage VH and the load current IL that can be stably detected with constant detection values. And each of the turn-on current slew rate can be calculated.

The respective times involved in calculating the turn-off voltage slew rate, turn-on voltage slew rate, turn-off current slew rate, and turn-on current slew rate are of the first cycle threshold V _th1c , the second cycle threshold V _th2c , and the third cycle threshold V _th3c . It is detected by applying the thresholds of the three control terminal voltages. In the present embodiment, one unit cycle is from when the gate signal is turned off to when it is turned on and immediately before it is turned off again. The cycle 1 is defined as the first threshold value detection section, the cycle following the first threshold value detection section is defined as the second threshold value detection section, and the cycle following the second threshold value detection section is defined as the third threshold value detection section. Then, the timing for detecting the change in the control terminal voltage using the first cycle threshold value V _th1c is set as the first threshold value detection section, and the timing for detecting the change in the control terminal voltage using the second cycle threshold value V _th2c is set as the second threshold value. By setting the detection section and the timing for detecting the change in the control terminal voltage using the third cycle threshold value V _th3c as the third threshold value detection section, the gate driver 20U to detect the change in the control terminal voltage using the threshold value. The load of 22 W can be suppressed.

10 Inverter, 12 motor, 22U gate driver, 24U input / output terminal voltage detector, 26U element current detector, 30U control unit, 32U operation unit, 32UF, 32UO variable resistor, 44U switching element, 90 turn-off operation section, 92 Turn-on operation section, 94 Turn-on operation section, 96 Turn-off operation section, 122U gate driver, 124U control terminal voltage detection unit, 124U input / output terminal voltage detection unit, 130U control unit, 132U load current detection unit, 134U power supply Voltage detector, _Id drain current, I _th1 1st threshold current, I _th2 2nd threshold current, I _th1a It _th2a , _{It 3a} , I _th4a threshold current, IL load current, T1 drain current transition period, between T2 drain source Voltage transition period, T ₁ , T ₂ , T ₃ , T ₄ , T _{sr_off_1} , T _{sr_off_2} , T _{sr_off_3} , T _{sr_on_1} , T _{sr_on_2} , T _{sr_on_3 ,} T _{sr_off_v1 , T sr_off_v1 sr_off_i2} , T _{sr_on_i1} , T _{sr_on_i2} time, V _ds drain source voltage, V _gs gate source voltage, V _m mirror voltage, V _th gate threshold voltage, V _th1 first threshold voltage, V _th2 second threshold voltage, V _th1a , V _th2a , V _th3a , V _th4a threshold voltage, V _th1c 1st cycle threshold, V _th2c 2nd cycle threshold, V _th3c 3rd cycle threshold, VH power supply voltage

Claims (17)

A voltage time series indicating a time change of the voltage of the input / output terminal of a switching element (44U) having a control terminal and an input / output terminal and switching between the input / output terminals according to an electric signal applied to the control terminal. A voltage detector (24U) that detects information, and
A current detection unit (26U) for detecting current time series information indicating a time change of the element current of the switching element (44U), and a current detection unit (26U).
The first voltage time series information detected by the voltage detection unit (24U) in the first switching of the switching element, and the second voltage detection unit detected in the second switching different from the first switching. The voltage slew rate derived based on the voltage time series information and indicating the voltage change rate between the input / output terminals and the first current time series information detected by the current detection unit (26U) in the first switching. , And the current slew rate, which is derived based on the second current time series information detected by the current detection unit (26U) in the second switching, and indicates the rate of change of the element current. The control unit (30U) that controls the current value of the electric signal and
Switching element drive circuit including. The control unit (30U) is the time when the voltage difference between the first threshold voltage and the second threshold voltage larger than the first threshold voltage is extracted from the first voltage time series information, and is the input / output. The voltage of the terminal is the first voltage time from the timing when the electric signal changes to the first threshold voltage, and the time extracted from the second voltage time series information, and the voltage of the input / output terminal is The switching element drive circuit according to claim 1, wherein the voltage through rate is calculated by dividing by the time difference from the second voltage time from the timing at which the electric signal changes to the time when the second threshold voltage is reached. The control unit (30U) is the time obtained by extracting the current difference between the first threshold current and the second threshold current larger than the first threshold current from the first current time series information, and is the element current. Is the first current time from the timing at which the electric signal changes to the time when the first threshold current is reached, and the time extracted from the second current time series information, and the element current changes the electric signal. The switching element drive circuit according to claim 1, wherein the current slew rate is calculated by dividing by the time difference from the second current time until the second threshold current is reached. After holding the first voltage time in the storage unit (30UC), the control unit (30U) detects the second voltage time a plurality of times, and each of the second voltage times detected a plurality of times and the storage unit. The switching element drive circuit according to claim 2, wherein the plurality of voltage slew rates are calculated using the first voltage time held at (30 UC). After holding the first current time in the storage unit (30UC), the control unit (30U) detects the second current time a plurality of times, and each of the second current times detected a plurality of times and the storage unit. The switching element drive circuit according to claim 3, wherein the plurality of current slew rates are calculated using the first current time held at (30 UC). The control unit (30U) holds the second voltage time related to the calculation of the voltage through rate in the storage unit (30UC), and then newly detects the first voltage time and the second voltage time, and newly detects the first voltage time and the second voltage time. When the difference between the generated second voltage time and the second voltage time held in the storage unit (30UC) is equal to or greater than a predetermined value, the voltage through calculated by the newly detected first voltage time and the second voltage time The switching element drive circuit according to claim 2, wherein the current value of the electric signal is controlled based on the rate. The control unit (30U) holds the second current time related to the calculation of the current slew rate in the storage unit (30UC), and then newly detects the first current time and the second current time, and newly detects the first current time and the second current time. When the difference between the generated second current time and the second current time held in the storage unit (30UC) is equal to or greater than a predetermined value, the current through calculated by the newly detected first current time and the second current time. The switching element drive circuit according to claim 3, wherein the current value of the electric signal is controlled based on the rate. The control unit (30U) corresponds to a plurality of different threshold voltages, and from each of the plurality of voltage time series information detected in each different switching of the switching element, the plurality of said from the timing when the electric signal changes. The time until each threshold voltage is reached is extracted, and the difference between the threshold voltages having adjacent values is the difference between the timings at which the electric signal changes and the time until the value reaches the adjacent threshold voltage. The switching element drive circuit according to claim 1, wherein a plurality of voltage slew rates are calculated by dividing by, and the current value of the electric signal is controlled based on the rate of change of the plurality of voltage slew rates in a time series. The control unit (30U) corresponds to a plurality of different threshold currents, and from each of the plurality of current time-series information detected in each different switching of the switching element, the plurality of currents are changed from the timing at which the electric signal is changed. The time until each threshold current is reached is extracted, and the difference between the threshold currents whose values are adjacent to each other is the difference between the timings when the electric signal changes and the time until the values reach the adjacent threshold currents. The switching element drive circuit according to claim 1, wherein a plurality of current slew rates are calculated by dividing by, and the current value of the electric signal is controlled based on the rate of change of the plurality of current slew rates in a time series. The switching element drive circuit according to any one of claims 1 to 3, wherein the second switching is switching following the first switching. In the second switching, the current supplied from the switching element (44U) to the power load (12) is supplied from the switching element (44U) to the power load (12) at the time of the first switching. The switching element drive circuit according to any one of claims 1 to 3, which is switching at a timing that appears at every electric angle cycle that is substantially the same as the current. In the second switching, the current supplied from the switching element (44U) to the power load (12) in the same electric angular cycle is the power load from the switching element (44U) at the time of the first switching. The switching element drive circuit according to any one of claims 1 to 3, which is switching at a timing substantially the same as the current supplied to (12). Any one of claims 1 to 3 in which a thinning section for stopping detection by each of the voltage detection unit (24U) and the current detection unit (26U) is provided for at least one switching after the first switching. The switching element drive circuit according to. After calculating the voltage slew rate and the current slew rate, detection by each of the voltage detection unit (24U) and the current detection unit (26U) and calculation of the voltage slew rate and the current slew rate by the control unit (30U). The switching element drive circuit according to any one of claims 1 to 3, wherein a slewing section for stopping and is provided for at least one switching. A control terminal voltage that indicates a time change of the voltage of the control terminal of a switching element (44U) having a control terminal and an input / output terminal and switching between the input / output terminals according to an electric signal applied to the control terminal. Control terminal voltage detector (124U) that detects series information,
The voltage of the control terminal extracted from the control terminal voltage time series information is derived based on the drain current transition period from the gate threshold voltage of the switching element to reaching the mirror voltage, and the change in the element current of the switching element. A current slew rate indicating the rate and a voltage derived from the control terminal voltage extracted from the control terminal voltage time series information based on the mirror period in which the mirror voltage becomes the mirror voltage and indicating the voltage change rate between the input / output terminals. A control unit (130U) that controls the current value of the electric signal based on either one of the through rate and the control unit (130U).
Switching element drive circuit including. The control unit (130U) has a first time from the first timing at which the voltage of the control terminal changes from on to off or from off to on to reach the gate threshold voltage, and the first. The voltage of the control terminal is larger than the gate threshold voltage and smaller than the mirror voltage from the second timing when the electric signal changes from on to off or from off to on after the timing of, and is close to the mirror voltage. The difference between the second time until the control terminal threshold voltage is reached and the drain current transition period is used as the drain current transition period, and the load current of the switching element (44U) is divided by the drain current transition period to calculate the current through rate. The switching element drive circuit according to claim 15. In the control unit (130U), the voltage of the control terminal is the mirror voltage from the second time and the third timing when the electric signal changes from on to off or from off to on after the second timing. The voltage slew rate is calculated by dividing the power supply voltage by the mirror period, where the difference from the third time until the other control terminal threshold voltage larger than and close to the mirror voltage is reached is the mirror period. 16. The switching element drive circuit according to claim 16.

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