JP7019995B2 - Semiconductor devices and their manufacturing methods - Google Patents

Description

The present invention relates to a semiconductor device made of a wide bandgap semiconductor such as silicon carbide (SiC) and a method for manufacturing the same.

In general, the energy loss during operation of a MOSFET is mainly dominated by the loss due to drift resistance, channel resistance and contact resistance. Of these, the contact resistance needs to be sufficiently lower than the drift resistance and channel resistance. Even in the case of manufacturing a semiconductor device made of SiC, the formation of ohmic contact between the electrode extraction region made of SiC and the metal electrode is one of the technical issues.

Conventionally, as a method for forming an ohmic contact between an electrode extraction region made of SiC and a metal electrode, a structure in which a graphene layer is arranged between the electrode extraction region and the metal electrode has been proposed (see Patent Document 1).

In the structure described in Patent Document 1, although ohmic contact between the electrode extraction region made of SiC and the metal electrode can be obtained, a method for further reducing the contact resistance is required.

International Publication No. 2016/002386

In view of the above problems, it is an object of the present invention to provide a semiconductor device capable of forming a low resistance ohmic contact between an electrode extraction region made of a wide bandgap semiconductor and a metal electrode, and a method for manufacturing the same.

One aspect of the present invention includes (a) an electrode extraction region made of a wide bandgap semiconductor provided in a part of the active region, (b) an intercalation layer arranged on the upper surface of the electrode extraction region, and (c). ) A graphene layer arranged on the upper surface of the intercalation layer and (d) a metal electrode arranged on the upper surface of the graphene layer, and the intercalation layer provides an interfacial dipole between the electrode extraction region and the graphene layer. The gist is a semiconductor device characterized by forming.

Another aspect of the present invention includes (a) a semiconductor layer made of a wideband gap semiconductor, and (b) a first conductive type first electrode extraction region made of a wideband gap semiconductor provided above the semiconductor layer. (C) An intercalation layer arranged on the upper surface of the first electrode extraction region, (d) a graphene layer arranged on the upper surface of the intercalation layer, and (e) a first electrode extraction region on the upper part of the semiconductor layer. It is provided with a second conductive type second electrode extraction region made of a wide band gap semiconductor provided in contact with the (f) graphene layer and a first main electrode arranged on the upper surface of the second electrode extraction region. The gist of the present invention is a semiconductor device characterized in that the curation layer forms an interfacial dipole between the first electrode extraction region and the graphene layer.

Other embodiments of the present invention include (a) a step of forming a graphene layer on the upper surface of an electrode extraction region made of a wide bandgap semiconductor provided in a part of an active region, and (b) an interposition on the upper surface of the graphene layer. By depositing the atoms to form the curation layer and (c) heat treatment and inserting the deposited atoms into the interface between the graphene layer and the graphene extraction region, between the electrode extraction region and the graphene layer. The gist of the present invention is a method for manufacturing a semiconductor device, which comprises a step of forming an intercalation layer for forming an interfacial dipole and a step of (d) forming a metal electrode on the upper surface of the graphene layer.

INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a semiconductor device capable of forming a low resistance ohmic contact between an electrode extraction region made of a wide bandgap semiconductor and a metal electrode, and a method for manufacturing the same.

It is sectional drawing of the main part which shows an example of the semiconductor device which concerns on 1st Embodiment of this invention. It is a schematic diagram for demonstrating the hypothesis of the contact formation of the semiconductor device which concerns on 1st Embodiment. It is a process sectional view which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a process cross-sectional view following FIG. 3 which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a process cross-sectional view following FIG. 4 which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. FIG. 6A is a diffraction image of low-energy electron diffraction (LEED) during formation of the graphene layer of the second embodiment of the first embodiment, and FIG. 6B corresponds to FIG. 6A. It is a schematic cross-sectional view. FIG. 7 (a) is a diffraction image of LEED after depositing platinum (Pt) of the second embodiment of the first embodiment, and FIG. 7 (b) is a schematic corresponding to FIG. 7 (a). It is a sectional view. 8 (a) is a diffraction image of LEED after 1000 ° C. annealing of the second embodiment of the first embodiment, and FIG. 8 (b) is a schematic cross-sectional view corresponding to FIG. 8 (a). be. 9 (a) is a diffraction image of LEED after 1200 ° C. annealing of the second embodiment of the first embodiment, and FIG. 9 (b) is a schematic cross-sectional view corresponding to FIG. 9 (a). be. It is sectional drawing which shows an example of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a process sectional view which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a process cross-sectional view following FIG. 11 which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a process cross-sectional view following FIG. 12 which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a process cross-sectional view following FIG. 13 which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a process cross-sectional view following FIG. 14 which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a process cross-sectional view following FIG. 15 which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing of the main part which shows an example of the semiconductor device which concerns on other embodiment of this invention. It is sectional drawing which shows the other example of the semiconductor device which concerns on other embodiment of this invention.

Hereinafter, the first and second embodiments of the present invention will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.

As used herein, the "first main electrode region" means a semiconductor region that is either a source region or a drain region in a field effect transistor (FET) or a static induction transistor (SIT). In an insulated gate bipolar transistor (IGBT), the semiconductor region, which is either the emitter region or the collector region, is the semiconductor region, and in the static induction thyristor (SI thyristor) or the gate turn-off thyristor (GTO), either the anode region or the cathode region. It means a semiconductor region on one side. The "second main electrode region" is a semiconductor region that is either a source region or a drain region that does not become the first main electrode region in FET or SIT, and is the first main electrode region in IGBT. In SI thyristors and GTOs, it means a region that is either an anode region or a cathode region that is not the first main electrode region. That is, if the "first main electrode region" is the source region, the "second main electrode region" means the drain region. When the "first main electrode region" is the emitter region, the "second main electrode region" means the collector region. When the "first main electrode region" is the anode region, the "second main electrode region" means the cathode region.

In the present specification, the case where the first conductive type is n type and the second conductive type is p type will be described schematically, but the conductive type is selected in the opposite relationship, and the first conductive type is p type and the first. 2 The conductive type may be n type. Further, in the present specification and the attached drawings, "+" and "-" added with superscripts to "n" and "p" are compared with the semiconductor region in which "+" and "-" are not added. This means that the semiconductor regions have relatively high or low impurity densities, respectively. Further, in the present specification, the member or region to which the "first conductive type" and the "second conductive type" are limited means a member or region made of a semiconductor material without any particular limitation. That is technically and logically self-evident. Further, in the present specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after that, and a negative index is represented by adding "-" in front of the index.

In the following description, the definitions of "upper" and "lower" such as "upper surface" and "lower surface" are merely representational problems on the illustrated cross-sectional view, and for example, the orientation of the semiconductor device may be changed by 90 ° for observation. For example, the names of "upper" and "lower" become "left" and "right", and it goes without saying that the relationship between the names of "upper" and "lower" is reversed when observed by changing 180 °.

(First Embodiment)
<Structure of semiconductor device made of SiC>
As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention has an electrode extraction region 1 made of p ⁺ type SiC provided in a part of the active region and an upper surface of the electrode extraction region 1. It includes an arranged intercalation layer 2, a graphene layer 3 arranged on the upper surface of the intercalation layer 2, and a metal electrode 4 arranged on the upper surface of the graphene layer 3.

The electrode extraction region 1 may be, for example, a semiconductor substrate (SiC wafer) itself made of p-type or p ⁺ -type SiC, or at least a part of a p-type or p ⁺ -type epitaxial growth layer epitaxially grown on the SiC wafer. May be. Alternatively, it may be a contact region of at least a part of a p-type or p ⁺ -type semiconductor region provided by adding a p-type impurity to the upper part of the SiC wafer or the epitaxial growth layer. Further, in a semiconductor region such as a p-type or p ⁺ -type contact region provided by adding a p-type impurity to the upper part of an n-well provided by adding an n-type impurity to the upper part of a SiC wafer or an epitaxial growth layer. There may be. The carrier density of the electrode extraction region 1 is, for example, about 1 × 10 ¹⁶ / cm ³ or more.

The electrode extraction region 1 made of SiC may be limited to any of six-layer periodic hexagonal crystal (6H-SiC), four-layer periodic hexagonal crystal (4H-SiC), and three-layer periodic cubic crystal (3C-SiC). do not have. The surface of the electrode extraction region 1 is surface-flattened to the extent that, for example, atomic-level flatness can be obtained. The crystal plane orientation of the surface of the electrode extraction region 1 in contact with the intercalation layer 2 is, for example, 6H-, 4H-SiC (0001) plane (Si plane), (000-1) plane (C plane), (11-). 20) It may be a surface. The (1-10) plane of 3C-SiC and the (11-20) plane of hexagonal crystals are equivalent planes.

The intercalation layer 2 forms an interfacial dipole (interface dipole) between the electrode extraction region 1 and the graphene layer 3, so that the potential difference (Schottky barrier) generated at the interface between the electrode extraction region 1 and the metal electrode 4 is formed. Height) can be reduced. The thickness of the intercalation layer 2 may be the thickness of one atomic layer constituting the intercalation layer 2, or may be the thickness of two or more atomic layers. Alternatively, the intercalation layer 2 may have atoms sparsely arranged with a thickness of an adsorption layer having less than one atomic layer constituting the intercalation layer 2. However, the intercalation layer 2 shall be at the atomic layer level of 3 or less layers constituting the intercalation layer 2 so that an interfacial dipole can be easily formed between the electrode extraction region 1 and the graphene layer 3. Is preferable.

The material constituting the intercalation layer 2 is at least one of a group 13 (group III) element, a metal having a larger absolute value of work function than graphene, and a rare earth element that becomes a trivalent cation. One can be adopted. Group 13 elements include boron (B) and any earth metal such as aluminum (Al), gallium (Ga), indium (In) or thallium (Tl) or one or more of these earth metals. Selected from a group of alloys.

For a metal having an absolute value of work function larger than that of graphene, it is preferable that the absolute value of the work function is 5.0 eV or more. Metals with a higher work function absolute value than graphene are platinum (Pt), gold (Au), ruthenium (Rb), ruthenium (Ru), rhodium (Rh), palladium (Pd), renium (Re), and iridium ( It is selected from the group consisting of Ir) or an alloy containing one or more of these metals.

Examples of rare earth elements include scandium (Sc), yttrium (Y), and lanthanoids (excluding radioactive elements). Lantanoids (excluding radioactive elements) are lanthanum (La), cerium (Ce), placeodim (Pr), neodym (Nd), samarium (Sm), europium (Eu), gadrinium (Gd), terbium (Tb), dysprosium. It is selected from the group consisting of (Dy), holmium (Ho), erybium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

The graphene layer 3 is composed of graphene, which is a semiconductor having no band gap. Graphene is a sheet-like substance having a thickness equivalent to one C atom, in which carbon (C) atoms are bonded in a hexagonal lattice pattern. The graphene layer 3 may have a single-layer structure of one layer of graphene or a laminated structure of two or more layers of graphene. In order to easily insert the intercalation layer 2 between the electrode extraction region 1 and the graphene layer 3, the graphene layer 3 is preferably a single-layer structure or a laminated structure of graphene having three or less layers. Further, the graphene layer 3 is more preferably a single-layer structure because the single-layer structure has no gap and the Fermi level can be easily moved.

FIG. 1 illustrates a graphene layer 3 having a single-layer structure. Further, the plurality of C atoms constituting the graphene layer 3 are shown in a circular shape, and the covalent bonds of the C atoms are shown in a straight line connecting the adjacent circular portions. Further, in FIG. 1, in order to clarify the positions of the junctions of the intercalation layer 2, the graphene layer 3, and the metal electrode 4, the intercalation layer 2, the graphene layer 3, and the metal electrode 4 are schematically separated from each other. As shown, the intercalation layer 2, the graphene layer 3, and the metal electrode 4 are actually in contact with each other.

The metal electrode 4 forms ohmic contact with the electrode extraction region 1 via the intercalation layer 2 and the graphene layer 3. The metal electrode 4 may be a surface electrode constituting a general device structure. The metal electrode 4 may be, for example, a source electrode or a drain electrode of a MOSFET constituting an active region, or an emitter electrode or a collector electrode of an IGBT constituting the active region. Further, it may be a pn diode, a p-in diode or the like constituting an active region, or an anode electrode of a thyristor.

As the electrode material of the metal electrode 4, gold (Au), silver (Ag), platinum (Pt), titanium (Ti), nickel (Ni), iron (Fe), cobalt (Co), copper (Cu), and chromium ( Cr), Al, Pd, or an alloy containing one or more of these metals may be used. Further, the metal electrode 4 may be a laminated film formed by laminating a plurality of metal films made of any one of these metals and alloys in different combinations.

FIG. 2 shows a structure in which the structure shown in FIG. 1 is rotated 90 ° counterclockwise, and a band diagram corresponding to the structure. As shown in FIG. 2, the electron affinity of p ⁺ type 4H- _SiC constituting the electrode extraction region 1 is 3.6 eV, the work function of _graphene constituting the graphene layer 3 is 4.5 eV, and the metal electrode. The work function φ _Au of Au as an example of the metal constituting 4 is 5.1 eV. By inserting the graphene layer 3 at the interface between the electrode extraction region 1 and the metal electrode 4, the Schottky barrier φb becomes smaller due to the movement of the Fermi level of graphene, but the height is only the amount of movement of the Fermi level of graphene. Only happens. Therefore, the movement of the Fermi level is small in the p-type, and the contact resistance tends to be larger than that in the n-type. Therefore, in the semiconductor device according to the first embodiment, by arranging the intercalation layer 2 between the electrode extraction region 1 and the graphene layer 3, the charge balance is further changed to create the Schottky barrier φb. Make it smaller. That is, the contact resistance is reduced by intercalating the cations to form an interface dipole opposite to the n-type.

<Manufacturing method of semiconductor device made of SiC>
Next, an example of the method for manufacturing a semiconductor device according to the first embodiment will be described with reference to FIGS. 3 to 5, focusing on the intercalation layer 2, the graphene layer 3, and the metal electrode 4.

First, a semiconductor wafer (SiC wafer) made of p-type SiC having a diameter of 3 inches, which has been mirror-polished on both sides by chemical mechanical polishing (CMP), is prepared. The thickness of the SiC wafer may be, for example, 430 μm. The main surface of the SiC wafer may be, for example, a (0001) surface having an off angle of about 4 ° to 8 ° in the <11-20> direction.

Next, a p-type epitaxial layer is grown on the main surface of the SiC wafer by a chemical vapor deposition (CVD) method. The impurity density and thickness of this epitaxial layer may be, for example, 1 × 10 ¹⁹ / cm ³ and 10 μm, respectively. As a result, an epitaxial wafer formed by growing an epitaxial layer on the SiC wafer is formed. Next, an active region is built in the upper part of the epitaxial layer by a general method. However, here, a detailed description of the specific manufacturing process of the active region will be omitted. That is, in the following description, the electrode extraction region 1 may be a part of the active region provided in the epitaxial wafer, and depending on the structure of the semiconductor device, the semiconductor wafer itself may be the same as the case of the back surface of the semiconductor wafer. It can be the electrode extraction region 1.

Next, the upper surface of the electrode extraction region 1 is cleaned by UV ozone cleaning using ultraviolet rays (UV) and ozone ₍ O3), and the deposits on the upper surface of the electrode extraction region 1 are removed by organic cleaning treatment. Next, as shown in FIG. 4, a single graphene layer 3 is formed on the upper surface of the electrode extraction region 1 by heat treatment. For example, the electrode extraction region 1 may be heated to, for example, about 1200 ° C. or higher to desorb Si atoms from the SiC constituting the electrode extraction region 1 to form a graphene layer 3 composed of the remaining C atoms. Further, as a method for forming the graphene layer 3, a CVD method, a molecular beam epitaxy (MBE) method, a molecular layer epitaxy (MLE) method, formation by laser irradiation, or the like, or a graphene layer 3 formed in advance is used as an electrode extraction region. 1 The method of transferring onto the top may be used.

For example, when the method of heating the electrode extraction region 1 to form the graphene layer 3 is used, the semiconductor wafer having the electrode extraction region 1 is inserted into the reaction furnace (chamber) of the infrared condensing type ultra-high temperature heating device. .. Then, the inside of the reactor is evacuated to, for example, about 6.6 × 10 ^-1 Pa. For example, argon (Ar) gas is introduced into the reaction furnace until it reaches atmospheric pressure, and the upper surface of the electrode extraction region 1 is exposed to the Ar gas atmosphere by continuing to flow at a predetermined flow rate. Then, the temperature in the reaction furnace is heated from room temperature (for example, about 25 ° C.) to about 1650 ° C. at a heating rate of, for example, 20 ° C./min, and then the temperature is maintained for about 5 minutes. As a result, the graphene layer 3 having a single layer structure is formed on the upper surface of the electrode extraction region 1. When the graphene layer 3 has a laminated structure, after the temperature in the reaction furnace reaches about 1650 ° C., the maintenance time of the temperature may be further extended. Then, after the temperature in the reactor is lowered to room temperature, the semiconductor wafer in which the electrode extraction region 1 is formed is taken out from the reactor.

Next, either a group 13 element (group III element) constituting the intercalation layer 2, a metal having a larger absolute value of work function than graphene, or a rare earth element by a vacuum vapor deposition method or a sputtering method. Atoms are deposited on the upper surface of the graphene layer 3. Then, by heat treatment, as shown in FIG. 4, the deposited atoms are inserted (intercalated) into the interface between the graphene layer 3 and the electrode extraction region 1 to form the intercalation layer 2. The heat treatment conditions are appropriately selected according to the atoms constituting the intercalation layer 2. For example, the heat treatment conditions are 1000 ° C. in vacuum when the atom constituting the intercalation layer 2 is B, 1200 ° C. in an Ar gas atmosphere when Pt, and 600 ° C. in vacuum when Al. The thickness of the intercalation layer 2 can be controlled, for example, by adjusting the heat treatment conditions. For example, the thickness of the intercalation layer 2 can be increased by increasing the heating temperature.

Next, as shown in FIG. 1, a metal electrode 4 made of Au or the like is formed on the upper surface of the graphene layer 3 by a vacuum vapor deposition method, a sputtering method, an MBE method, or the like. When the electrode extraction region 1 is a part of the active region provided in the epitaxial wafer, the metal electrode 4 is patterned by a metallization step by a photolithography step. The semiconductor wafer for which the metallization step of the metal electrode 4 has been completed is then diced into a chip having a predetermined size such as a chip size of 10 mm to form a semiconductor chip, and a semiconductor device made of SiC is completed.

In the above-mentioned method for manufacturing a semiconductor device made of SiC, the process proceeds to the metallization step in a wafer state, and after the metallization step is completed, the semiconductor device is formed into a chip by dicing, but the procedure is not limited to this. Depending on the request of the manufacturing equipment, etc., the graphene layer 3, the intercalation layer 2, and the metal electrode 4 are divided into specific sizes in the stage before forming the graphene layer 3, the intercalation layer 2, and the metal electrode 4 in each electrode extraction region 1, and a small chamber is manufactured. It may be inserted inside the device.

According to the semiconductor device according to the first embodiment, by arranging the intercalation layer 2 between the electrode extraction region 1 and the graphene layer 3, the interface dipole between the electrode extraction region 1 and the graphene layer 3 is provided. Can be formed, and the potential difference (Schottky barrier height) generated at the interface between the electrode extraction region 1 and the metal electrode 4 can be reduced. As a result, low resistance ohmic contact between the electrode extraction region 1 and the metal electrode 4 can be formed with high reproducibility.

Although the case where the electrode extraction region 1 is p-type is illustrated in FIG. 1, the electrode extraction region 1 may be n-type. The electrode extraction region 1 may be a SiC wafer itself made of n-type or n ⁺ -type SiC, or may be at least a part of an n-type or n ⁺ -type epitaxial growth layer on the SiC wafer. Alternatively, it may be a contact region of at least a part of an n-type or n ⁺ -type semiconductor region provided on the upper part of the SiC wafer or the epitaxial growth layer. Further, it may be a p-well provided on the upper part of the SiC wafer or the epitaxial growth layer, an n-type or n ⁺ type contact region provided on the upper part of the p-base, or the like.

When the electrode extraction region 1 is n-type, at least one of a group 5 transition metal and a group 15 (group V) element can be adopted as a material constituting the intercalation layer 2. Group 5 transition metals are selected from the group consisting of tantalum (Ta), niobium (Nb), vanadium (V), or alloys containing one or more of these metals. Group 15 (Group V) elements are selected from the group consisting of phosphorus (P), arsenic (As) and antimony (Sb), bismuth (Bi) or alloys containing one or more of these metals. By adopting a group 5 transition metal or a group 15 (group V) element as a material constituting the intercalation layer 2, a dipole is formed between the n-type electrode extraction region 1 and the graphene layer 3. The potential difference (shotkey barrier height) generated at the interface between the electrode extraction region 1 and the metal electrode 4 can be reduced.

<First Example>
As the first embodiment of the first embodiment, a laminated structure of a p-type electrode extraction region 1, an intercalation layer 2, a graphene layer 3 and a metal electrode 4 was produced. The atoms constituting the intercalation layer 2 were changed with Al, B, and Pt to prepare three kinds of samples of Examples A to C. In each of Examples A to C, the impurity density of SiC was set to 1 × 10 ¹⁹ / cm ³ . As a comparative example, the same samples as in Examples A to C were prepared except that the intercalation layer 2 was not present. Table 1 shows the measurement results of the contact resistance values of Examples A to C and Comparative Examples.

As shown in Table 1, in any of Examples A to C, the contact resistance is 10 ^-4 Ω / cm ² or less, which is a practical requirement, and the contact resistance is 10 ^-2 Ω / cm ² units. It was confirmed that the contact resistance could be significantly reduced compared to the above.

<Second Example>
As a second embodiment of the first embodiment, after forming the graphene layer 3, Pt is deposited as an element constituting the intercalation layer 2, and the deposited Pt is intercalated by heat treatment. The surface of the sample was observed by linear diffraction (LEED). The formation conditions of the graphene layer 3 are as follows: using an n-type SiC substrate with 4 ° off, a pressure of 101.325 kPa (gas flow rate: 8.45 × 10 ^-3 Pa · m ³ / sec) and a heating temperature under an Ar atmosphere. The temperature was 1575 ° C., the heating rate was 100 ° C./min, and the heating time was 30 minutes. The deposition conditions for Pt were a flux of 7 nA and a deposition time of 30 minutes. The intercalation condition of Pt is that it is transported in-situ to an ultra-high temperature heating device, and heated at 101.325 kPa (gas flow rate: 8.45 × 10 ^-3 Pa · m ³ / sec) under an Ar atmosphere. The temperature was 1000 ° C. or 1200 ° C., the heating rate was 20 ° C./min, and the heating time was 60 minutes.

7 (a), 8 (a), 9 (a), and 10 (a) are diffraction images by LEED after graphene formation, Pt deposition, 1000 ° C annealing, and 1200 ° C annealing. 7 (b), FIG. 8 (b), FIG. 9 (b), and FIG. 10 (b) show schematic views of the corresponding structures, respectively. In FIG. 7A, the points (spots) indicating SiC are circled with a solid line, and the points indicating graphene are circled with a broken line. The small dots around each point indicate the buffer layer in which the graphene of the graphene layer 3 and the SiC of the electrode extraction region 1 are covalently bonded.

In FIG. 7A, a point indicating the buffer layer is observed, and it is considered that the buffer layer 3a in which the graphene of the graphene layer 3 and the SiC of the electrode extraction region 1 are bonded is formed as shown in FIG. 7B. .. Further, the points showing the buffer layer 3a were also observed in FIGS. 8 (a) and 9 (a), and as shown in FIGS. 8 (b) and 9 (b), Pt atoms 2a were deposited and the temperature was 1000 ° C. It is considered that the buffer layer 3a is maintained even after annealing. On the other hand, in FIG. 10A, the point indicating the buffer layer 3a disappears, and as shown in FIG. 10B, the Pt atom 2a is placed between the graphene layer 3 and the electrode extraction region 1 by annealing at 1200 ° C. It is considered that the covalent bond between graphene in the buffer layer 3a and SiC was broken.

(Second embodiment)
<Structure of semiconductor device made of SiC>
A MOSFET will be described as an example of the semiconductor device according to the second embodiment of the present invention. As shown in FIG. 10, the semiconductor device according to the second embodiment is selectively embedded in the semiconductor layer (drift layer) 10 made of the first conductive type (n ⁻ type) SiC and the upper part of the drift layer 10. The base region 11 of the second conductive type (p ⁺ type) and the first main electrode region (source region) 13a of the first conductive type (n ⁺ type) selectively embedded in the upper part of the base region 11 It is provided with 13b.

Gate electrodes 15a and 15b made of doped polysilicon or the like are arranged from above the base region 11 to above the drift layer 10 via the gate insulating film 14, respectively. The upper surface and the side surface of the gate electrodes 15a and 15b are covered with the interlayer insulating film 16.

A second conductive type (p ⁺ type) base contact region 12 having a higher impurity density than the base region 11 is embedded on the base region 11 so as to be in contact with the source regions 13a and 13b. A first main electrode (source electrode) 19 is arranged on the source regions 13a and 13b and the base contact region 12 so as to cover the interlayer insulating film 16. The source regions 13a and 13b and the base contact region 12 are electrode extraction regions and form ohmic contact with the source electrode 19.

An intercalation layer 17 and a graphene layer 18 are selectively arranged between the p ⁺ type base contact region 12 and the source electrode 19. That is, the structure of the p ⁺ type base contact region 12, the intercalation layer 17, the graphene layer 18, and the source electrode 19 shown in FIG. 10 is the electrode extraction region 1 of the semiconductor device made of SiC shown in FIG. 1, the inter. It corresponds to the structure of the carbide layer 2, the graphene layer 3, and the metal electrode 4. As the material of the intercalation layer 17, a Group 13 (Group III) element, a metal having a larger absolute value of work function than graphene, or a rare earth element can be adopted.

On the other hand, there is no intercalation layer and graphene layer between the n ⁺ type source regions 13a and 13b shown in FIG. 10 and the source electrode 19, and the source regions 13a and 13b and the source electrode 19 are in contact with each other. ..

On the lower surface of the drift layer 10, a second main electrode region (drain region) 20 made of a first conductive type (n ⁺ type) SiC having a higher impurity density than the drift layer 10 is arranged. For example, the drain region 20 is composed of a SiC substrate, and the drift layer 10 is composed of an epitaxial growth layer. A second main electrode (drain electrode) 21 is arranged on the lower surface of the drain region 20. There is no intercalation layer and graphene layer between the n ⁺ type drain region 20 and the drain electrode 21, and the drain region 20 and the drain electrode 21 are in contact with each other.

According to the semiconductor device according to the second embodiment, the ohmic contact of the p ⁺ type base contact region 12 having a relatively higher contact resistance than the n ⁺ type source regions 13a and 13b and the n ⁺ type drain region 20. In the portion, the intercalation layer 17 and the graphene layer 18 are selectively arranged between the base contact region 12 and the source electrode 19. As a result, an interfacial dipole is formed between the base contact region 12 and the graphene layer 18, and contact resistance can be reduced.

<Manufacturing method of semiconductor device made of SiC>
Next, an example of a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. 11 to 16. The method for manufacturing a semiconductor device made of SiC described below is an example, and the semiconductor device according to the second embodiment can be manufactured by various other methods.

As shown in FIG. 11, the n ⁺ type SiC substrate is used as the drain region 20, and an n ⁻ type drift layer 10 having a lower impurity density than the drain region 20 is epitaxially grown on the drain region 20.

Next, a photoresist film is applied onto the drift layer 10, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an ion implantation mask, p-type impurities such as Al and B are implanted into the surface of the drift layer 10 in multiple stages with different acceleration voltages so that the implantation range is different. On the high acceleration voltage side, multi-stage ion implantation is performed with a low dose amount that realizes the p-type base region 11, and on the low acceleration voltage side, the dose amount is higher than that on the high acceleration voltage side so as to realize the p ⁺ type base contact region 12. Ion implant with. Remove the photoresist film used as a mask.

Further, a photoresist film is newly applied to the upper surface of the drift layer 10, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as a mask, n-type impurity ions such as nitrogen (N) are selectively injected in multiple stages. Remove the photoresist film used as a mask. After that, heat treatment is performed to activate the injected ions, and as shown in FIG. 12, a p-type base region 11, a p ⁺ -type base contact region 12 and an n ⁺ -type source region are formed on the upper part of the drift layer 10. Form 13a and 13b.

Next, the surface of the drift layer 10 is thermally oxidized to form a gate insulating film 14 made of a silicon oxide film (SiO ₂ film). Then, a polysilicon layer (doped polysilicon layer) to which an n-type impurity is added is deposited on the gate insulating film 14 by a CVD method or the like. Then, the gate insulating film 14 and a part of the doped polysilicon layer are selectively removed by photolithography technology, dry etching, or the like to form the gate electrodes 15a and 15b as shown in FIG.

Next, an interlayer insulating film 16 made of a phospholytic glass (PSG) film or the like is deposited on the upper surfaces of the gate electrodes 15a and 15b, the source regions 13a and 13b, and the base contact region 12 by a CVD method or the like. Next, a photoresist film is applied on the interlayer insulating film 16 and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as a mask, a part of the interlayer insulating film 16 is selectively removed by dry etching to expose the base contact region 12 and the source regions 13a and 13b, and then the photoresist film is formed. Remove. As a result, as shown in FIG. 14, the interlayer insulating film 16 is formed so as to cover the gate electrodes 15a and 15b.

Next, the graphene layer 18 is selectively formed on the upper surface of the base contact region 12 by heat treatment or the like. The graphene layer 18 may also be formed on the upper surfaces of the source regions 13a and 13b. Then, using a mask such as a SiO ₂ film, atoms constituting the intercalation layer 17 are selectively deposited on the upper surface of the graphene layer 18 by a sputtering method, a vapor deposition method, or the like. Then, by performing heat treatment, the deposited atoms are inserted (intercalated) between the graphene layer 18 and the base contact region 12, and the intercalation layer 17 is selected between the graphene layer 18 and the base contact region 12. Form.

Next, a metal film such as Au is deposited on the graphene layer 18 and the source regions 13a and 13b by a sputtering method, a vapor deposition method, or the like, and the photoresist film is removed to form the source electrode 19. After that, as shown in FIG. 10, the drain electrode 21 is formed on the lower surface of the drain region 20 by a sputtering method, a vapor deposition method, or the like. In this way, the semiconductor device according to the second embodiment is completed.

(Other embodiments)
As mentioned above, the invention has been described by the first and second embodiments, but the statements and drawings that form part of this disclosure should not be understood as limiting the invention. This disclosure will reveal to those skilled in the art various alternative embodiments, examples and operational techniques.

For example, in the first and second embodiments, a semiconductor device made of SiC using the electrode extraction region 1 made of SiC is exemplified, but from a wide bandgap semiconductor such as gallium nitride (GaN) or diamond other than SiC. It is also possible to apply it to a semiconductor device using the electrode extraction region 1.

Further, in the semiconductor device according to the first embodiment, as shown in FIG. 17, a plurality of intercalation layers 2A and 2B made of atoms of different types are arranged between the graphene layer 3 and the metal electrode 4. It may have been done. When manufacturing the structure shown in FIG. 17, after forming the graphene layer 3 on the upper surface of the electrode extraction region 1, a plurality of intercalation layers 2A and 2B are formed on the upper surface of the graphene layer 3 by a vacuum deposition method, a sputtering method or the like. The atoms that make up the graphene are sequentially deposited. After that, by performing heat treatment, the deposited atoms are sequentially inserted between the electrode extraction region 1 and the graphene layer 3, and a plurality of intercalation layers 2A and 2B are formed. Although FIG. 17 illustrates a structure in which two types of intercalation layers 2A and 2B different from each other are arranged, three or more types of intercalation layers may be arranged.

Further, in the semiconductor device according to the first embodiment, as shown in FIG. 1, a structure in which the graphene layer 3 and the metal electrode 4 are in contact with each other is illustrated, but an insulator is provided between the graphene layer 3 and the metal electrode 4. A layer (h-BN layer) of hexagonal boron nitride (h-BN) may be provided. The h-BN layer may have a single-layer structure or a laminated structure. The h-BN layer has a function of preventing the graphene layer 3 and the metal electrode 4 from interacting with each other to have an adverse effect. After the formation of the graphene layer 3 and before the formation of the metal electrode 4, for example, a single h-BN layer may be formed on the graphene layer 3. The h-BN layer can be formed by, for example, a CVD method, an MBE method, and a method of transferring a preformed h-BN layer onto the graphene layer 3.

Further, in the semiconductor device according to the second embodiment, as shown in FIG. 10, there is no intercalation layer and graphene layer between the n ⁺ type source regions 13a and 13b and the source electrode 19, and the source is An example is shown in which the regions 13a and 13b are in contact with the source electrode 19, but as shown in FIG. 18, between the source regions 13a and 13b and the source electrode 19, the intercalation layers 17a and 17b and the graphene layer are formed. 18a and 18b may be arranged respectively. That is, the intercalation layers 17a and 17b may be arranged on the upper surfaces of the source regions 13a and 13b, and the graphene layers 18a and 18b may be arranged on the upper surfaces of the intercalation layers 17a and 17b. In this case, since the source regions 13a and 13b are n-type, if the transition metal of Group 5 or the element of Group 15 (Group V) is adopted as the material constituting the intercalation layers 17a and 17b, the intercalation layer 17a and 17b are intercalated. The curation layers 17a and 17b can form an intercalation dipole. Further, the intercalation layers 17a and 17b between the source regions 13a and 13b and the source electrode 19 may be sparsely composed of an adsorption layer having an atomic number of less than one atomic layer. In the structure shown in FIG. 18, for example, the graphene layers 18, 18a, 18b are collectively formed by heat treatment, and then the atoms constituting the graphene layer 18 selectively by vapor deposition or the like and the atoms constituting the graphene layers 18a, 18b are formed. Can be formed by sequentially depositing and heat-treating all at once.

Further, as the semiconductor device according to the second embodiment, the structure of the planar type and vertical power MOSFET is illustrated in FIG. 10, but the semiconductor device of the present invention can be used in various structures other than the structure shown in FIG. Applicable. Further, the applicable range of the semiconductor device of the present invention is not limited to the MOSFET in which the oxide film is the gate insulating film, and a MISFET using a gate insulating film other than the oxide film may be used. Further, the semiconductor device made of SiC of the present invention is not limited to FET, and is applicable as long as it is a semiconductor device that forms an ohmic contact between an electrode extraction region made of a wide bandgap semiconductor such as an IGBT or SIT and a metal electrode. It is possible.

For example, in the case of an IGBT, an intercalation layer and a graphene layer may be arranged between the p ⁺ type collector region on the lower surface side of the drift layer and the collector electrode on the lower surface side thereof. That is, the intercalation layer may be arranged on the lower surface of the p ⁺ type collector region, and the graphene layer may be arranged on the lower surface of the intercalation layer. By adopting a Group 13 (Group III) element, a metal having a larger absolute value of work function than graphene, or a rare earth element as the material of the intercalation layer, the intercalation layer can be formed between the collector region and the graphene layer. Interfacial dipoles can be formed between them.

1 ... Electrode extraction region 2, 2A, 2B, 17, 17a, 17b ... Intercalation layer 3, 18, 18a, 18b ... Graphene layer 3a ... Buffer layer 4 ... Metal electrode 10 ... Drift layer 11 ... Base region 12 ... Base Contact regions 13a, 13b ... Source region 14 ... Gate insulating film 15a, 15b ... Gate electrode 16 ... Interlayer insulating film 19 ... Source electrode 20 ... Drain region 21 ... Drain electrode

Claims (8)

An electrode extraction region made of a wide bandgap semiconductor provided in a part of the active region,
An intercalation layer arranged on the upper surface of the electrode extraction region,
The graphene layer arranged on the upper surface of the intercalation layer and
A metal electrode arranged on the upper surface of the graphene layer is provided, and the intercalation layer forms an interfacial dipole between the electrode extraction region and the graphene layer.
When the electrode extraction region is p-type, the intercalation layer is composed of at least one of a group 13 element, a metal having a higher absolute value of work function than graphene, and a rare earth element.
When the electrode extraction region is n-type, the semiconductor device is characterized in that the intercalation layer is composed of at least one of a Group 5 transition metal and a Group 15 element . The semiconductor device according to claim 1, wherein the intercalation layer is at the atomic layer level of three or less layers. The semiconductor device according to claim 1 or 2 , wherein the intercalation layer is formed by laminating atoms of different types from each other. A semiconductor layer made of wide bandgap semiconductors and
A first conductive type first electrode extraction region made of a wide bandgap semiconductor provided on the upper part of the semiconductor layer, and
The first intercalation layer arranged on the upper surface of the first electrode extraction region,
The first graphene layer arranged on the upper surface of the first intercalation layer,
A second conductive type second electrode extraction region made of a wide bandgap semiconductor provided in contact with the first electrode extraction region on the upper part of the semiconductor layer.
The first graphene layer and the first main electrode arranged on the upper surface of the second electrode extraction region are provided, and the first intercalation layer is provided between the first electrode extraction region and the first graphene layer. Forming an interfacial dipole,
When the first electrode extraction region is p-type, the first intercalation layer is composed of at least one of a group 13 element, a metal having a higher absolute value of work function than graphene, and a rare earth element.
When the first electrode extraction region is n-type, the semiconductor device is characterized in that the first intercalation layer is composed of at least one of a Group 5 transition metal and a Group 15 element . The second intercalation layer arranged on the upper surface of the second electrode extraction region,
A second graphene layer arranged on the upper surface of the second intercalation layer is further provided, and the second intercalation layer forms an interface dipole between the second electrode extraction region and the second graphene layer. death,
When the second electrode extraction region is p-type, the second intercalation layer is composed of at least one of a group 13 element, a metal having a higher absolute value of work function than graphene, and a rare earth element.
The fourth aspect of claim 4 , wherein when the second electrode extraction region is n-type, the second intercalation layer is composed of at least one of a Group 5 transition metal and a Group 15 element. Semiconductor device. The semiconductor device according to claim 5 , wherein the second intercalation layer is composed of an atomic layer of less than one atomic layer. A third electrode extraction region made of a wide bandgap semiconductor provided in the lower part of the semiconductor layer, and
A third intercalation layer arranged on the lower surface of the third electrode extraction region,
A third graphene layer arranged on the lower surface of the third intercalation layer,
A second main electrode arranged on the lower surface of the third graphene layer is further provided, and the third intercalation layer forms an interfacial dipole between the third electrode extraction region and the third graphene layer.
When the third electrode extraction region is p-type, the third intercalation layer is composed of at least one of a group 13 element, a metal having a higher absolute value of work function than graphene, and a rare earth element.
Claims 4 to 6 , wherein when the third electrode extraction region is n-type, the third intercalation layer is composed of at least one of a group 5 transition metal and a group 15 element. The semiconductor device according to any one item. A step of forming a graphene layer on the upper surface of an electrode extraction region made of a wide bandgap semiconductor provided in a part of the active region, and
A step of depositing atoms for forming an intercalation layer on the upper surface of the graphene layer, and
By performing heat treatment and inserting the deposited atoms into the interface between the graphene layer and the electrode extraction region, the intercalation layer forming an interface dipole is formed between the electrode extraction region and the graphene layer. And the process to do
Including the step of forming a metal electrode on the upper surface of the graphene layer.
When the electrode extraction region is p-type, the intercalation layer is composed of at least one of a group 13 element, a metal having a higher absolute value of work function than graphene, and a rare earth element.
A method for manufacturing a semiconductor device , wherein when the electrode extraction region is n-type, the intercalation layer is composed of at least one of a Group 5 transition metal and a Group 15 element .

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