JP2019040921A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of forming a low resistance ohmic contact between an electrode extraction region made of a wide bandgap semiconductor and a metal electrode. SOLUTION: An electrode extraction region 1 made of a wide bandgap semiconductor provided in a part of an active region, an intercalation layer 2 arranged on the upper surface of the electrode extraction region 1, and an upper surface of the intercalation layer 2. The graphene layer 3 is provided with the arranged graphene layer 3 and the metal electrode 4 arranged on the upper surface of the graphene layer 3, and the intercalation layer 2 forms an interfacial dipole between the electrode extraction region 1 and the graphene layer 3. [Selection diagram] Fig. 1

Description

  The present invention relates to a semiconductor device made of a wide band gap semiconductor such as silicon carbide (SiC) and a method for manufacturing the same.

  In general, energy loss during operation of a MOSFET is mainly governed by losses due to drift resistance, channel resistance, and contact resistance. Of these, the contact resistance needs to be sufficiently lower than the drift resistance and channel resistance. Even when a semiconductor device made of SiC is manufactured, the formation of an ohmic contact between an electrode extraction region made of SiC and a metal electrode is one of the technical problems.

  Conventionally, as a method for forming an ohmic contact between an electrode extraction region made of SiC and a metal electrode, a structure in which a graphene layer is arranged between the electrode extraction region and the metal electrode has been proposed (see Patent Document 1).

  In the structure described in Patent Document 1, an ohmic contact between the electrode extraction region made of SiC and the metal electrode can be obtained, but a technique for further reducing the contact resistance is required.

International Publication No. 2016/002386

  In view of the above problems, an object of the present invention is to provide a semiconductor device capable of forming a low-resistance ohmic contact between an electrode extraction region made of a wide band gap semiconductor and a metal electrode, and a method for manufacturing the same.

  One embodiment of the present invention includes: (a) an electrode extraction region made of a wide band gap semiconductor provided in a part of the active region; (b) an intercalation layer disposed on the upper surface of the electrode extraction region; A graphene layer disposed on the top surface of the intercalation layer, and (d) a metal electrode disposed on the top surface of the graphene layer, the intercalation layer having an interface dipole between the electrode extraction region and the graphene layer The gist of the semiconductor device is characterized by being formed.

  In another aspect of the present invention, (a) a semiconductor layer made of a wide bandgap semiconductor, (b) a first electrode extraction region of the first conductivity type made of a wide bandgap semiconductor provided on the semiconductor layer, (C) an intercalation layer disposed on the upper surface of the first electrode extraction region; (d) a graphene layer disposed on the upper surface of the intercalation layer; and (e) a first electrode extraction region on the semiconductor layer. A second-conductivity-type second electrode extraction region made of a wide bandgap semiconductor provided in contact with the substrate, and (f) a graphene layer and a first main electrode disposed on the upper surface of the second electrode extraction region, The gist of the semiconductor device is that the calation layer forms an interface dipole between the first electrode extraction region and the graphene layer.

  In another aspect of the present invention, (a) a step of forming a graphene layer on the upper surface of an electrode extraction region made of a wide bandgap semiconductor provided in a part of the active region, and (b) an interface on the upper surface of the graphene layer A step of depositing atoms for forming a calation layer; and (c) performing a heat treatment, and inserting the deposited atoms into the interface between the graphene layer and the electrode extraction region, thereby forming a gap between the electrode extraction region and the graphene layer. The gist of the present invention is a method for manufacturing a semiconductor device, comprising: a step of forming an intercalation layer for forming an interfacial dipole, and a step (d) of forming a metal electrode on an upper surface of the graphene layer.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can form the low resistance ohmic contact of the electrode extraction area | region which consists of a wide band gap semiconductor, and a metal electrode, and its manufacturing method can be provided.

It is principal part sectional drawing which shows an example of the semiconductor device which concerns on the 1st Embodiment of this invention. It is the schematic for demonstrating the hypothesis of contact formation of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. FIG. 4 is a process cross-sectional view subsequent to FIG. 3 illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 5 is a process cross-sectional view subsequent to FIG. 4 illustrating an example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6A is a low-energy electron diffraction (LEED) diffraction image during graphene layer formation in the second example of the first embodiment, and FIG. 6B corresponds to FIG. It is typical sectional drawing. FIG. 7A is a LEED diffraction image after depositing platinum (Pt) of the second example of the first embodiment, and FIG. 7B is a schematic view corresponding to FIG. It is sectional drawing. 8A is a LEED diffraction image after 1000 ° C. annealing of the second example of the first embodiment, and FIG. 8B is a schematic cross-sectional view corresponding to FIG. 8A. is there. 9A is a LEED diffraction image after 1200 ° C. annealing of the second example of the first embodiment, and FIG. 9B is a schematic cross-sectional view corresponding to FIG. 9A. is there. It is sectional drawing which shows an example of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. FIG. 12 is a process cross-sectional view subsequent to FIG. 11 illustrating an example of the method for manufacturing the semiconductor device according to the second embodiment. FIG. 13 is a process cross-sectional view subsequent to FIG. 12 illustrating an example of the method for manufacturing the semiconductor device according to the second embodiment. FIG. 14 is a process cross-sectional view subsequent to FIG. 13 illustrating an example of the method for manufacturing the semiconductor device according to the second embodiment. FIG. 15 is a process cross-sectional view subsequent to FIG. 14 illustrating an example of the method for manufacturing the semiconductor device according to the second embodiment. FIG. 16 is a process cross-sectional view subsequent to FIG. 15 illustrating an example of the method for manufacturing the semiconductor device according to the second embodiment. It is principal part sectional drawing which shows an example of the semiconductor device which concerns on other embodiment of this invention. It is sectional drawing which shows another example of the semiconductor device which concerns on other embodiment of this invention.

  In the following, first and second embodiments of the present invention will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  In the present specification, the “first main electrode region” means a semiconductor region that is either a source region or a drain region in a field effect transistor (FET) or a static induction transistor (SIT). In an insulated gate bipolar transistor (IGBT), a semiconductor region that is either an emitter region or a collector region is selected. It means a semiconductor region that becomes one side. The “second main electrode region” refers to a semiconductor region that is either a source region or a drain region that is not the first main electrode region in the FET or SIT, and the first main electrode region in the IGBT. The region that becomes either the emitter region or the collector region that does not become a region means the region that becomes either the anode region or the cathode region that does not become the first main electrode region in the SI thyristor or GTO. That is, if the “first main electrode region” is the source region, the “second main electrode region” means the drain region. If the “first main electrode region” is an emitter region, the “second main electrode region” means a collector region. If the “first main electrode region” is an anode region, the “second main electrode region” means a cathode region.

  In this specification, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example. However, the first conductivity type is selected as the p-type and the second conductivity type is selected in the reverse relationship. The two conductivity type may be n-type. Further, in this specification and the accompanying drawings, “+” and “−” attached to “n” and “p” in superscript are compared with semiconductor regions not marked with “+” and “−”. It means that the semiconductor region has a relatively high or low impurity density. Further, in the present specification, the members and regions to which “first conductivity type” and “second conductivity type” are added mean members and regions made of a semiconductor material without any particular limitation. This is obvious both technically and logically. Also, in this specification, in the Miller index notation, “−” means a bar attached to the index immediately after that, and “−” is added before the index to indicate a negative index.

  In the following description, the definitions of “upper” and “lower” such as “upper surface” and “lower surface” are merely representational problems on the illustrated sectional view. For example, the orientation of the semiconductor device may be changed by 90 °. For example, the names of “up” and “down” are “left” and “right”, and the relationship between the names of “up” and “bottom” is of course reversed when observed by changing 180 °.

(First embodiment)
<Structure of semiconductor device made of SiC>
As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention includes an electrode extraction region 1 made of p ⁺ -type SiC provided in a part of an active region, and an upper surface of the electrode extraction region 1. The intercalation layer 2 is disposed, the graphene layer 3 is disposed on the top surface of the intercalation layer 2, and the metal electrode 4 is disposed on the top surface of the graphene layer 3.

Electrode lead-out region 1 is, for example, a semiconductor substrate (SiC wafer) made of p-type and p ⁺ -type SiC may also be itself, at least a portion of the p-type and p ⁺ -type epitaxial layer epitaxially grown on the SiC wafer It may be. Alternatively, it may be a contact region or the like of at least a part of a p-type or p ⁺ -type semiconductor region provided by adding a p-type impurity to an upper part of a SiC wafer or an epitaxial growth layer. Further, in a semiconductor region such as a p-type or p ⁺ -type contact region provided by adding a p-type impurity to an upper portion of an n-well provided by adding an n-type impurity to the upper portion of the SiC wafer or the epitaxial growth layer. There may be. The carrier density of the electrode extraction region 1 is, for example, about 1 × 10 ¹⁶ / cm ³ or more.

  The electrode extraction region 1 made of SiC is limited to any one of a six-layer periodic hexagonal crystal (6H—SiC), a four-layer periodic hexagonal crystal (4H—SiC), and a three-layer periodic hexagonal crystal (3C—SiC). Absent. The surface of the electrode extraction region 1 is subjected to a surface flattening process to such an extent that, for example, an atomic level flatness is obtained. The crystal plane orientation of the surface in contact with the intercalation layer 2 in the electrode extraction region 1 is, for example, 6H-, 4H-SiC (0001) plane (Si plane), (000-1) plane (C plane), (11- 20) It may be a plane. The (1-10) plane of 3C—SiC and the (11-20) plane of hexagonal crystal are equivalent planes.

  The intercalation layer 2 forms an interface dipole (interface dipole) between the electrode extraction region 1 and the graphene layer 3, thereby generating a potential difference (Schottky barrier) generated at the interface between the electrode extraction region 1 and the metal electrode 4. (Height) can be reduced. The thickness of the intercalation layer 2 may be the thickness of one atomic layer constituting the intercalation layer 2, or may be the thickness of two or more atomic layers. Alternatively, in the intercalation layer 2, atoms may be sparsely arranged with a thickness of an adsorption layer having a number of atoms less than one atomic layer constituting the intercalation layer 2. However, the intercalation layer 2 is at the atomic layer level of three or less layers constituting the intercalation layer 2 so that an interface dipole can be easily formed between the electrode extraction region 1 and the graphene layer 3. Is preferred.

  The material constituting the intercalation layer 2 is at least one of a Group 13 (Group III) element, a metal whose work function has a larger absolute value than graphene, and a rare earth element that becomes a trivalent cation. One can be adopted. The Group 13 element includes boron (B) and one or more earth metals of aluminum (Al), gallium (Ga), indium (In), or thallium (Tl), or one of these earth metals. Selected from the group consisting of alloys.

  A metal whose work function has an absolute value larger than that of graphene preferably has an absolute value of the work function of 5.0 eV or more. Metals having a larger work function absolute value than graphene are platinum (Pt), gold (Au), rubidium (Rb), ruthenium (Ru), rhodium (Rh), palladium (Pd), rhenium (Re), iridium ( Ir) or an alloy containing one or more of these metals.

  Examples of rare earth elements include scandium (Sc), yttrium (Y), and lanthanoids (excluding radioactive elements). Lanthanoids (excluding radioactive elements) are lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium. It is selected from the group consisting of (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

  The graphene layer 3 is composed of graphene, which is a semiconductor having no band gap. Graphene is a sheet-like substance having a thickness of one C atom in which carbon (C) atoms are bonded in a hexagonal lattice shape. The graphene layer 3 may have a single-layer structure of graphene or a stacked structure of two or more layers of graphene. In order to easily insert the intercalation layer 2 between the electrode extraction region 1 and the graphene layer 3, the graphene layer 3 preferably has a single layer structure or a laminated structure of three or less graphene layers. In addition, the graphene layer 3 is more preferably a single layer structure because the single layer structure has no gap and the Fermi level can easily move.

  FIG. 1 illustrates a graphene layer 3 having a single layer structure. A plurality of C atoms constituting the graphene layer 3 are each shown in a circular shape, and a covalent bond of C atoms is shown in a straight line connecting adjacent circular portions. Further, in FIG. 1, in order to clarify the position of each interface between the intercalation layer 2, the graphene layer 3, and the metal electrode 4, the intercalation layer 2, the graphene layer 3, and the metal electrode 4 are schematically separated from each other. As shown, the intercalation layer 2, the graphene layer 3, and the metal electrode 4 are actually in contact with each other.

  The metal electrode 4 forms an ohmic contact with the electrode extraction region 1 through the intercalation layer 2 and the graphene layer 3. The metal electrode 4 may be a surface electrode constituting a general element structure. The metal electrode 4 may be, for example, a source electrode or a drain electrode of a MOSFET that constitutes an active region, or may be an emitter electrode or a collector electrode of an IGBT that constitutes an active region. Furthermore, a pn diode, a pin diode, or the like constituting the active region, or an anode electrode of a thyristor may be used.

  As an electrode material of the metal electrode 4, gold (Au), silver (Ag), platinum (Pt), titanium (Ti), nickel (Ni), iron (Fe), cobalt (Co), copper (Cu), chromium ( Cr), Al, Pd, or an alloy containing one or more of these metals may be used. Further, the metal electrode 4 may be a laminated film in which a plurality of metal films made of any one of these metals and alloys are laminated in different combinations.

FIG. 2 shows a structure obtained by rotating the structure shown in FIG. 1 by 90 ° counterclockwise and a band diagram corresponding to the structure. As shown in FIG. 2, the electron affinity χ _SiC of p ⁺ type 4H—SiC constituting the electrode extraction region 1 is 3.6 eV, the work function φ _{gra of} graphene constituting the graphene layer 3 is 4.5 eV, and the metal electrode The work function φ _Au of Au as an example of the metal constituting 4 is 5.1 eV. By inserting the graphene layer 3 at the interface between the electrode extraction region 1 and the metal electrode 4, the Schottky barrier φb is reduced by the movement of the graphene Fermi level, but the height is only the amount of the movement of the graphene Fermi level. Only happens. Therefore, in the p-type, the Fermi level shift is small, and the contact resistance tends to be larger than that in the n-type. Therefore, in the semiconductor device according to the first embodiment, by arranging the intercalation layer 2 between the electrode extraction region 1 and the graphene layer 3, the charge balance is further changed, and the Schottky barrier φb is reduced. Make it smaller. That is, contact resistance is reduced by intercalating cations to form an interface dipole opposite to the n-type.

<Manufacturing method of semiconductor device made of SiC>
Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the intercalation layer 2, the graphene layer 3, and the metal electrode 4 with reference to FIGS.

  First, a semiconductor wafer (SiC wafer) made of p-type SiC having a diameter of 3 inches and subjected to double-side mirror polishing by chemical mechanical polishing (CMP) is prepared. The thickness of the SiC wafer may be 430 μm, for example. The main surface of the SiC wafer may be, for example, a (0001) plane having an off angle of about 4 ° to 8 ° in the <11-20> direction.

Next, a p-type epitaxial layer is grown on the main surface of the SiC wafer by chemical vapor deposition (CVD). The impurity density and thickness of this epitaxial layer may be, for example, 1 × 10 ¹⁹ / cm ³ and 10 μm, respectively. Thereby, an epitaxial wafer formed by growing an epitaxial layer on the SiC wafer is formed. Next, an active region is formed on the epitaxial layer by a general method. However, detailed description of a specific manufacturing process of the active region is omitted here. That is, in the following description, the electrode extraction region 1 may be a part of the active region provided in the epitaxial wafer. Depending on the structure of the semiconductor device, the semiconductor wafer itself may be used as in the case of the back surface of the semiconductor wafer. This can be the electrode extraction region 1.

Next, the upper surface of the electrode extraction region 1 is cleaned by UV ozone cleaning using ultraviolet rays (UV) and ozone (O ₃ ), and the upper surface of the electrode extraction region 1 is removed by organic cleaning treatment. Next, as shown in FIG. 4, a single graphene layer 3 is formed on the upper surface of the electrode extraction region 1 by heat treatment. For example, by heating the electrode extraction region 1 to, for example, about 1200 ° C. or more, Si atoms are desorbed from SiC constituting the electrode extraction region 1, and the graphene layer 3 made of the remaining C atoms may be formed. Further, as a method of forming the graphene layer 3, the CVD method, the molecular beam epitaxy (MBE) method, the molecular layer epitaxy (MLE) method, the formation by laser irradiation, or the like, or the graphene layer 3 formed in advance is used as an electrode extraction region. Alternatively, a method of transferring onto the first layer may be used.

For example, when the method of forming the graphene layer 3 by heating the electrode extraction region 1 is used, a semiconductor wafer in which the electrode extraction region 1 is configured is inserted into a reaction furnace (chamber) of an infrared condensing ultra-high temperature heating apparatus. . Then, the inside of the reaction furnace is evacuated to about 6.6 × 10 ⁻¹ Pa, for example. For example, argon (Ar) gas is introduced into the reaction furnace until the atmospheric pressure is reached, and the upper surface of the electrode extraction region 1 is exposed to an Ar gas atmosphere by continuing to flow at a predetermined flow rate. And after heating the temperature in a reaction furnace from room temperature (for example, about 25 degreeC) to about 1650 degreeC with the temperature increase rate of 20 degreeC / min, the temperature is maintained for about 5 minutes. Thereby, the graphene layer 3 having a single layer structure is formed on the upper surface of the electrode extraction region 1. When the graphene layer 3 has a laminated structure, after the temperature in the reaction furnace reaches about 1650 ° C., the temperature maintenance time may be further increased. Then, after the temperature in the reaction furnace is lowered to room temperature, the semiconductor wafer having the electrode extraction region 1 is taken out from the reaction furnace.

  Next, any one of group 13 elements (group III elements) constituting the intercalation layer 2, a metal having a larger work function absolute value than graphene, or a rare earth element is formed by vacuum deposition or sputtering. Are deposited on the upper surface of the graphene layer 3. Thereafter, by performing heat treatment, as shown in FIG. 4, the deposited atoms are inserted (intercalated) into the interface between the graphene layer 3 and the electrode extraction region 1 to form the intercalation layer 2. The heat treatment conditions are appropriately selected according to the atoms constituting the intercalation layer 2. For example, the heat treatment conditions are 1000 ° C. in a vacuum when the atoms constituting the intercalation layer 2 are B, 1200 ° C. in an Ar gas atmosphere for Pt, and 600 ° C. in a vacuum for Al. The thickness of the intercalation layer 2 can be controlled, for example, by adjusting the heat treatment conditions. For example, the thickness of the intercalation layer 2 can be increased by increasing the heating temperature.

  Next, as shown in FIG. 1, a metal electrode 4 made of Au or the like is formed on the top surface of the graphene layer 3 by vacuum deposition, sputtering, MBE, or the like. When the electrode extraction region 1 is a part of the active region provided in the epitaxial wafer, the metal electrode 4 is patterned by a metallization process by a photolithography process. The semiconductor wafer after completion of the metallization process of the metal electrode 4 is then diced into a chip having a predetermined size such as a chip size of 10 mm, for example, and a semiconductor chip is formed, thereby completing a semiconductor device made of SiC.

  In the above-described method for manufacturing a semiconductor device made of SiC, the process proceeds to the metallization process in the wafer state, and after completion of the metallization process, the chip is formed by dicing. However, the present invention is not limited to such a procedure. Depending on the requirements of the manufacturing equipment, etc., the manufacturing may have a small chamber by dividing into a specific size at a stage before forming the graphene layer 3, the intercalation layer 2 and the metal electrode 4 in each electrode extraction region 1. It may be inserted inside the device.

  According to the semiconductor device according to the first embodiment, the intercalation layer 2 is disposed between the electrode extraction region 1 and the graphene layer 3, whereby the interface dipole is interposed between the electrode extraction region 1 and the graphene layer 3. And the potential difference (Schottky barrier height) generated at the interface between the electrode extraction region 1 and the metal electrode 4 can be reduced. Thereby, a low resistance ohmic contact between the electrode extraction region 1 and the metal electrode 4 can be formed with high reproducibility.

1 illustrates the case where the electrode extraction region 1 is p-type, but the electrode extraction region 1 may be n-type. Electrode lead-out region 1 may be a SiC wafer itself consisting of n-type and n ⁺ -type SiC, may be at least part of the n-type and n ⁺ -type epitaxial layer on a SiC wafer. Alternatively, it may be a contact region or the like of at least a part of an n-type or n ⁺ -type semiconductor region provided on an SiC wafer or an epitaxial growth layer. Further, it may be a p-well provided above the SiC wafer or the epitaxial growth layer, an n-type or n ⁺ -type contact region provided above the p-base, or the like.

  When the electrode extraction region 1 is n-type, at least one of a Group 5 transition metal and a Group 15 (Group V) element can be adopted as a material constituting the intercalation layer 2. The Group 5 transition metal is selected from the group consisting of tantalum (Ta), niobium (Nb), vanadium (V), or an alloy containing one or more of these metals. The Group 15 (Group V) element is selected from the group consisting of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), or an alloy containing one or more of these metals. A dipole is formed between the n-type electrode extraction region 1 and the graphene layer 3 by adopting a Group 5 transition metal or a Group 15 (Group V) element as a material constituting the intercalation layer 2. The potential difference (Schottky barrier height) generated at the interface between the electrode extraction region 1 and the metal electrode 4 can be reduced.

<First embodiment>
As a first example of the first embodiment, a stacked structure of a p-type electrode extraction region 1, an intercalation layer 2, a graphene layer 3, and a metal electrode 4 was produced. Three types of samples of Examples A to C were manufactured by changing the atoms constituting the intercalation layer 2 with Al, B, and Pt. In all of Examples A to C, the impurity density of SiC was set to 1 × 10 ¹⁹ / cm ³ . As a comparative example, samples similar to those in Examples A to C were prepared except that the intercalation layer 2 was not provided. Table 1 shows the measurement results of the contact resistance values of Examples A to C and the comparative example.

As shown in Table 1, in any of Examples A to C, the contact resistance is 10 ⁻⁴ Ω / cm ² or less, which is a practical required value, and the contact resistance is 10 ⁻² Ω / cm ^2. It was confirmed that the contact resistance could be greatly reduced compared to

<Second embodiment>
As a second example of the first embodiment, after the graphene layer 3 is formed, Pt is deposited as an element constituting the intercalation layer 2, and in the process of intercalating the deposited Pt by heat treatment, slow electrons The surface of the sample was observed by line diffraction (LEED). The formation conditions of the graphene layer 3 are as follows: a 4 ° -off n-type SiC substrate, an Ar atmosphere, a pressure of 101.325 kPa (gas flow rate: 8.45 × 10 ⁻³ Pa · m ³ / sec), and a heating temperature Was 1575 ° C., the heating rate was 100 ° C./min, and the heating time was 30 minutes. The Pt deposition conditions were a flux of 7 nA and a deposition time of 30 minutes. The Pt intercalation conditions were transferred in-situ to an ultra-high temperature heating device, heated under an Ar atmosphere at a pressure of 101.325 kPa (gas flow rate of 8.45 × 10 ⁻³ Pa · m ³ / sec), and heated. The temperature was 1000 ° C. or 1200 ° C., the heating rate was 20 ° C./min, and the heating time was 60 minutes.

  FIGS. 7 (a), 8 (a), 9 (a), and 10 (a) are diffraction images by LEED after graphene formation, after depositing Pt, after annealing at 1000 ° C., and after annealing at 1200 ° C. 7 (b), FIG. 8 (b), FIG. 9 (b), and FIG. 10 (b) show schematic diagrams of corresponding structures, respectively. In FIG. 7A, points (spots) indicating SiC are surrounded by solid circles, and points indicating graphene are surrounded by broken circles. A small dot around each point indicates a buffer layer in which the graphene of the graphene layer 3 and the SiC of the electrode extraction region 1 are covalently bonded.

  In FIG. 7A, a point indicating the buffer layer is observed, and it is considered that the buffer layer 3a in which the graphene of the graphene layer 3 and the SiC of the electrode extraction region 1 are combined as shown in FIG. 7B is formed. . 8A and 9A, points indicating the buffer layer 3a are observed. As shown in FIGS. 8B and 9B, Pt atoms 2a are deposited, and the temperature is 1000 ° C. It is considered that the buffer layer 3a is maintained even after annealing. On the other hand, in FIG. 10A, the point indicating the buffer layer 3a disappears, and as shown in FIG. 10B, the Pt atoms 2a are moved between the graphene layer 3 and the electrode extraction region 1 by annealing at 1200 ° C. It is considered that the covalent bond between graphene and SiC in the buffer layer 3a was broken.

(Second Embodiment)
<Structure of semiconductor device made of SiC>
A MOSFET will be described as an example of a semiconductor device according to the second embodiment of the present invention. As shown in FIG. 10, the semiconductor device according to the second embodiment is selectively embedded in the semiconductor layer (drift layer) 10 made of SiC of the first conductivity type (n ⁻ type) and the drift layer 10. A second conductivity type (p ⁺ type) base region 11 and a first conductivity type (n ⁺ type) first main electrode region (source region) 13a selectively embedded above the base region 11; 13b.

  Gate electrodes 15 a and 15 b made of doped polysilicon or the like are arranged from the base region 11 to the drift layer 10 via the gate insulating film 14. The upper and side surfaces of the gate electrodes 15 a and 15 b are covered with an interlayer insulating film 16.

A base contact region 12 of a second conductivity type (p ⁺ type) having a higher impurity density than that of the base region 11 is buried on the base region 11 so as to be in contact with the source regions 13a and 13b. A first main electrode (source electrode) 19 is disposed on the source regions 13 a and 13 b and the base contact region 12 so as to cover the interlayer insulating film 16. The source regions 13a and 13b and the base contact region 12 are electrode extraction regions, and form an ohmic contact with the source electrode 19.

An intercalation layer 17 and a graphene layer 18 are selectively disposed between the p ⁺ -type base contact region 12 and the source electrode 19. That is, the structure of the p ⁺ type base contact region 12, the intercalation layer 17, the graphene layer 18 and the source electrode 19 shown in FIG. 10 is the same as the electrode extraction region 1 of the semiconductor device made of SiC shown in FIG. This corresponds to the structure of the calation layer 2, the graphene layer 3, and the metal electrode 4. As a material of the intercalation layer 17, a Group 13 (Group III) element, a metal having a larger work function absolute value than graphene, or a rare earth element can be employed.

On the other hand, there are no intercalation layers and graphene layers between the n ⁺ -type source regions 13a and 13b and the source electrode 19 shown in FIG. 10, and the source regions 13a and 13b and the source electrode 19 are in contact with each other. .

On the lower surface of the drift layer 10, a second main electrode region (drain region) 20 made of SiC of the first conductivity type (n ⁺ type) having a higher impurity density than the drift layer 10 is disposed. For example, the drain region 20 is composed of a SiC substrate, and the drift layer 10 is composed of an epitaxial growth layer. A second main electrode (drain electrode) 21 is disposed on the lower surface of the drain region 20. There is no intercalation layer and graphene layer between the n ⁺ -type drain region 20 and the drain electrode 21, and the drain region 20 and the drain electrode 21 are in contact with each other.

According to the semiconductor device of the second embodiment, the ohmic contact of the p ⁺ type base contact region 12 having a contact resistance relatively higher than that of the n ⁺ type source regions 13 a and 13 b and the n ⁺ type drain region 20. In part, the intercalation layer 17 and the graphene layer 18 are selectively disposed between the base contact region 12 and the source electrode 19. Thereby, an interface dipole is formed between the base contact region 12 and the graphene layer 18, and the contact resistance can be reduced.

<Manufacturing method of semiconductor device made of SiC>
Next, an example of a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. Note that the method for manufacturing a semiconductor device made of SiC described below is an example, and the semiconductor device according to the second embodiment can be manufactured by various other methods.

As shown in FIG. 11, an n ⁻ type drift layer 10 having an impurity density lower than that of the drain region 20 is epitaxially grown on the drain region 20 using an n ⁺ type SiC substrate as the drain region 20.

Next, a photoresist film is applied on the drift layer 10, and the photoresist film is patterned using a photolithography technique. Using the patterned photoresist film as an ion implantation mask, p-type impurities such as Al and B are implanted into the surface of the drift layer 10 in multiple stages by changing the acceleration voltage so that the implantation range is different. On the high acceleration voltage side, multi-stage ion implantation is performed at a low dose to realize the p-type base region 11, and on the low acceleration voltage side, a higher dose than the high acceleration voltage side is realized to realize the p ⁺ -type base contact region 12. Ion implantation. The photoresist film used as a mask is removed.

Further, a photoresist film is newly applied on the upper surface of the drift layer 10, and the photoresist film is patterned by using a photolithography technique. Using the patterned photoresist film as a mask, n-type impurity ions such as nitrogen (N) are selectively implanted in multiple stages. The photoresist film used as a mask is removed. Thereafter, heat treatment is performed to activate the implanted ions, and as shown in FIG. 12, a p-type base region 11, a p ⁺ -type base contact region 12, and an n ⁺ -type source region are formed on the drift layer 10. 13a and 13b are formed.

Next, the surface of the drift layer 10 is thermally oxidized to form a gate insulating film 14 made of a silicon oxide film (SiO ₂ film). Then, a polysilicon layer (doped polysilicon layer) to which an n-type impurity is added is deposited on the gate insulating film 14 by a CVD method or the like. Then, a part of the gate insulating film 14 and the doped polysilicon layer is selectively removed by photolithography technique, dry etching, etc., and gate electrodes 15a and 15b are formed as shown in FIG.

  Next, an interlayer insulating film 16 made of a phosphorous silicate glass (PSG) film or the like is deposited on the upper surfaces of the gate electrodes 15a and 15b, the source regions 13a and 13b, and the base contact region 12 by a CVD method or the like. Next, a photoresist film is applied on the interlayer insulating film 16, and the photoresist film is patterned by using a photolithography technique. Using the patterned photoresist film as a mask, a part of the interlayer insulating film 16 is selectively removed by dry etching to expose the base contact region 12 and the source regions 13a and 13b, and then the photoresist film is formed. Remove. As a result, as shown in FIG. 14, an interlayer insulating film 16 is formed so as to cover the gate electrodes 15a and 15b.

Next, the graphene layer 18 is selectively formed on the upper surface of the base contact region 12 by heat treatment or the like. Note that the graphene layer 18 may also be formed on the upper surfaces of the source regions 13a and 13b. Then, using a mask such as a SiO ₂ film, atoms constituting the intercalation layer 17 are selectively deposited on the upper surface of the graphene layer 18 by sputtering or vapor deposition. Thereafter, by performing heat treatment, the deposited atoms are inserted (intercalated) between the graphene layer 18 and the base contact region 12, and the intercalation layer 17 is selected between the graphene layer 18 and the base contact region 12. Form.

  Next, a metal film such as Au is deposited on the graphene layer 18 and the source regions 13a and 13b by sputtering or vapor deposition, and the source electrode 19 is formed by removing the photoresist film. Thereafter, a drain electrode 21 is formed on the lower surface of the drain region 20 by sputtering or vapor deposition, as shown in FIG. In this way, the semiconductor device according to the second embodiment is completed.

(Other embodiments)
As described above, the present invention has been described according to the first and second embodiments. However, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, in the first and second embodiments, the semiconductor device made of SiC using the electrode extraction region 1 made of SiC is exemplified, but from a wide band gap semiconductor such as gallium nitride (GaN) or diamond other than SiC. The present invention can also be applied to a semiconductor device using the electrode extraction region 1.

  In the semiconductor device according to the first embodiment, as shown in FIG. 17, a plurality of intercalation layers 2A and 2B made of different types of atoms are arranged between the graphene layer 3 and the metal electrode 4. May be. When the structure shown in FIG. 17 is manufactured, after the graphene layer 3 is formed on the upper surface of the electrode extraction region 1, a plurality of intercalation layers 2A and 2B are formed on the upper surface of the graphene layer 3 by vacuum deposition or sputtering. Are sequentially deposited. Thereafter, by performing heat treatment, the deposited atoms are sequentially inserted between the electrode extraction region 1 and the graphene layer 3 to form a plurality of intercalation layers 2A and 2B. FIG. 17 illustrates a structure in which two different types of intercalation layers 2A and 2B are arranged, but three or more types of intercalation layers may be arranged.

  In the semiconductor device according to the first embodiment, as illustrated in FIG. 1, the structure in which the graphene layer 3 and the metal electrode 4 are in contact with each other is illustrated, but an insulator is provided between the graphene layer 3 and the metal electrode 4. A hexagonal boron nitride (h-BN) layer (h-BN layer) may be provided. The h-BN layer may have a single layer structure or a stacked structure. The h-BN layer has a function of preventing the graphene layer 3 and the metal electrode 4 from interacting and adversely affecting each other. For example, a single h-BN layer may be formed on the graphene layer 3 after the formation of the graphene layer 3 and before the formation of the metal electrode 4. The h-BN layer can be formed by, for example, a CVD method, an MBE method, and a method of transferring a previously formed h-BN layer onto the graphene layer 3.

In the semiconductor device according to the second embodiment, as shown in FIG. 10, there are no intercalation layer and graphene layer between the n ⁺ type source regions 13a and 13b and the source electrode 19, and the source Although the case where the regions 13a and 13b and the source electrode 19 are in contact with each other is illustrated, as shown in FIG. 18, the intercalation layers 17a and 17b and the graphene layer are provided between the source regions 13a and 13b and the source electrode 19. 18a and 18b may be respectively arranged. That is, the intercalation layers 17a and 17b may be disposed on the upper surfaces of the source regions 13a and 13b, and the graphene layers 18a and 18b may be disposed on the upper surfaces of the intercalation layers 17a and 17b. In this case, since the source regions 13a and 13b are n-type, if a Group 5 transition metal or a Group 15 (Group V) element is used as a material constituting the intercalation layers 17a and 17b, an inter Calation layers 17a and 17b can form an interface dipole. Further, the intercalation layers 17a and 17b between the source regions 13a and 13b and the source electrode 19 may be sparsely configured by an adsorption layer having an atom number of less than one atomic layer. In the structure shown in FIG. 18, for example, after the graphene layers 18, 18 a, and 18 b are collectively formed by heat treatment, the atoms that selectively form the graphene layer 18 by vapor deposition or the like and the atoms that form the graphene layers 18 a and 18 b Can be formed by sequentially depositing and performing heat treatment collectively.

  Further, as the semiconductor device according to the second embodiment, the structure of the planar and vertical power MOSFETs is illustrated in FIG. 10, but the semiconductor device of the present invention is applicable to various structures other than the structure shown in FIG. Applicable. Furthermore, the application range of the semiconductor device of the present invention is not limited to a MOSFET having an oxide film as a gate insulating film, and a MISFET using a gate insulating film other than an oxide film may be used. Further, the semiconductor device made of SiC of the present invention is not limited to an FET, but can be applied to any semiconductor device that forms an ohmic contact between an electrode extraction region made of a wide band gap semiconductor such as IGBT or SIT and a metal electrode. Is possible.

For example, in the case of an IGBT, an intercalation layer and a graphene layer may be disposed between a p ⁺ -type collector region on the lower surface side of the drift layer and a collector electrode on the lower surface side. That is, an intercalation layer may be disposed on the lower surface of the p ⁺ -type collector region, and a graphene layer may be disposed on the lower surface of the intercalation layer. By using a Group 13 (Group III) element, a metal whose work function has a larger absolute value than graphene, or a rare earth element as the material of the intercalation layer, the intercalation layer is formed between the collector region and the graphene layer. An interfacial dipole can be formed between them.

DESCRIPTION OF SYMBOLS 1 ... Electrode extraction area | region 2, 2A, 2B, 17, 17a, 17b ... Intercalation layer 3, 18, 18a, 18b ... Graphene layer 3a ... Buffer layer 4 ... Metal electrode 10 ... Drift layer 11 ... Base region 12 ... Base Contact region 13a, 13b ... Source region 14 ... Gate insulating film 15a, 15b ... Gate electrode 16 ... Interlayer insulating film 19 ... Source electrode 20 ... Drain region 21 ... Drain electrode

Claims (12)

An electrode extraction region made of a wide band gap semiconductor provided in a part of the active region;
An intercalation layer disposed on the upper surface of the electrode extraction region;
A graphene layer disposed on an upper surface of the intercalation layer;
And a metal electrode disposed on an upper surface of the graphene layer, wherein the intercalation layer forms an interface dipole between the electrode extraction region and the graphene layer. The electrode extraction region is p-type;
The semiconductor device according to claim 1, wherein the intercalation layer is made of a Group 13 element. The electrode extraction region is p-type;
The semiconductor device according to claim 1, wherein the intercalation layer is made of a metal having an absolute value of a work function larger than that of graphene. The electrode extraction region is p-type;
The semiconductor device according to claim 1, wherein the intercalation layer is made of a rare earth element. The electrode extraction region is n-type;
The semiconductor device according to claim 1, wherein the intercalation layer is made of at least one of a Group 5 transition metal and a Group 15 element.   The semiconductor device according to claim 1, wherein the intercalation layer is at an atomic layer level of three layers or less.   The semiconductor device according to claim 1, wherein the intercalation layer is formed by stacking different types of atoms. A semiconductor layer made of a wide band gap semiconductor;
A first electrode extraction region of a first conductivity type made of a wide band gap semiconductor provided on the semiconductor layer;
A first intercalation layer disposed on an upper surface of the first electrode extraction region;
A first graphene layer disposed on an upper surface of the first intercalation layer;
A second conductivity type second electrode extraction region made of a wide band gap semiconductor provided on the semiconductor layer in contact with the first electrode extraction region;
A first main electrode disposed on an upper surface of the first graphene layer and the second electrode extraction region, wherein the first intercalation layer is interposed between the first electrode extraction region and the first graphene layer. A semiconductor device characterized by forming an interface dipole. A second intercalation layer disposed on the upper surface of the second electrode extraction region;
A second graphene layer disposed on an upper surface of the second intercalation layer, and the second intercalation layer forms an interface dipole between the second electrode extraction region and the second graphene layer. The semiconductor device according to claim 8.   The semiconductor device according to claim 9, wherein the second intercalation layer has a number of atoms less than one atomic layer. A third electrode extraction region made of a wide band gap semiconductor provided under the semiconductor layer;
A third intercalation layer disposed on the lower surface of the third electrode extraction region;
A third graphene layer disposed on a lower surface of the third intercalation layer;
A second main electrode disposed on a lower surface of the third graphene layer, and the third intercalation layer forms an interface dipole between the third electrode extraction region and the third graphene layer. The semiconductor device according to claim 8, wherein: Forming a graphene layer on the upper surface of the electrode extraction region made of a wide band gap semiconductor provided in a part of the active region;
Depositing atoms for forming an intercalation layer on the top surface of the graphene layer;
Forming the intercalation layer that forms an interface dipole between the electrode extraction region and the graphene layer by performing heat treatment and inserting the deposited atoms into the interface between the graphene layer and the electrode extraction region And a process of
Forming a metal electrode on an upper surface of the graphene layer. A method for manufacturing a semiconductor device, comprising: