JP7003752B2 - Data transfer device, data transfer method, program - Google Patents

Description

The present invention relates to a data transfer device, a data transfer method, and a program.

DMA (Direct Memory Access) is known as a technique for transferring data between memory and memory, between register and memory, and between memory and I / O devices without going through a CPU (Central Processing Unit).

As a technique related to DMA, for example, there is Patent Document 1. Patent Document 1 describes a data transfer device having a transfer execution means that performs DMA transfer based on the set transfer information. According to Patent Document 1, when the transfer information includes the waiting time information, the transfer executing means starts the DMA transfer, waits for the time indicated by the waiting time information included in the transfer information, and then another transfer. Start DMA transfer based on information. The waiting time information is set when the transfer destination and the transfer source satisfy a predetermined condition, such as when the transfer destination address when executing the DMA transfer is included in the transfer source address.

Further, as a related technique, for example, there is Patent Document 2. Patent Document 2 describes an arbiter device that delays the start of execution of a subsequent request having a dependency when making a DMA request having a dependency in which addresses overlap when performing a DMA transfer.

Japanese Unexamined Patent Publication No. 2017-167644 Japanese Unexamined Patent Publication No. 2006-215621

The setting of the DMA descriptor at the time of performing the DMA transfer may be performed by a plurality of requesters such as the core of the accelerator processor as well as the processor. When a plurality of requesters set the DMA descriptor in this way, for example, the DMA transfer according to the setting from the other requesters is performed in the middle of the DMA transfer having the preceding dependency, and the execution order is guaranteed. There was a risk that it would not be possible.

In particular, the dependency between DMA transfers may occur regardless of the transfer destination address, the transfer source address, or the like, for example, when it is desired to execute a subsequent request after changing the flag for changing the control by the preceding DMA transfer. However, in the case of the techniques described in Patent Documents 1 and 2, only the overlap of addresses is considered. Therefore, in the techniques described in Patent Documents 1 and 2, there is a possibility that appropriate control according to the relationship between DMA transfers cannot be executed due to the setting of DMA transfer from a plurality of requesters as described above. there were.

Therefore, an object of the present invention is a data transfer that solves a problem that when there is a DMA transfer setting from a plurality of requesters, it may not be possible to execute appropriate control according to the relationship between the DMA transfers. The purpose is to provide equipment, data transfer methods, and programs.

The data transfer device, which is one embodiment of the present invention, is used to achieve such an object.
Transfer information for performing DMA (Direct Memory Access) transfer is set, and a transfer execution means for performing DMA transfer based on the set transfer information is provided.
The transfer information includes identification information indicating a requester for which the transfer information is set.
The transfer executing means has a configuration in which, after the DMA transfer based on the transfer information is completed, the DMA transfer based on the transfer information registered by another requester different from the requester registered the transfer information is started.

Further, the data transfer method, which is another embodiment of the present invention, is
The data transfer device
Transfer information for performing DMA (Direct Memory Access) transfer is set, and DMA transfer is performed based on the set transfer information.
The transfer information includes identification information indicating a requester for which the transfer information is set.
After the DMA transfer based on the transfer information is completed, the DMA transfer based on the transfer information registered by another requester different from the requester registered with the transfer information is started.

In addition, the program which is another embodiment of the present invention
For data transfer equipment
Transfer information for performing DMA (Direct Memory Access) transfer is set, and a transfer execution means for performing DMA transfer is realized based on the set transfer information.
The transfer information includes identification information indicating a requester for which the transfer information is set.
The transfer executing means is for realizing a process of starting a DMA transfer based on the transfer information registered by another requester different from the requester registered the transfer information after the DMA transfer based on the transfer information is completed. It is a program.

According to the present invention, if there are DMA transfer settings from a plurality of requesters, it may not be possible to execute appropriate control according to the relationship between the DMA transfers. It will be possible to provide data transfer devices, data transfer methods, and programs that solve problems.

It is a block diagram which shows an example of the structure of the system in 1st Embodiment of this invention. It is a figure which shows an example of the structure of the DMA descriptor in 1st Embodiment. It is a figure which shows an example of the DMA transfer performed by a system. It is a sequence diagram which shows an example of the operation of a system. It is a sequence diagram which shows an example of the flow of a general DMA transfer. It is a sequence diagram which shows an example of the flow of a general DMA transfer. It is a figure which shows an example of the structure of the DMA descriptor in the 2nd Embodiment. It is a figure which shows an example of the DMA transfer performed by a system. It is a sequence diagram which shows an example of the operation of a system. It is a block diagram which shows an example of the structure of the data transfer apparatus in 3rd Embodiment of this invention.

[First Embodiment]
The first embodiment of the present invention will be described with reference to FIGS. 1 to 6. FIG. 1 is a block diagram showing an example of the configuration of the system 1. FIG. 2 is a diagram showing an example of the configuration of the DMA descriptor 312 in the first embodiment. FIG. 3 is a diagram showing an example of DMA transfer executed by the system 1. FIG. 4 is a sequence diagram showing an example of the operation of the system 1. 5 and 6 are sequence diagrams showing an example of a general DMA transfer flow.

In the first embodiment, a system 1 capable of performing DMA (Direct Memory Access) transfer will be described. In the system 1 of the present embodiment, the processor 2 sets the DMA descriptor 312, so that the DMA engine 311 executes the DMA transfer. As will be described later, the DMA descriptor 312 in this embodiment has a dependency flag. When the DMA descriptor 312 has the dependency flag, the DMA engine 311 waits for the execution of the succeeding DMA transfer that is dependent on the preceding DMA transfer, while waiting for the succeeding DMA transfer that is not dependent on the preceding DMA transfer. It can be executed without.

FIG. 1 shows an example of the configuration of the system 1 in the present embodiment. Referring to FIG. 1, the system 1 (data transfer device) in the present embodiment includes a host PC (Personal Computer) 2 and an acceleration processor 3. Further, the host PC 2 and the acceleration processor 3 are connected so as to be able to communicate with each other via the communication network 4.

The host PC 2 has a processor 21 which is a control means for executing arithmetic processing and setting for executing DMA transfer, and a host memory 22 for storing information. Since the processor 21 sets the DMA descriptor 312, it is also called a requester.

When executing the DMA transfer, the processor 21 sets the DMA descriptor 312 which is the transfer information via the communication network 4. That is, when executing the DMA transfer, the processor 21 writes a request for the DMA transfer to the DMA descriptor 312 of the DMA engine 311 included in the acceleration processor 3. When the request is written to the DMA descriptor 312, the DMA engine 311 starts the DMA transfer.

The processor 21 has an arithmetic unit (not shown) and a storage device (may be host memory 22 or may be other than host memory 22). The processor 21 realizes a function of setting the DMA descriptor 312 by, for example, executing a program stored in the storage device by the arithmetic unit.

The DMA descriptor 312 set by the processor 21 includes, for example, information necessary for the DMA engine 311 to execute the DMA transfer and information necessary for guaranteeing the execution order of the DMA transfer. There is. FIG. 2 shows an example of the DMA descriptor 312 set by the processor 21. Referring to FIG. 2, the DMA descriptor 312 includes information such as write data, a transfer destination address, a transfer source address, a transfer request, and a transfer length as information required when the DMA engine 311 executes a DMA transfer. I'm out. The DMA engine 311 described later executes data transfer based on information such as write data, a transfer source address, a transfer destination address, a transfer request, and a transfer length on the DMA descriptor 312 shown in FIG.

Further, the DMA descriptor 312 in the present embodiment is a dependency flag (dependency information, required) which is information indicating that the execution order must be guaranteed as the information necessary for guaranteeing the execution order of the DMA transfer. Order guarantee information), write request completion time valid, write request completion time (waiting time information), and information indicating.

The write request completion time indicates the time to wait for the DMA transfer that is dependent on the write request. In other words, the write request completion time indicates the time after the DMA engine 311 starts the DMA transfer based on the information on the DMA descriptor 312 and then waits for the start of the subsequent DMA transfer which is dependent on the DMA engine. The write request completion time is determined based on the time required to complete all the data transfer set in one DMA descriptor 312, for example, between memory and memory, between registers and between registers, and between registers.

The write request completion time valid is information indicating whether or not the write request completion time included in the DMA descriptor 312 is valid. When the write request completion time is valid and the DMA transfer based on the DMA descriptor 312 in which the write request completion time is set is started, the DMA engine 311 performs the subsequent DMA transfer having a dependency on the write request completion time. It will start after waiting for a minute.

The dependency flag indicates whether or not there is a dependency relationship with the preceding DMA transfer. For example, the processor 21 sets the dependency flag when it is determined that it is necessary to guarantee the execution order. When it is judged that it is necessary to guarantee the execution order, for example, when there is an overlap of the forwarding source address and the forwarding address, or when the flag is controlled, the preceding is performed regardless of the overlapping of the addresses. There are cases where you want to have a dependency relationship with DMA transfer.

When the dependency flag is set, the DMA transfer based on the DMA descriptor 312 in which the dependency flag is set is the target of the standby based on the preceding DMA transfer (the target of the execution order guarantee). That is, the DMA transfer based on the DMA descriptor 312 in which the dependency flag is set is started after waiting until the waiting time (write request completion time) based on the preceding DMA transfer elapses. On the other hand, when the dependency flag is not set, the DMA transfer based on the DMA descriptor 312 in which the dependency flag is not set is not the target of the standby based on the preceding DMA transfer (the target of the execution order guarantee). That is, the DMA transfer based on the DMA descriptor 312 in which the dependency flag is not set is started without waiting regardless of whether or not the write request completion time is set in the DMA descriptor 312 at the time of the preceding DMA transfer.

The DMA descriptor 312 includes the information required for the DMA engine 311 to execute the DMA transfer and the information required for guaranteeing the execution order of the DMA transfer as described above. ..

The DMA descriptor 312 and the DMA engine 311 have a corresponding relationship, for example. For example, a DMA transfer based on the same DMA descriptor 312 is performed by the same DMA engine 311.

The acceleration processor 3 executes DMA transfer between memory memory, register memory, register register, etc. without going through the processor 21 based on the DMA descriptor 312 set by the processor 21 of the host PC 2. That is, the acceleration processor 3 executes data transfer between the host memory 22 and the memory 33, between the registers 321 and between the host memory 22 and the memory 33 and the register 321 based on the DMA descriptor 312.

Referring to FIG. 1, the acceleration processor 3 has a DMA unit 31 that executes DMA transfer, a plurality of cores 32, and a memory 33. As shown in FIG. 1, the DMA unit 31 and the core 32, the core 32 and the memory 33, the core 32 and another core 32, and the memory 33 and the DMA unit 31 are connected so as to be able to communicate with each other.

Note that FIG. 1 illustrates a case where the acceleration processor 3 has four cores 32 (cores 32-0, cores 32-1, cores 32-2, and cores 32-3). However, the number of cores 32 included in the acceleration processor 3 is not limited to four. The acceleration processor 3 can have any number of cores 32.

The DMA unit 31 has a plurality of DMA engines 311 and a plurality of DMA descriptors 312. The DMA unit 31 can process a plurality of DMA transfers in parallel by the plurality of DMA engines 311 and the plurality of DMA descriptors 312.

The DMA engine 311 is a transfer execution means that executes a DMA transfer based on the DMA descriptor 312. In other words, the DMA engine 311 performs data transfer based on information such as write data on the DMA descriptor 312 shown in FIG. 2, a transfer source address, a transfer destination address, a transfer request, and a transfer length. Data transfer by the DMA engine 311 is performed, for example, between the host memory 22 and the memory 33, between the registers 321 and between the host memory 22 and the memory 33 and the register 321.

Further, when the DMA engine 311 performs the preceding DMA transfer satisfying the predetermined condition, the DMA engine 311 waits until the predetermined time elapses to start the subsequent DMA transfer satisfying the predetermined condition. For example, when the DMA engine 311 starts the DMA transfer based on the DMA descriptor 312 in which the write request completion time is set and the write request completion time is valid, the write request completion time is started after the DMA transfer is started. Waits for the start of the subsequent DMA transfer based on the DMA descriptor 312 in which the dependency flag is set until the time indicated by (waiting time) elapses. Further, for example, the DMA engine 311 starts the subsequent DMA transfer based on the DMA descriptor 312 in which the dependency flag is not set without waiting even before the time indicated by the write request completion time elapses.

As described above, when the DMA engine 311 starts the DMA transfer based on the DMA descriptor 312 in which the write request completion time is set and the write request completion time is valid, the subsequent DMA transfer satisfying a predetermined condition is started. Wait until the specified time elapses. Further, when the DMA engine 311 performs the preceding DMA transfer satisfying a predetermined condition, the DMA descriptor refers to the start of the DMA transfer based on the DMA descriptor 312 in which the dependency flag is set when the preceding DMA transfer is started. Wait until the time indicated by the write request completion time included in 312 elapses. Further, even when the preceding DMA transfer satisfying a predetermined condition is performed, the DMA engine 311 starts the DMA transfer based on the DMA descriptor 312 in which the dependency flag is not set without waiting.

The DMA descriptor 312 shows information necessary for executing DMA transfer, information necessary for guaranteeing the execution order of DMA transfer, and the like. As described above, the DMA descriptor 312 has the write data, the transfer destination address, the transfer source address, the transfer request, the transfer length, the dependency flag, the write request completion time valid, and the write request completion time. ,It is included.

In the case of this embodiment, as described above, the DMA descriptor 312 is set by the processor 21. Also, the DMA descriptor 312 is referred to by the DMA engine 311. As described above, the DMA transfer based on the same DMA descriptor 312 is performed by the same DMA engine 311.

The core 32 has an address-mapped register 321 and an arithmetic unit 322. There are three types of access paths to register 321. Specifically, for example, there are an access path from the host PC 2, an access path from the arithmetic unit 322 in the core 32, and an access path from another core 32.

The memory 33 is a storage device such as a RAM (Random Access Memory). The memory 33 is used for DMA transfer and the like.

The system 1 has, for example, the above configuration.

In the system 1 described above, it is assumed that the register 321 of the core 32 is mapped to the memory address space where DMA transfer is possible. Further, it is assumed that the access from the DMA engine 311 to the register 321 of the core 32 is completed within a fixed time.

Further, in the above-mentioned system 1, in principle, it is assumed that the DMA transfer is performed in the order set in the DMA descriptor 312. On the other hand, since the plurality of DMA descriptors 312 are processed in parallel by the plurality of DMA engines 311, the execution order is not guaranteed. Further, even in the case of DMA transfer using the same DMA descriptor 312, if there is an address conflict between the two DMA transfers, the execution order is not guaranteed in principle. However, the execution order can be guaranteed by setting the dependency flag, the write request completion time valid, the write request completion time, and the like.

Next, with reference to FIG. 3, an example of the operation when the system 1 performs DMA transfer using the same DMA descriptor 312 will be described.

FIG. 3 illustrates a case where three DMA transfers are performed. Specifically, in the DMA transfer at the top of FIG. 3, data is read from the transfer source address "0x1000" and the data is written to the transfer destination address "0x2000". Further, in the second DMA transfer in FIG. 3, the data is read from the transfer source address "0x2000" and the data is written to the transfer destination address "0x3000". Further, in the DMA transfer at the bottom of FIG. 3, the data is read from the transfer source address "0x6000" and the data is written to the transfer destination address "0x7000".

Further, in the example shown in FIG. 3, the top DMA descriptor 312 includes "0x1" indicating that the write request completion time is valid and "0x100" that indicates the write request completion time. That is, in the top DMA descriptor 312, the write request completion time is set and the write request completion time is valid. Further, the second DMA descriptor 312 contains "0x1" indicating that the dependency flag is set. Due to the above configuration, the DMA engine 311 performs the DMA transfer based on the second DMA descriptor 312 from the start of the DMA transfer based on the first DMA descriptor 312 until the write request completion time elapses. Wait for the start. That is, the DMA engine 311 starts the DMA transfer based on the second DMA descriptor 312 after the write request completion time elapses after starting the DMA transfer based on the first DMA descriptor 312. On the other hand, the lowermost DMA descriptor 312 contains "0x0" indicating that the dependency flag is not set. Therefore, the DMA engine 311 starts the lowermost DMA transfer even before the write request completion time elapses after starting the uppermost DMA transfer. As a result of the above, for example, the lowest DMA transfer is started earlier than the second DMA transfer.

As described above, in the system 1, the execution order is guaranteed for the DMA transfer having the dependency that requires the guarantee of the execution order, while the DMA transfer without the dependency is not waited unnecessarily. DMA transfer can be started.

Subsequently, an example of the operation of the system 1 will be described with reference to FIG. FIG. 4 describes a case where a DMA transfer having a dependency for which the execution order is to be guaranteed and a DMA transfer without a dependency for which the execution order is not required to be guaranteed are performed.

Referring to FIG. 4, the processor 21 makes necessary settings for the same DMA descriptor 312. Specifically, the processor 21 sets to instruct the preceding DMA transfer (step S101) and sets to instruct the subsequent DMA transfer (step S102) (step S103). The processor 21 makes settings including the write request completion time valid and the write request completion time when making the preceding settings. Further, the processor 21 makes a setting including setting a dependency flag when setting the step S102 among the subsequent settings. Further, the processor 21 makes a setting including not setting the dependency flag when setting the step S103 among the subsequent settings.

When the DMA descriptor 312 is set, the DMA engine 311 of the acceleration processor 3 starts the DMA transfer based on the DMA descriptor 312 instructing the preceding DMA transfer (step S201). The DMA transfer is performed by issuing a DMA request and transferring data from the transfer source indicated by the DMA descriptor 312 to the transfer destination. Then, after the data transfer is completed, the DMA transfer is completed.

Further, the DMA engine 311 responds to step S102 in which the dependency flag is set because the write request completion time is set in the DMA descriptor 312 instructing the preceding DMA transfer and the write request completion time is valid. Waits for the start of the DMA transfer until the write request completion time elapses. Then, the DMA engine 311 starts the DMA transfer according to the step S102 after the write request completion time has elapsed since the preceding DMA transfer was started (step S202). By such an operation, the DMA engine 311 starts the subsequent DMA transfer according to the step S102 after the preceding DMA transfer according to the step S101 is completed. On the other hand, the DMA engine 311 starts the DMA transfer according to the step S103 in which the dependency flag is not set without waiting for the lapse of the write request completion time (step S203). As a result, in the case shown in FIG. 4, the DMA transfer in step S203 starts earlier than the DMA transfer in step S202.

In addition to the method described in this embodiment, there are a confirmation method by polling (see FIG. 5) and a confirmation method by a DMA transfer completion interrupt (see FIG. 6) as a method of guaranteeing the execution order of the two DMA transfers. ..

As shown in FIG. 5, in the case of the confirmation method by polling, the processor 21 performs polling to confirm the end of the preceding DMA transfer. Therefore, the processor 21 is occupied to confirm the completion of the DMA transfer from the start of the first DMA transfer to the start of the second DMA transfer.

Further, as shown in FIG. 6, in the case of the confirmation method using the DMA transfer completion interrupt, the acceleration processor 3 notifies the host PC 2 of the DMA transfer completion interrupt when the DMA transfer is completed. In the host PC 2, when the DMA transfer completion interrupt is detected, the processor 21 starts the interrupt handler process. At that time, the processor 21 needs to save the process and start a new process that had been performed before the interrupt was detected. Therefore, the latency until the DMA transfer completion notification, the interrupt detection of the host PC, and the subsequent start of the DMA transfer tends to be deteriorated. Further, since the DMA transfer completion interrupt can only know that the DMA transfer request issuance has been completed from the DMA engine 311 and the amount of information is small, which DMA descriptor 312 has been completed and whether the data transfer has been successful. It is necessary to confirm. As described above, even with the confirmation method using the DMA transfer completion interrupt, problems such as poor latency will occur.

As described above, in the case of the confirmation method by polling or the confirmation method by the DMA transfer completion interrupt, problems such as a long occupancy time of the processor 21 will occur. On the other hand, as shown in FIG. 4, in the case of the system 1 described in the present embodiment, the execution order of the DMA transfer can be guaranteed without occupying the processor 21 more than necessary. That is, the processor resources can be used efficiently. Further, by setting the dependency flag, it is possible to start the DMA transfer without waiting for the lapse of the write request completion time for the DMA transfer having no dependency.

As described above, the system 1 in the present embodiment has a DMA descriptor 312 including a dependency flag and a DMA engine 311. With such a configuration, the DMA engine 311 waits for the execution of the succeeding DMA transfer, which is dependent on the preceding DMA transfer and requires the guarantee of the execution order, and is independent of the preceding DMA transfer. Can be executed without waiting. As a result, it is possible to guarantee the execution order of the DMA transfer having a dependency, and it is possible to prevent the start of the transfer from being delayed until the DMA transfer having no dependency.

Further, since the DMA descriptor 312 includes the dependency flag, it is possible to have a dependency relationship between a plurality of DMA transfers regardless of the address relationship, such as the transfer destination address and the transfer source address overlapping. It becomes. As a result, it becomes possible to perform appropriate control according to the dependency between DMA transfers. For example, according to the system 1 described in the present embodiment, by setting the dependency flag, it is possible to forcibly wait for the completion of data transfer without performing address comparison. As a result, for example, it is possible to start DMA transfer after completing the flag setting of different address positions.

In this embodiment, a case where the execution order of two DMA transfers is guaranteed has been described. However, the DMA transfer for which the system 1 guarantees the execution order is not limited to two. The system 1 can be configured to guarantee the execution order of three or more DMA transfers.

Further, in the present embodiment, an example of determining whether or not the software is a DMA transfer for which the execution order should be guaranteed, such as an address conflict between DMA transfers, has been described. However, hardware may be configured to compare addresses between DMA transfers.

Further, the system 1 shown in FIG. 1 is merely an example. The system 1 may have a plurality of processors 21 or a plurality of memories 33. Further, the number of DMA engines 311 and the number of DMA descriptors 312 included in the DMA unit 31 are not particularly limited.

[Second Embodiment]
Next, the first embodiment of the present invention will be described with reference to FIGS. 7 to 9. FIG. 7 is a diagram showing an example of the configuration of the DMA descriptor 412. FIG. 8 is a diagram showing an example of DMA transfer executed by the system 1. FIG. 9 is a sequence diagram showing an example of the operation of the system 1.

In the second embodiment, a case where there are a plurality of control means (hereinafter referred to as a requester) for setting when executing the DMA transfer will be described. Specifically, in the case of the present embodiment, in addition to the processor 2, the core 32 (core 32-0, core 32-1, core 32-2, core 32-3) also sets the DMA descriptor 412. As will be described later, the DMA descriptor 412 in the present embodiment has a requester identifier used in addition to the configuration of the DMA descriptor 312 described in the first embodiment. Since the DMA descriptor 412 has the requester identifier used, the DMA engine 311 can wait for the DMA transfer by the request from another requester when one requester is executing the DMA transfer with the dependency.

The system 1 in the present embodiment has a host PC 2 and an acceleration processor 3 as in the first embodiment. In the case of the present embodiment, in addition to the processor 21 of the host PC 2, the core 32 (core 32-0, core 32-1, core 32-2, core 32-3) of the acceleration processor 3 is also the DMA descriptor 412. You can make settings. Hereinafter, a configuration characteristic of the present embodiment will be described.

FIG. 7 shows an example of the DMA descriptor 412 set by the processor 21 and the core 32. Referring to FIG. 7, the DMA descriptor 412 has a used requester identifier which is identification information for identifying the requester, in addition to the configuration of the DMA descriptor 312 described in the first embodiment.

The requester identifier used is an identifier for identifying the requester in which the DMA descriptor 412 is set. When setting the DMA descriptor 412, the requester such as the processor 21 or the core 32 sets the identifier assigned to itself in advance as the used requester identifier. That is, the requester identifier used is different depending on, for example, the case where the processor 21 sets the DMA descriptor 412 and the case where the core 32-0 sets the DMA descriptor 412.

The DMA transfer based on the DMA descriptor 412 in which the used requester identifier is set is started after waiting for the completion of the dependent DMA transfer by the request from another requester to which the same used requester identifier is not assigned. .. That is, in the case of the DMA descriptor 412 in which the requester identifier to be used is set, the DMA transfer based on the DMA descriptor 412 is started after the DMA transfer having the preceding dependency is completed. The completion of the DMA transfer having the preceding dependency may be determined based on the completion flag of the preceding DMA transfer. Further, when the used requester identifier is not set, the DMA transfer is started without waiting even when the DMA transfer having the dependency is executed by the request from another requester.

Next, with reference to FIG. 8, an example of the operation when the system 1 performs DMA transfer using the same DMA descriptor 412 will be described.

FIG. 8 illustrates a case where four DMA transfers are performed. Specifically, the first, second, and lowest DMA transfers in FIG. 8 are the same as the DMA transfers already described with reference to FIG. On the other hand, in the third DMA transfer in FIG. 8, the data is read from the transfer source address "0x4000" and the data is written to the transfer destination address "0x5000".

In the example shown in FIG. 8, the requester identifier "0x1" to be used is set in the DMA descriptor 412 at the top, the second, and the bottom. Therefore, the 1st, 2nd, and 1st DMA descriptors 412 are set by the same requester. On the other hand, the requester identifier used "0x2" is set in the third DMA descriptor 412. Therefore, the third DMA descriptor 412 is set by a requester different from the first, second, and lower DMA descriptors 412.

In such a situation shown in FIG. 8, the DMA transfer based on the third DMA descriptor 412 having a different used requester identifier is started after the DMA transfer having the preceding dependency is completed. Here, in the case of FIG. 8, there are the first and second DMA transfers as the DMA transfers having the preceding dependency relationship. Therefore, the DMA engine 311 starts the DMA transfer based on the third DMA descriptor 412 having a different requester identifier used after the DMA transfer based on the first and second DMA descriptors 412 is completed. For example, the DMA engine 311 starts the DMA transfer based on the third DMA descriptor 412 after the DMA transfer based on the second DMA descriptor 412 is completed. As a result, the DMA engine 311 can execute the request from another requester without disturbing the order guarantee of the request being executed.

As described above, in the case of the present embodiment, when the requester identifier to be used is set, the DMA transfer based on the DMA descriptor 412 set by another requester is started after the DMA transfer having the dependency is completed. Thus, for example, if the processor 21 sets the dependent DMA transfer to the DMA descriptor 412 and then the core 32-0 sets the DMA transfer to the DMA descriptor 412, the DMA engine 311 is set by the processor 21. After the completion of the DMA transfer having the dependency, the DMA transfer set by the core 32-0 is performed. In this way, by not interfering with the DMA transfer of other requesters, it is possible to guarantee the execution order of the DMA transfer even when there are a plurality of requesters.

Subsequently, an example of the operation of the system 1 in the second embodiment will be described with reference to FIG. In FIG. 9, in addition to the case described with reference to FIG. 4, a case where the setting of the DMA descriptor 412 from the core 32 is added will be described.

Referring to FIG. 9, the processor 21 sets to instruct the preceding DMA transfer (step S101) and sets to instruct the succeeding DMA transfer (step S102) (step S103). Further, the core 32 is set to instruct DMA transfer after the setting of step S101 by the processor 21 (step S301).

When the DMA descriptor 412 is set, the DMA engine 311 of the acceleration processor 3 starts the DMA transfer based on the DMA descriptor 412 instructing the preceding DMA transfer (step S201). The DMA transfer is performed by issuing a DMA request and transferring data from the transfer source indicated by the DMA descriptor 412 to the transfer destination. Then, after the data transfer is completed, the DMA transfer is completed.

Further, the DMA engine 311 responds to step S102 in which the dependency flag is set because the write request completion time is set in the DMA descriptor 412 instructing the preceding DMA transfer and the write request completion time is valid. Waits for the start of the DMA transfer until the write request completion time elapses. Then, after the write request completion time has elapsed, the DMA engine 311 starts the DMA transfer according to step S102 (step S202). As a result, after the preceding DMA transfer is completed, the DMA engine 311 starts the DMA transfer according to step S102.

Further, since the DMA descriptor 412 having a different requester identifier from the preceding DMA transfer is registered, the DMA engine 311 waits for the start of the DMA transfer according to step S301 until the preceding DMA transfer having a dependency is completed. .. In the case shown in FIG. 9, the DMA engine 311 waits for the start of the DMA transfer according to the step S301 until the DMA transfer in the step S202 is completed. Then, the DMA engine 311 starts the DMA transfer according to the step S301 after the preceding DMA transfer having the dependency is completed (for example, after the completion flag is set in the DMA transfer in the step S202). As a result, it is possible to start DMA transfer in response to a request from another requester without disturbing the order guarantee of the request being executed.

Further, the DMA engine 311 starts the DMA transfer according to the step S103 in which the dependency flag is not set without waiting for the lapse of the write request completion time (step S203).

As described above, the system 1 in the present embodiment has a DMA descriptor 412 including a requester identifier used and a DMA engine 311. With such a configuration, the DMA engine 311 can start the subsequent DMA transfer registered by another requester after the series of DMA transfers having the preceding dependency is completed. This makes it possible for the acceleration processor 3 to guarantee the execution order even when different requesters perform DMA transfers. If it is not necessary to guarantee the execution order of DMA transfers, if the requester identifier used is not set, DMA transfers can be continuously performed without waiting even between DMA transfers using the same DMA descriptor 412. ..

In the case of the second embodiment, various modifications can be adopted as in the first embodiment.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 10 is a block diagram showing an example of the configuration of the data transfer device 5.

Referring to FIG. 10, the data transfer device 5 has a transfer execution means 51. The transfer executing means 51 is set with transfer information for performing DMA (Direct Memory Access) transfer, and performs DMA transfer based on the set transfer information. Here, the transfer information includes identification information indicating a requester for which the transfer information is set. After the DMA transfer based on the transfer information is completed, the transfer executing means 51 starts the DMA transfer based on the transfer information registered by another requester different from the requester registered the transfer information.

As described above, the data transfer device 5 in the present embodiment has a transfer execution means 51 that performs DMA transfer based on the transfer information. In addition, the transfer information includes identification information indicating a requester for which the transfer information is set. With such a configuration, the transfer executing means 51 can start the DMA transfer based on the registration from another requester after the DMA transfer based on the registration from one requester is completed. As a result, for example, even if a DMA transfer having a dependency is performed by registration from a certain preceding requester, the DMA transfer based on the registration from another requester is waited for the completion of the DMA transfer having the dependency. Can be started. As a result, it is possible to guarantee the execution order even when different requesters perform DMA transfer.

Further, the above-mentioned data transfer device 5 can be realized by incorporating a predetermined program into the data transfer device 5. Specifically, in the program according to another embodiment of the present invention, transfer information for performing DMA (Direct Memory Access) transfer is set in the data transfer device, and transfer is performed based on the set transfer information. The execution means is realized, and the transfer information includes identification information indicating a requester for which the transfer information is set, and the transfer execution means registers the transfer information after the DMA transfer based on the transfer information is completed. It is a program to start DMA transfer based on the transfer information registered by another requester different from the requester.

Further, in the data transfer method executed by the data transfer device 5 described above, transfer information for the data transfer device to perform DMA (Direct Memory Access) transfer is set, and DMA transfer is performed based on the set transfer information. The transfer information includes identification information indicating the requester for which the transfer information is set, and after the DMA transfer based on the transfer information is completed, another requester different from the requester that registered the transfer information is registered. It is a method of starting DMA transfer based on the transferred transfer information.

Even the invention of the program or the data transfer method having the above-mentioned configuration can achieve the above-mentioned object of the present invention because it has the same operation as the above-mentioned data transfer device 5.

<Additional Notes>
Part or all of the above embodiments may also be described as in the appendix below. Hereinafter, the outline of the data transfer device and the like in the present invention will be described. However, the present invention is not limited to the following configuration.

(Appendix 1)
Transfer information for performing DMA (Direct Memory Access) transfer is set, and a transfer execution means for performing DMA transfer based on the set transfer information is provided.
The transfer information includes identification information indicating a requester for which the transfer information is set.
The transfer executing means is a data transfer device that starts a DMA transfer based on the transfer information registered by another requester different from the requester registered the transfer information after the DMA transfer based on the transfer information is completed.
(Appendix 2)
The data transfer device according to Appendix 1, wherein the data transfer device is described.
The transfer executing means is a data transfer device that, when the identification information is not set, starts a subsequent DMA transfer registered by another requester without waiting for the completion of the preceding DMA transfer.
(Appendix 3)
The data transfer device according to Supplementary Note 1 or Supplementary Note 2.
The transfer information includes order-required guarantee information indicating that the transfer is a DMA transfer for which it is necessary to guarantee the execution order.
When it is determined that it is necessary for the transfer executing means to guarantee the execution order based on the order-required guarantee information, after the DMA transfer for which the execution order is guaranteed based on the setting information is completed, the transfer execution means is completed. A data transfer device that starts a DMA transfer based on the transfer information registered by another requester different from the requester that registered the transfer information.
(Appendix 4)
The data transfer device according to Appendix 3,
The transfer information includes dependency information indicating a dependency relationship with other DMA transfers as the order guarantee information.
The transfer executing means is a data transfer device that starts a DMA transfer based on the transfer information registered by another requester after the DMA transfer having a dependency determined based on the dependency information is completed.
(Appendix 5)
The data transfer device according to Appendix 4, wherein the data transfer device is described.
The transfer executing means is a data transfer device that starts a DMA transfer based on the transfer information registered by another requester after a completion flag is set for a DMA transfer having a dependency determined based on the dependency information.
(Appendix 6)
The data transfer device according to any one of Supplementary note 1 to Supplementary note 5.
The data transfer device has a plurality of requesters which are setting means for setting the transfer information.
The identification information is a data transfer device having a different identifier for each requester.
(Appendix 7)
The data transfer device
Transfer information for performing DMA (Direct Memory Access) transfer is set, and DMA transfer is performed based on the set transfer information.
The transfer information includes identification information indicating a requester for which the transfer information is set.
A data transfer method for starting a DMA transfer based on the transfer information registered by another requester different from the requester registered the transfer information after the DMA transfer based on the transfer information is completed.
(Appendix 8)
The data transfer method described in Appendix 7
A data transfer method for starting a subsequent DMA transfer registered by another requester without waiting for the completion of the preceding DMA transfer when the identification information is not set.
(Appendix 9)
For data transfer equipment
Transfer information for performing DMA (Direct Memory Access) transfer is set, and a transfer execution means for performing DMA transfer is realized based on the set transfer information.
The transfer information includes identification information indicating a requester for which the transfer information is set.
The transfer executing means is a program that starts a DMA transfer based on the transfer information registered by another requester different from the requester registered the transfer information after the DMA transfer based on the transfer information is completed.
(Appendix 10)
The program described in Appendix 9
The transfer executing means is a program that, when the identification information is not set, starts a subsequent DMA transfer registered by another requester without waiting for the completion of the preceding DMA transfer.

In addition, the program described in each of the above-described embodiments and appendices may be stored in a storage device or recorded in a recording medium readable by a computer. For example, the recording medium is a portable medium such as a flexible disk, an optical disk, a magneto-optical disk, and a semiconductor memory.

Although the present invention has been described above with reference to each of the above embodiments, the present invention is not limited to the above-described embodiments. Various changes that can be understood by those skilled in the art can be made to the structure and details of the present invention within the scope of the present invention.

1 system 2 host PC
21 Processor 22 Host memory 3 Acceleration processor 31 DMA unit 311 DMA engine 312 DMA descriptor 32 Core 321 Register 322 Computer 33 Memory 412 DMA descriptor 5 Data transfer device 51 Transfer execution means

Claims (8)

Transfer information for performing DMA (Direct Memory Access) transfer is set, and a transfer execution means for performing DMA transfer based on the set transfer information is provided.
The transfer information includes identification information indicating a requester for which the transfer information is set.
After the DMA transfer based on the transfer information is completed, the transfer execution means starts the DMA transfer based on the transfer information registered by another requester different from the requester registered the transfer information .
If the identification information is not set, the transfer executing means starts the subsequent DMA transfer registered by another requester without waiting for the completion of the preceding DMA transfer.
Data transfer device. The data transfer device according to claim 1 .
The transfer information includes order-required guarantee information indicating that the transfer is a DMA transfer for which it is necessary to guarantee the execution order.
If it is determined that it is necessary for the transfer execution means to guarantee the execution order based on the order guarantee information, after the DMA transfer that requires the guarantee of the execution order based on the transfer information is completed, the transfer execution means completes. A data transfer device that starts a DMA transfer based on the transfer information registered by another requester different from the requester that registered the transfer information. The data transfer device according to claim 2 .
The transfer information includes dependency information indicating a dependency relationship with other DMA transfers as the order guarantee information.
The transfer executing means is a data transfer device that starts a DMA transfer based on the transfer information registered by another requester after the DMA transfer having a dependency determined based on the dependency information is completed. The data transfer device according to claim 3 .
The transfer executing means is a data transfer device that starts a DMA transfer based on the transfer information registered by another requester after a completion flag is set for a DMA transfer having a dependency determined based on the dependency information. The data transfer device according to any one of claims 1 to 4 .
The data transfer device has a plurality of requesters which are setting means for setting the transfer information.
The identification information is a data transfer device having a different identifier for each requester. The data transfer device
Transfer information for performing DMA (Direct Memory Access) transfer is set, and DMA transfer is performed based on the set transfer information.
The transfer information includes identification information indicating a requester for which the transfer information is set.
After the DMA transfer based on the transfer information is completed, the DMA transfer based on the transfer information registered by another requester different from the requester registered the transfer information is started .
If the identification information is not set, the subsequent DMA transfer registered by another requester is started without waiting for the completion of the preceding DMA transfer.
Data transfer method. For data transfer equipment
Transfer information for performing DMA (Direct Memory Access) transfer is set, and a transfer execution means for performing DMA transfer is realized based on the set transfer information.
The transfer information includes identification information indicating a requester for which the transfer information is set.
After the DMA transfer based on the transfer information is completed, the transfer execution means starts the DMA transfer based on the transfer information registered by another requester different from the requester registered the transfer information .
If the identification information is not set, the transfer executing means starts the subsequent DMA transfer registered by another requester without waiting for the completion of the preceding DMA transfer.
program. Transfer information for performing DMA (Direct Memory Access) transfer is set, and a transfer execution means for performing DMA transfer based on the set transfer information is provided.
The transfer information includes identification information indicating a requester for which the transfer information is set.
After the DMA transfer based on the transfer information is completed, the transfer execution means starts the DMA transfer based on the transfer information registered by another requester different from the requester registered the transfer information.
The transfer information includes order-required guarantee information indicating that the transfer is a DMA transfer for which it is necessary to guarantee the execution order.
When it is determined that it is necessary for the transfer execution means to guarantee the execution order based on the order guarantee information, after the DMA transfer for which the execution order is guaranteed based on the transfer information is completed, the transfer execution means is completed. A data transfer device that starts a DMA transfer based on the transfer information registered by another requester different from the requester that registered the transfer information .

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