JP6519343B2 - Data processor - Google Patents

Description

  The present invention relates to a data processing apparatus comprising a plurality of processors.

  In order to execute processing efficiently in parallel by multiple processors, it is important to realize synchronization processing between processors, that is, barrier synchronization processing and mutual exclusion control processing at high speed. For example, Patent Document 1 improves the efficiency of barrier synchronization processing by providing each processor with a register for holding synchronization wait states of all processors and a register for notifying another processor of its own synchronization wait state. Technology has been disclosed.

JP, 2013-137833, A

  By the way, in recent years, it has been proposed to realize a configuration suitable for stream data processing by connecting a plurality of data processing devices by a bidirectional slotted bus. In this configuration, the write processing to the shared memory and the read processing from the shared memory are accessed through different paths. Therefore, it is difficult to maintain coherency, that is, consistency between write processing and read processing. Also, the slotted bus is a bus that can cause a delay. Therefore, due to the influence of the delay due to the slotted bus, there is a possibility that the flag is set and the synchronization waiting state is entered even though the process of writing the data to the shared memory is not completed. Therefore, there is a possibility that the processor may start the next processing cycle before the other processors complete the processing to the synchronization point, for example, before completing the write processing to the shared memory. In such a case, normal barrier synchronization processing can not be realized.

  Therefore, the present invention prevents the processor from waiting for synchronization before the write process to the shared memory is completed even if the write process from the processor to the shared memory is performed via a bus that may cause a delay. To provide a data processing apparatus capable of realizing normal synchronous processing.

  According to the data processing apparatus of the present invention, the shared memory is shared by a plurality of processors. The flag storage unit stores a write flag indicating that the processor has completed processing up to the synchronization point, and a plurality of flag storage units are provided in association with each processor. The access speed to the flag storage unit of the processor is faster than the access speed to the shared memory. A data write bus is a bus used by a processor to write data to a shared memory, which is shared by multiple processors. The data write bus is a bus that can cause a delay. The flag write bus is a bus for writing a write flag in the flag storage unit. Then, according to the data processing device, the data write bus and the flag write bus are made common, and the write flag is written to the flag storage unit after data is written to the shared memory.

  According to this configuration, before the processing to the synchronization point of the processor is completed, for example, before the data is written to the shared memory, the write flag indicating that the processing to the synchronization point is completed is written. It can be avoided. That is, the write flag is written after the data is written to the shared memory. Therefore, even if the write process from the processor to the shared memory is performed via the data write bus which may cause a delay, the processor starts the next processing cycle before the write process to the shared memory is completed. Can be avoided, and a normal synchronization process can be realized.

Block diagram schematically showing a configuration example of a data processing apparatus according to the first embodiment Block diagram schematically showing a comparative configuration example of the data processing apparatus Timing flow chart showing the relationship between data write processing and flag write processing according to a comparative configuration example Timing flow chart showing the relationship between data write processing and flag write processing according to the present embodiment Block diagram schematically showing a configuration example of a data processing apparatus according to the second embodiment A block diagram schematically showing a configuration example of a flag write information prefetch circuit Diagram showing an example of delayed output of flag write command information Block diagram schematically showing a configuration example of a data processing apparatus according to the third embodiment A block diagram schematically showing a configuration example of a flag write information prefetch circuit Block diagram schematically showing a configuration example of a data processing apparatus according to the fourth embodiment Block diagram schematically showing a configuration example of a data processing apparatus according to the fifth embodiment Block diagram schematically showing a configuration example of a data processing apparatus according to the sixth embodiment Block diagram schematically showing a configuration example of a data processing apparatus according to the seventh embodiment Diagram showing an example of processor state stored in the state storage unit Diagram showing an example of permission conditions stored in the condition storage unit Block diagram schematically showing a configuration example of a data processing apparatus according to the eighth embodiment

Hereinafter, a plurality of embodiments of the data processing apparatus will be described with reference to the drawings. In each embodiment, substantially the same elements are denoted by the same reference numerals, and the description thereof will be omitted.
First Embodiment
The data processing apparatus 10 illustrated in FIG. 1 includes a plurality of, in this case, four processors 11a to 11d, a shared memory 12, a data write bus 13, a data read bus 14, and a plurality of, in this case, four flag storages. The units 15a to 15d and the flag write bus 16 are provided. The processors 11 a to 11 d perform a process of writing data to the shared memory 12 via the data write bus 13 and a process of reading data from the shared memory 12 via the data read bus 14. Further, the processors 11a to 11d can perform write processing and read processing on the flag storage units 15a to 15d through the dedicated interfaces 17a to 17d.

  When writing data to the shared memory 12, the processors 11a to 11d output the data to be written and also write data command information instructing to write the data to the shared memory 12, and write flags to the flag storage units 15a to 15d. To output various information such as flag write instruction information for instructing to write. In this case, the processors 11a to 11d output the flag write instruction information after outputting the data write instruction information. The access speed to the flag storage units 15a to 15d of the processors 11a to 11d is higher than the access speed to the shared memory 12 of the processors 11a to 11d.

  The shared memory 12 is shared by a plurality of processors 11a to 11d. The data write bus 13 is a bus used by the plurality of processors 11 a to 11 d to write data to the shared memory 12. The data write bus 13 is shared by a plurality of processors 11a to 11d. The data write bus 13 is an example of a bus that may cause a delay. The data read bus 14 is a bus used by the plurality of processors 11 a to 11 d to read data from the shared memory 12. The data read bus 14 is shared by a plurality of processors 11 a to 11 d.

  The flag storage units 15 a to 15 d are storage units that store a write flag indicating that the processors 11 a to 11 d have written data to the shared memory 12. The flag storage units 15a to 15d are configured by, for example, registers. The flag storage units 15a to 15d are provided in association with the plurality of processors 11a to 11d, respectively. The write flag is, for example, a flag indicating that processing up to a synchronization point set in advance based on the synchronization condition is completed. The processors 11a to 11d corresponding to the flag storage units 15a to 15d in which the write flag is written transition from the state before the data writing to the synchronization waiting state. The pre-data write state is the state prior to execution of the data write process to the shared memory 12, that is, the process to the synchronization point is not completed. The synchronization waiting state is the state in which the process of writing data to the shared memory 12 is completed, that is, the process up to the synchronization point is completed, and the next processing cycle can be started. When all the processors 11a to 11d designated by the synchronization condition are in the synchronization waiting state, that is, when all the processors 11a to 11d designated by the synchronization condition complete the processing up to the synchronization point, the data processing apparatus 10 Transfer to the next processing cycle.

  The flag write bus 16 is a bus for writing a write flag in the flag storage units 15a to 15d. The data processor 10 has a configuration in which the data write bus 13 and the flag write bus 16 are shared. In this case, the data write bus 13 and the flag write bus 16 are shared between the processors 11 a to 11 d and the branch point P. Then, branching from the branch point P, the data write bus 13 is connected to the shared memory 12, and the flag write bus 16 is connected to the flag storage units 15a to 15d.

  In the configuration illustrated in FIG. 2, the data write bus 113 is not provided with the flag write bus shared. In this configuration, the processors 111a to 111d write the flags in the flag storage units 115a to 115d via the dedicated interfaces 117a to 117d. Therefore, as illustrated in FIG. 3, when a delay occurs in the data write bus 113, a write flag may be written to the flag storage units 115a to 115d before the writing of data to the common memory 112 is completed. .

  On the other hand, according to the data processing apparatus 10, the data write bus 13 and the flag write bus 16 are made common, and the processors 11a to 11d transmit the data write bus 13 as shown in FIG. Data write command information is output, and subsequently, flag write command information is output. That is, the data write command information is output first on the shared bus, and then the flag write command information is output. Therefore, the process of writing data to the shared memory 12 is performed first, and then the flag storage units 15a to 15d, that is, the flag storage units 15a to 15d corresponding to the processor that performed the writing process are stored. A write process is performed.

  According to the data processing apparatus 10, the write flag is written to the flag storage units 15a to 15d before the data is written to the shared memory 12, that is, the processors 11a to 11d can start the next processing cycle. It is possible to avoid Therefore, even when the processing of writing data from the processors 11a to 11d to the shared memory 12 is performed via the data writing bus 13 which may cause a delay, the processors 11a to 11d are completed before the writing processing on the shared memory 12 is completed It can be avoided that 11d enters the synchronization waiting state, and normal synchronization processing can be realized.

Second Embodiment
The data processor 20 illustrated in FIG. 5 includes flag write information prefetch circuits 21a to 21d as an example of a dedicated circuit. Hereinafter, the flag write information prefetching circuits 21a to 21d will be simply referred to as prefetching circuits 21a to 21d. The prefetch circuits 21a to 21d are provided in association with the plurality of processors 11a to 11d, respectively. The dedicated interfaces 17a to 17d are respectively branched and connected to the prefetching circuits 21a to 21d. Next, a configuration example of the prefetch circuits 21a to 21d will be described. The configurations of the prefetching circuits 21a to 21d are the same, so here, the configuration of the prefetching circuit 21a corresponding to the processor 11a will be described. As illustrated in FIG. 6, the prefetch circuit 21 a includes an information storage unit 22 and a match determination unit 23. The information storage unit 22 and the match determination unit 23 may be realized virtually by software, may be realized by hardware, or may be realized by a combination of software and hardware.

  The information storage unit 22 stores information that the processor 11 a outputs to the data write bus 13 when writing data to the shared memory 12. In this case, when writing data to the shared memory 12, the processor 11 a outputs address information that specifies the write destination of the data in the shared memory 12. This address information is output at least after the data write instruction information is output. Then, the information storage unit 22 acquires address information from the processor 11a via the dedicated interface 17a, and stores the address information in the storage area 22a provided in the storage medium.

  The match determination unit 23 includes a determination processing unit 23a and a flag writing processing unit 23b. The match determination unit 23 determines whether the address information obtained from the data write bus 13 matches the address information stored in the information storage unit 22 by the determination processing unit 23a. Then, if the two pieces of information match, the match determination unit 23 writes the write flag in the flag storage unit 15a by the flag write processing unit 23b.

  According to the data processing apparatus 20, the information that the processors 11a to 11d output to the data writing bus 13 when writing data to the shared memory 12, in this case, writing to the flag storage units 15a to 15d using address information Determine whether to write the flag. Therefore, flag write command information can be made unnecessary. Further, as illustrated in FIG. 7, in the configuration in which the flag write command information is output following the data write command information, for example, the data write command information from another processor is interrupted after the data write command information is output. The output of the write command information may be delayed. According to the data processing device 20, the write processing of the write flag can be performed regardless of the flag write command information, and therefore, the delay due to the interrupt does not occur.

Third Embodiment
The data processing device 30 illustrated in FIG. 8 includes flag write information prefetching circuits 31 a to 31 d as an example of a dedicated circuit. Hereinafter, the flag write information prefetching circuits 31a to 31d are simply referred to as prefetching circuits 31a to 31d. The prefetch circuits 31a to 31d are provided in association with the plurality of processors 11a to 11d, respectively. Next, a configuration example of the prefetching circuits 31a to 31d will be described. The configuration of the prefetching circuits 31a to 31d is the same, so the configuration of the prefetching circuit 31a corresponding to the processor 11a will be described here. As illustrated in FIG. 9, the prefetch circuit 31 a includes an information storage unit 32, a match determination unit 33, and an information monitoring unit 34. The information storage unit 32, the match determination unit 33, and the information monitoring unit 34 may be virtually realized by software, may be realized by hardware, or may be realized by a combination of software and hardware. . The functions of the information storage unit 32 and the match determination unit 33 are the same as those of the information storage unit 22 and the match determination unit 23 of the second embodiment.

  The information monitoring unit 34 monitors the write command [2] and the write command [1] continuously output by the processor 11 a when writing data in the shared memory 12. In this case, the information monitoring unit 34 includes storage areas 34a and 34b provided in the storage medium. The information monitoring unit 34 stores the write command [2] obtained from the processor 11a first, specifically, the “data write command information” in the storage area 34a, and the write command [1] obtained after the data write command information. Specifically, "flag write command information" is stored in the storage area 34b. If both of the write commands [1] and [2] are “data write command information”, that is, if “data write command information” is continuously output, “data write to the storage area 34 b is performed. Command information is stored.

  The information monitoring unit 34 determines whether the information stored in the storage area 34 b is “flag write instruction information”. Then, when the information stored in the storage area 34 b is “flag write instruction information”, the information monitoring unit 34 writes the immediately preceding write information [2], ie, the storage area 34 a. The data write command information stored in the data storage unit 32 is output to the information storage unit 32. The information storage unit 32 stores the data writing command information obtained from the information monitoring unit 34 in the storage area 32 a. The match determination unit 33 determines whether the data write command information obtained from the data write bus 13 matches the data write command information stored in the information storage unit 32 by the determination processing unit 33a. If the two pieces of information match, the match determination unit 33 writes the write flag in the flag storage unit 15a by the flag write processing unit 33b.

  In the present embodiment, the configuration for determining whether or not the data write command information matches is illustrated. However, whether or not the data processing device 30 matches other information, for example, source information specifying the processor that has issued the data write command information, address information specifying the data write destination in the shared memory 12, etc. It may be configured to determine whether to write the write flag based on the above.

  According to the data processing device 30, the information that the processors 11a to 11d continuously output to the data writing bus 13 when writing data to the shared memory 12, in this case, using the data writing command information and the flag writing command information It is possible to determine whether to write the write flag to the flag storage units 15a to 15d.

Fourth Embodiment
The data processing apparatus 40 illustrated in FIG. 10 includes an arbitration unit 41. The arbitration unit 41 may be realized by software, hardware or a combination of software and hardware. The arbitration unit 41 is an example of a priority unit, and in this case, is provided on the data write bus 13. When the arbitration unit 41 has a request for writing data to the shared memory 12 by the processors 11a to 11d that the arbitration unit 41 has and a request for writing data to the shared memory 12 by the processors that the other data processing devices 401 and 402 have. In addition, the data write request from the own device is prioritized over the data write request from the other device. Further, the arbitration unit 41 requests writing to the flag storage units 15a to 15d by its own processors 11a to 11d and requests the flag storage units 15a to 15d by processors of other data processing devices 401 and 402. When there is a conflict with the write request for the write flag, the flag write request from the own device is prioritized over the flag write request from the other device.

  When processing the respective requests in the order of occurrence, including the requests from the processors 11a to 11d of the own device and the requests from the processors of the other devices, between the data writing process of the own device and the flag writing process of the own device Requests from other devices may interrupt and cause delay. According to the data processing apparatus 40, the request from the own apparatus is prioritized over the request from the other apparatus. Therefore, it is possible to prevent the request from the other device from being interrupted between the data writing process of the own device and the flag writing process of the own device, and speeding up of the process can be achieved without causing a delay. The arbitration unit 41 may be provided separately from the data write bus 13.

Fifth Embodiment
The data processing apparatus 50 illustrated in FIG. 11 includes processing order storage units 51a to 51d. The processing order storage units 51a to 51d are provided in association with the flag storage units 15a to 15d, respectively. Further, the processing order storage units 51a to 51d are respectively provided in the flag storage units 15a to 15d. The processing order storage units 51a to 51d may be provided on storage media separate from the flag storage units 15a to 15d. The processing order storage units 51a to 51d store the order in which the write flags are written in the flag storage units 15a to 15d.

  According to the data processing device 50, it is possible to grasp on what order the data writing process of the processors 11a to 11d is completed based on the order information stored in the process order storage units 51a to 51d. This makes it possible to identify the processors 11a to 11d that can complete the data write process quickly. Therefore, for example, by allocating many processes to the processors 11a to 11d capable of completing the data write process quickly in the next process cycle, the speed of the entire process can be increased.

Sixth Embodiment
The data processor 60 illustrated in FIG. 12 includes time storage units 61a to 61d. The time storage units 61a to 61d are provided in association with the flag storage units 15a to 15d, respectively. Further, the time storage units 61a to 61d are respectively provided in the flag storage units 15a to 15d. The time storage units 61a to 61d may be provided on storage media separate from the flag storage units 15a to 15d. The time storage units 61a to 61d store the time when the write flag is written in the flag storage units 15a to 15d. The data processing apparatus 60 includes a timer (not shown) for measuring time. The time storage units 61a to 61d specify the time when the flag is written based on the timer.

  According to the data processing device 60, it can be grasped on what order the data writing process of the processors 11a to 11d is completed based on the time information stored in the time storage units 61a to 61d. Further, based on the time information stored in the time storage units 61a to 61d, it can be grasped how fast the data writing process of the processors 11a to 11d is completed. This makes it possible to more accurately identify the processors 11 a to 11 d that can complete the data write process quickly. Therefore, for example, by allocating many processes to the processors 11a to 11d capable of completing the data write process quickly in the next process cycle, the speed of the entire process can be increased.

Seventh Embodiment
The data processing device 70 illustrated in FIG. 13 includes a state storage unit 71 and a plurality of condition storage units 72a to 72d. The state storage unit 71 stores whether the processors 11 a to 11 d are in a state before writing data to the shared memory 12 or in a state after writing data. That is, as illustrated in FIG. 14, the state storage unit 71 determines the states of the processors 11a to 11d, that is, whether it is before data writing or not, based on, for example, the presence or absence of flag write command information obtained from the data write bus 13. Remember what it is. In FIG. 14, the state after writing the data is shown as the synchronization waiting state.

  The condition storage units 72a to 72d are provided in association with the flag storage units 15a to 15d, respectively. As exemplified in FIG. 15, the condition storage units 72a to 72d store permission conditions for permitting writing of the write flag to the flag storage units 15a to 15d. In the example shown in FIG. 15, the condition that writing of the write flag is permitted when the processor 11a is in the synchronization wait state, the processor 11b is in the pre-data writing state, the processor 11c is in the synchronization wait state, and the processor 11d is in the pre-data writing state. It has become.

  The data processing device 70 determines whether the actual states of the processors 11a to 11d stored in the state storage unit 71 match the permission conditions stored in the condition storage units 72a to 72d, respectively. Then, the data processing device 70 writes the write flag in the corresponding flag storage units 15a to 15d when the two pieces of information match.

  According to the data processing device 70, when the flag write command information is obtained, the write flags are not written in the flag storage units 15a to 15d immediately, but the actual states of the processors 11a to 11d match the predetermined permission conditions. , Write the write flag. As a result, the write flag can be written in consideration of not only the state of the processor itself but also the state of other processors, and a more accurate data write process can be performed as a whole system. The permission condition may be fixed, or may be dynamically changed according to, for example, the processing content or the degree of progress of the processing.

Eighth Embodiment
The data processing device 80 illustrated in FIG. 16 includes an access right granting unit 81. The access right granting unit 81 exclusively grants the processors 11a to 11d the access right to the shared memory 12. The access right granting unit 81 may be realized by software, hardware or a combination of software and hardware. The processors 11a to 11d request the access right granting unit 81 to grant the access right. The access right granting unit 81 that has received the request from the processors 11a to 11d grants the access right to any one of the requested processors 11a to 11d.

  The access right may be granted to, for example, the processor 11a to 11d requested first, or may be randomly selected from a plurality of requested processors 11a to 11d, or a plurality of requested. It may be given to the processor with the fastest processing among the processors 11a to 11d. The processors 11a to 11d can write data to the shared memory 12 on the condition that the access right is granted. Also, the processors 11 a to 11 d to which the access right is not given can not perform the process of writing data to the shared memory 12.

  According to the data processing device 80, the processors 11a to 11d capable of writing data to the shared memory 12 can be exclusively controlled. Therefore, the plurality of processors 11a to 11d can be prevented from simultaneously writing data to the shared memory 12, and the data writing process can be performed more accurately. Further, since the read / write process to the shared memory 12, that is, the memory access can be exclusively controlled, it is possible to guarantee the order of the read process and the write process.

(Other embodiments)
The present invention is not limited to the embodiments described above, and can be applied to various embodiments without departing from the scope of the invention.
The number of processors can be changed as appropriate. In addition, when the number of processors is changed, the number of peripheral elements such as the flag storage unit and the dedicated circuit may be appropriately changed according to the number. Moreover, you may implement combining several embodiment mentioned above suitably. The data processing apparatus according to the present embodiment is applicable to a stream data processing apparatus that processes stream data.

  In the drawings, 10 indicates a data processing apparatus, 11a to 11d indicate processors, 12 indicates a shared memory, 13 indicates a data write bus, 15a to 15d indicate flag storage units, and 16 indicates a flag write bus.

Claims (8)

With multiple processors (11a-11d),
Shared memory (12) shared by a plurality of said processors;
A bus used by the processor to write data to the shared memory, a data write bus (13) shared by a plurality of the processors;
A storage unit that stores a write flag indicating that the processor has completed processing up to the synchronization point, the processor can be accessed faster than the shared memory, and provided in association with each of the plurality of processors. A plurality of flag storage units (15a to 15d)
A flag write bus (16) for writing the write flag in the flag storage unit;
Equipped with
A data processing apparatus, wherein the data write bus and the flag write bus are made common, and the data write flag is written to the flag storage unit after data is written to the shared memory. The information storage unit (22) stores information to be output to the data write bus by the processor when writing data to the shared memory.
The said write flag is written in the said flag storage part, when the information which the said processor outputs to the said data write bus | bath, and the information memorize | stored in the said information storage part correspond. Data processing equipment. The processor continuously outputs data write instruction information instructing to write data to the shared memory and flag write instruction information instructing to write a write flag to the flag storage unit.
It further comprises an information monitoring unit (34) that monitors the data write command information and the flag write command information that the processor continuously outputs.
The data processing according to claim 2, wherein the information monitoring unit stores the data write instruction information in the information storage unit when the flag write instruction information is obtained following the data write instruction information. apparatus.   The data processing apparatus further comprises a priority unit (41) which prioritizes a request for writing data to the shared memory by the processor provided in itself over a request for writing data to the shared memory by a processor included in another data processing apparatus. The data processing apparatus according to any one of claims 1 to 3, wherein   The data processing apparatus according to any one of claims 1 to 4, further comprising a processing order storage unit (51a to 51d) that stores the order in which the write flag is written in the flag storage unit.   The data processing apparatus according to any one of claims 1 to 5, further comprising a time storage unit (61a to 61d) that stores the time when the write flag is written in the flag storage unit. A state storage unit (71) for storing whether the processor is in a state before or after writing data to the shared memory;
And a condition storage unit (72a to 72d) storing permission conditions for permitting the writing of the write flag to the flag storage unit;
When the state and the conditions for permitting the processor to the state storage unit stores match, the data processing apparatus according to claim 1, characterized in that the write flag in the flag storage unit is written.
The processor further comprises an access right grant unit (81) for granting the access right to the shared memory.
The data processing apparatus according to any one of claims 1 to 7, wherein the processor can write data to the shared memory on condition that the access right is granted. .

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