JP2011232917A - Semiconductor integrated circuit and request control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the number of request issues from a plurality of bus masters without increasing a logic scale.SOLUTION: A semiconductor integrated circuit 100 of the present invention comprises: a plurality of queues 330; a request distribution part 301 for distributing requests to any of a plurality of queues 330 on the basis of destination addresses for access of the requests which are issued from a plurality of bus masters 1 and 2; and a request selector 302 for issuing a request in a queue selected from the plurality of queues 330 to an external device 5.

Description

  The present invention relates to a semiconductor integrated circuit and a request control method, and more particularly to a request control method between a plurality of bus masters and an external device.

  FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor integrated circuit (LSI: Large Scale Integration) in the related art. Referring to FIG. 1, the LSI includes a CPU 10, a DMA controller 20, a plurality of slaves 60-1 and 60-2, and an address-dependent comparator 70 that are connected to each other via a system bus 40. The CPU 10 and the DMA (Direct Memory Access) controller 20 function as a bus master of the system bus 40, and external devices (example: memory, input / output) via slaves 60-1 and 60-2 exemplified by an external bus bridge circuit. A request is issued to an interface (I / O) (not shown). The address dependency comparator 70 confirms the address dependency relationship between the request issued to the external device and the request preceding it. If the preceding request for accessing the same address as the request from the bus master is not completed, the address-dependent comparator 70 waits for the request from the bus master to be issued.

  A technique for performing request control using the address-dependent comparator 70 as described above is described in, for example, Japanese Patent Application Laid-Open No. 2008-9763 (see Patent Document 1).

  FIG. 2 is a diagram showing another example of the configuration of the semiconductor integrated circuit according to the prior art. The semiconductor integrated circuit shown in FIG. 2 includes an external bus bridge 30 connected to an external device 50 (example: memory, I / O) as the slave 60 shown in FIG. The external bus bridge 30 includes a system bus request receiving circuit 31, a system bus request transmitting circuit 32, a command queue 33, and a response queue 32.

  Requests issued from the CPU 10 and the DMA controller 20 that are bus masters of the system bus 40 are temporarily stored in the command queue 33. At this time, the storage control to the command queue 33 is controlled by the system bus request receiving circuit 31. In the command queue 33, requests from the system bus 40 are stored in order. Requests stored (stacked) in the command queue 33 are issued to the external device 50 in the order of storage and processed. On the other hand, a request completion notification from the external device 50 is stored in the response queue 34 and issued to the CPU 10 and the DMA 20 under the control of the system bus request transmission unit 32.

  The order of requests to the external device 50 is maintained in the order of arrival of requests to the slave (external bus bridge 30). For example, in this example, after a prior request (for example, a write request) is issued to the external device 50, a subsequent request (for example, a read request) is issued. In this case, the response response to the read request may be deteriorated. In particular, the problem becomes prominent when processing requiring QoS is performed.

  In order to solve such a problem, a configuration including a read queue 35 and a write queue 36 as command queues is known as in the semiconductor integrated circuit shown in FIG.

JP2008-9763

  In the semiconductor integrated circuit shown in FIG. 3, since read and write requests can be issued separately, the processing performance is improved as compared with the example shown in FIG. However, in cases where exclusive memory control is performed, it is necessary to guarantee the request issue order for read and write. For example, when the CPU 10 issues a write request to the address “0X4000” and then issues a read request to the address, the write needs to be completed before the read. In this case, a mechanism (data dependency determination mechanism) for determining which of the requests stored in the read queue 35 and the write queue 36 is to be issued to the external device 50 first is referred to as a read queue 35 or a write queue 36. It is necessary to provide between.

  For this reason, in the semiconductor integrated circuit shown in FIG. 3, when the number of queue stages is increased in order to improve performance, it is necessary to compare the data dependency relationship of entries according to the increased number of stages. In this case, the logic scale of the semiconductor integrated circuit becomes large, and mounting problems such as the inability to increase the operating frequency become prominent.

  In order to solve the above problems, the present invention employs the means described below. In the description of technical matters constituting the means, in order to clarify the correspondence between the description of [Claims] and the description of [Mode for Carrying Out the Invention] The number / symbol used in [Form] is added. However, the added numbers and symbols should not be used to limit the technical scope of the invention described in [Claims].

  The semiconductor integrated circuit (100) according to the present invention sends requests to a plurality of queues (330) based on addresses of access destinations of requests issued from a plurality of queues (330) and a plurality of bus masters (1, 2). A request distribution unit (301) that distributes to any of the above, and a request selector (302) that issues a request in the queue selected from the plurality of queues (330) to the external device (5).

  According to the request control method of the present invention, a request is prepared based on the steps of preparing a plurality of queues (330) and the access destination addresses of requests issued from the plurality of bus masters (1, 2). And a step of issuing a request in the queue selected from the plurality of queues (330) to the external device (5).

  In the present invention, since requests from the bus master are distributed to any of a plurality of queues based on the request address, the address dependency between the queues (between requests) is canceled when the requests are stored in the queue. That is, the present invention does not require logic for comparing the address dependency between queues.

  Therefore, according to the present invention, it is possible to increase the number of requests issued from a plurality of bus masters while suppressing an increase in logical scale.

  It is also possible to increase the number of requests issued while guaranteeing the address dependency and priority processing of requests issued from a plurality of bus masters.

  Furthermore, it is possible to increase the number of requests issued while guaranteeing the address dependency and QoS control of requests issued from a plurality of bus masters.

FIG. 1 is a diagram showing an example of a configuration of a semiconductor integrated circuit according to the prior art. FIG. 2 is a diagram showing another example of the configuration of the semiconductor integrated circuit according to the prior art. FIG. 3 is a diagram showing still another example of the configuration of the semiconductor integrated circuit according to the prior art. FIG. 4 is a diagram showing a configuration in the embodiment of the semiconductor integrated circuit according to the present invention. FIG. 5 is a diagram showing a configuration in the embodiment of the external bus bridge according to the present invention. FIG. 6 is a diagram showing an example of the configuration of the request distribution unit and the structure of the window according to the present invention. FIG. 7 is a diagram showing an example of the structure of a window according to the present invention. FIG. 8 is a diagram showing an example of the configuration of the request selector according to the present invention. FIG. 9A is a flowchart showing an example of a request control operation according to the present invention. FIG. 9B is a flowchart showing an example of a request control operation according to the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same or similar reference numerals indicate the same, similar, or equivalent components.

  An embodiment of a semiconductor integrated circuit according to the present invention will be described with reference to FIGS. FIG. 4 is a diagram showing an example of the configuration of a semiconductor integrated circuit according to the present invention. Referring to FIG. 4, the semiconductor integrated circuit according to the present invention includes a CPU 1, a DMA controller 2, and an external bus bridge 3 which are exemplified by an LSI and are connected to each other via a system bus 4.

  The CPU 1 and the DMA controller 2 function as a bus master of the system bus 4 and issue requests to the external devices 5 (a plurality of external devices 5-1 to 5-3) via the external bus bridge 3. The external device 5 is connected to the external bus bridge 3 via an external bus, and is an I / O interface exemplified by USB (Universal Serial Bus) or PCI Express, or a memory exemplified by RAM (Random Access Memory).

  The external bus bridge 3 controls the connection between the system bus 4 and the external device 5 (external bus), and functions as a slave of the system bus 4. The external bus bridge 3 transfers requests (request command, request address (access destination address)) and data issued by the bus master (CPU 1, DMA controller 2) to the external device 5 to the external device 5. The external bus bridge 3 transfers requests (request command, request address) and data issued from the external device 5 to the bus master (CPU 1 and DMA controller 2).

  The external bus bridge 3 according to the present invention has a request priority processing mechanism. Details of the configuration of the external bus bridge 3 according to the present invention will be described with reference to FIG.

  The external bus bridge 3 includes a request distribution unit 301 that functions as a system bus request reception circuit, a transmission queue group 330, a request selector 302, a reception unit 303, a reception queue group 320, and a system bus request transmission circuit 304.

  The request distribution unit 301 decodes a request issued from a bus master (e.g., CPU 1, which will be described below using the CPU 1 as an example) via the system bus 4, and executes the request according to the decoding result (transfer address and command type). The requests are distributed to the subsequent transmission queue group 330 and stored (enqueued).

  The transmission queue group 330 includes a plurality of queues 331, 332, and 333. It is preferable that different priorities are assigned to the plurality of queues 331, 332, and 333, respectively. In this case, the request selector 302 preferentially selects a queue having a high priority, extracts a request from the selected queue, and issues the request to the external device 5.

  Some queues in the transmission queue group 330 are set to a first queue (hereinafter referred to as a high priority queue) that stores a request that can issue a next request without waiting for a request completion notification. Is preferred. For example, a request for accessing the memory can be issued without waiting for completion of the request (for example, read data for the read request). For this reason, it is preferable to set the request for memory access in the request distribution unit 301 so as to store the request in the high priority queue. The other queues in the transmission queue group 330 are second queues (hereinafter referred to as sequential queues) that store requests that need to be notified of the completion of previous requests in order to issue the next request. It is preferably set. For example, a request to the I / O interface needs to wait for completion of the request before issuing the next request. For this reason, it is preferable to set the request distribution unit 301 so that the request issued to the I / O interface is stored in the sequential queue.

  Here, the high priority queue is issued to the external device 5 with priority over the sequential queue. In addition, when a plurality of queues are set as high priority queues, it is preferable that different priorities are given to the respective queues. In this embodiment, the queues 331 and 332 are set as high priority queues, the priority “0” is given to the queue 331, and the priority “1” is given to the queue 332. It is assumed that the priority “0” is higher than the priority “1”. In this embodiment, it is assumed that the queue 333 is set as a sequential queue.

  FIG. 6 is a diagram showing an example of the configuration of the request distribution unit 301 and the window structure according to the present invention. Details of the configuration of the request distribution unit 301 will be described with reference to FIG.

  With reference to FIG. 6B, the request distribution unit 301 includes a window register 310 and a distribution circuit 314.

  The distribution circuit 314 decodes the request input from the system bus 4, and when the decoded result hits the request window 300, enqueues (stores) the request in the storage destination queue set in the hit window. The request window 300 has a plurality of windows to which addresses corresponding to the request addresses are assigned, and information specifying a command type and a storage destination queue is set in each of the windows.

  The decoded request includes a request address (access destination address) and a request command. If a window with an address that matches the request address exists (hits), or the same command type as the request command When the set window exists (hits), the request is stored in the storage destination queue set in the hit window.

  The window register 310 includes a base register 311, a size register 312, and a request register 313, and sets the request window 300 shown in FIG. 6A according to the values set in the respective registers. Each of the base register 311, the size register 312, and the request register 313 is prepared in a number corresponding to a plurality of windows set in the request window 300. For example, when setting a request window 300 having a plurality of windows # 0, # 1, and # 2, three base registers 311, a size register 312 and a request register 313 are prepared.

  The address ranges of the windows # 0, # 1, and # 2 are set by the base register 311 and the size register 312.

  The base register 311 is set with a value that specifies the start address of the window. That is, the base register 311 sets the head addresses of the windows # 0, # 1, and # 2. For example, the start address of window # 0 is set to “0X0000”, the start address of window # 1 is set to “0X1000”, and the start address of window # 2 is set to “0X2000”.

  The size register 312 is set with a value that specifies the size of the window. That is, the size registers 312 set the sizes of the windows # 0, # 1, and # 2. For example, the sizes of the windows # 0, # 1, and # 2 are set to “0X1000”.

  When the request from the system bus 4 hits the window, the request register 313 is set with information for determining which queue is enqueued (storage destination queue) and the request type (command type) set for the window. That is, the request register 313 sets a queue for storing a hit request in each of the windows # 0, # 1, and # 2, and sets the request type (command type) of the window.

  FIG. 7 is a diagram showing an example of the structure of windows # 0, # 1, and # 2 according to the present invention. Details of the request distribution process based on the request window 300 will be described with reference to FIG.

  In the example shown in FIG. 7A, the address range is “0x0000” to “0x0FFF” and the storage destination queue is “queue 331”, window # 0, the address range is “0x1000” to “0x1FFF”, and the storage destination queue is “ The window # 1 of the queue 331, the window # 2 whose address range is “0x2000” to “0x2FFF”, and whose storage destination queue is “queue 332” is set as the request window 300. In this example, no command type is set in any of windows # 0, # 1, and # 2.

  As shown in FIG. 7A, when the command type is not set in the request window 300, the distribution circuit 314 searches for a window with a matching decoded request address, and determines the request based on the hit (match) window. Determine the storage location. For example, when the request address is “0X1005”, the request hits the window # 1. In this case, the distribution circuit 314 is placed in the queue 331 (priority “0”) set as the storage destination queue of the window # 1. The request is enqueued (stored), or if the request address is “0X2010”, the request hits window # 2. In this case, the distribution circuit 314 enqueues (stores) the request in the queue 332 (priority “1”) set as the storage destination queue of the window # 2. Further, when the request address is an address not set in the request window 300 (for example, “0X3000”), there is no window that hits the request. In this case, the distribution circuit 314 enqueues (stores) the request in the queue 333 (sequential queue).

  Whether the window is hit or not is determined from the smallest window number. For example, even if the same address is set in a plurality of windows # 0 and # 1, the requests are judged in order from the window # 0 having the smallest address, so that the request does not hit multiple windows in duplicate. . In other words, by giving priority to the search order of the windows hit by the request, it is possible to prevent malfunction due to a window setting error.

In the example shown in FIG. 7B, the command type is “memory read”, the address range is “0x0000” to “0x0FFF”, the storage destination queue is “queue 331”, window # 0, and the command type is “I / O access”. ”, Window # 1, whose address range is“ 0x1000 ”to“ 0x1FFF ”, and whose storage destination queue is“ queue 332 ”,
A window # 2 having an address range of “0x2000” to “0x2FFF” and a storage destination queue of “queue 333” is set as the request window 300.

  As shown in FIG. 7B, the distribution circuit 314 searches for a window that matches the decoded request address or / and command type, and determines the storage location of the request based on the hit (match) window. For example, when the request address is “0X0100 and the command type is memory access, the request hits the window # 0. In this case, the distribution circuit 314 has the queue 331 set as the storage destination queue of the window # 0. Enqueue (store) the request at (priority “0”) In order to hit window # 0 or window # 1, the address and the command type must match, while the request address is “0X2010” In some cases, the request hits window # 2 regardless of the command type. In this case, the distribution circuit 314 enqueues (stores) the request in the queue 333 (sequential queue) set as the storage destination queue of the window # 2.

  Further, when the request address is an address not set in the request window 300 (for example, “0X3000”), even if the addresses match, the command type is different from the command set in the request window 300, or the command type is one. If the request address is different from the address set in the request window 300, it is determined that no window hits the request. In this case, the distribution circuit 314 enqueues (stores) the request in the queue 333 (sequential queue). For example, when the request address is 0x0100 and the I / O access is made, there is no hit window and the request is stored in the queue 333.

  In the example shown in FIG. 7C, window # 0 having an address range of “0x0000” to “0x0FFF” and a storage destination queue of “queue 331”, a command type of “memory read”, and a storage destination queue of “queue 332”. Window # 1, window # 2 with command type "I / O access" and storage queue "queue 333" is set as request window 300. In this example, no address range is set for windows # 1 and # 2.

  As shown in FIG. 7C, the distribution circuit 314 searches for a window that matches the decoded request address or command type, and determines the storage location of the request based on the hit (match) window. For example, when the request address is “0X0100”, the request hits the window # 0. In this case, the distribution circuit 314 is placed in the queue 331 (priority “0”) set in the storage destination queue of the window # 0. The request is enqueued (stored), or if the request address is arbitrary and the command type is memory read, the request hits window # 1. In this case, the distribution circuit 314 stores the storage destination of window # 1 The request is enqueued (stored) in the queue 332 (priority level “1”) set in the queue, and if the request address is not set in the request window 300 (for example, “0X3000”), There is no window to hit. In this case, the distribution circuit 314 enqueues (stores) the request in the queue 333 (sequential queue), and determines whether or not the request hits the request window 300 only by the command type (for example, memory access, I / O access). If the request cannot be made, the request address from the system bus 4 is assigned as the transfer destination address of the request.

  As described above, by setting the address and command type to be set in the window according to the process to be executed, the storage destination queue corresponding to the access destination address and the command to be executed can be changed. When there is a request that does not hit the window, an error may be returned or the request may be discarded.

  The request distribution unit 301 according to the present invention can determine the storage destination queue according to the input request address and command type without comparing addresses between requests. That is, in the present invention, the address dependency relationship is canceled when enqueued in each queue. For this reason, the request selector 302 at the subsequent stage can select the queue to be processed without worrying about the address dependency and the command issue order.

  The request selector 302 issues a request in the queue selected from the transmission queue group 330 to the external device 5. It is preferable that the request selector 302 preferentially selects a queue having a high priority and issues a request in the selected queue to the external device 5.

  When the request selector 302 extracts and issues a request from the high priority queue (queues 331 and 332), the request selector 302 extracts the next request from the high priority queue without receiving a completion notification of the issued request to the external device 5. It is preferable to issue it. Specifically, the request selector 302 notifies the reception unit 303 of the issuance of a high priority request when issuing a request in the high priority queue (queues 331 and 332). The receiving unit 303 returns an ACK signal (command acknowledge) in response to the issuance notification of the high priority request. The request selector 302 extracts and issues the next request from the high priority queue according to the ACK signal from the receiving unit 303. Thereby, the next request stored in the high priority queue can be issued without waiting for completion of the previously issued request. For example, the request selector 302 can issue the next request in the high priority queue before the read response (read data) to the read command is returned.

  On the other hand, when the request selector 302 extracts and issues a request from the sequential queue (queue 333), the request selector 302 issues the next request after receiving the reception completion notification of the issued request. Specifically, the request selector 302 issues requests in the sequential queue (queue 333) as usual. Upon receiving the request completion notification from the external device 5, the receiving unit 303 outputs an ACK signal (command acknowledge) to the request selector 302. The request selector 302 extracts and issues the next request from the sequential queue according to the ACK signal from the receiving unit 303. As a result, the next request stored in the sequential queue is issued upon completion of the previously issued request. For example, the request selector 302 waits without issuing the next request in the sequential queue until a read response (read data) to the read command is returned to the receiving unit 303.

  FIG. 8 is a diagram showing an example of the configuration of the request selector 302 according to the present invention. Referring to FIG. 8, the request selector 302 includes a FULL determination flag 321, a priority processing determination circuit 322, and a selector 323.

  The priority processing determination circuit 322 performs priority processing determination according to the number of requests enqueued (stored) in each queue, and determines a queue to be processed. At this time, the priority processing determination circuit 322 checks the storage status in order from the queue with the highest priority, and if no request is stored in the queue 331 with the highest priority, the queue with the next highest priority is selected as the processing target. 323 is specified. The sequential queue has the lowest priority. In addition, when the high-priority queue is filled with requests (becomes FULL), the priority processing determination circuit 322 issues all the requests in the queue and then sets the queue with the next highest priority to the selector 323. specify.

  The FULL determination flag 321 is a flag indicating whether or not the high priority queue has become FULL due to a request. The FULL determination flag 321 is provided corresponding to each of the queues 331 and 332 set as the high priority queue. For example, “1” is set in the FULL determination flag 321 of the queue that has become FULL due to the request. The priority processing determination circuit 322 can check the queue that has become FULL by the FULL determination flag 321.

  The selector 323 extracts a request from the queue designated as a processing target by the priority processing determination circuit 322 and issues the request to the external device 5 according to the content of the request.

  With the configuration described above, the request selector 302 processes the high priority queue until the high priority queue is filled with requests (becomes FULL). In the present invention, a queue with a low priority is processed with the high priority queue set to FULL as a trigger. As a result, it is possible to prevent the system from becoming a live block without issuing a request stored in a queue having a low priority.

  Details of the priority processing control method by the request selector 302 will be described with reference to FIGS. 9A and 9B. 9A and 9B are flowcharts showing an example of a request control operation according to the present invention.

  The request selector 302 first checks whether or not a request is loaded (stored) in the queue 331 having the highest priority (priority “0”) in the prepared transmission queue group 330. (Step S101). When requests are loaded (stored) in the queue 331, the request selector 302 issues the request in the queue 331 to the external device 5 (Yes in steps S101 and S102).

  Next, the request selector 302 refers to the FULL determination flag 321 and confirms whether the queue 331 has become FULL due to the request (step S103). If the queue 331 is not FULL, the process proceeds to step S101 (No in step S103). On the other hand, when the queue 331 becomes FULL, “1” indicating FULL is set in the FULL determination flag 321 corresponding to the queue 331, and the request selector 302 displays all the requests stored in the queue 331 at that time. The processing is continued until it is issued to the external device 5 (No at Steps S103, S104, S105).

  If no requests are stacked in the priority processing queue 331 (No in step S101), or if all requests in the queue 331 that has become FULL are processed (Yes in step S105), the request selector 302 has the next highest priority. It is checked whether or not requests are stored (stored) in the queue 332 (priority “1”) (step S201).

  When requests are accumulated in the queue 332, the request selector 302 issues a request in the queue 332 to the external device 5 (steps S201 Yes and S202).

  Next, the request selector 302 refers to the FULL determination flag 321 and confirms whether or not “1” indicating FULL is set in the FULL determination flag 321 of the queue 331 having a higher priority than the queue 332 (step). S203). When “1” indicating FULL is not set in the FULL determination flag 321 of the queue 331, the process proceeds to step S101 (No in step S203). In other words, when the queue 332 is processed with a request that there is no request in the high-priority queue 331, the request selector 302 is controlled to preferentially process the high-priority queue 331 after the processing of the queue 332. The

  If “1” indicating FULL is set in step S203, the request selector 302 refers to the FULL determination flag 321 and confirms whether the queue 332 is FULL (steps S203 Yes, S204).

  If the queue 332 is not FULL in step S204, the process proceeds to step S201 (No in step S204). That is, when the queue 332 is processed with the queue 331 having a high priority set to FULL as a trigger, the request selector 302 continues the processing of the queue 332 or the processing having a lower priority than the queue 332.

  On the other hand, when the queue 332 becomes FULL, “1” indicating FULL is set in the FULL determination flag 321 corresponding to the queue 332, and the request selector 302 displays all requests stored in the queue 332 at that time. The process is continued until it is issued to the external device 5 (No in steps S204, S205, and S206).

  If no requests are stacked in the priority processing queue 332 (No in step S201), or if all requests in the queue 332 that has become FULL are processed (Yes in step S206), the request selector 302 has the next highest priority. It is confirmed whether or not requests are queued (here, a sequential queue (queue 333)) (step S301).

  If there are requests in the queue 333, the request selector 302 issues the request in the queue 333 to the external device 5 (Yes in steps S301 and S302). On the other hand, if no request is loaded in the queue 333, the process proceeds to step S101 (No in step S301).

  The request selector 302 that has performed processing for the queue 333 in step S302 refers to the FULL determination flag 321 and “1” indicating FULL is displayed in the FULL determination flag 321 of the queues 331 and 332 having higher priority than the queue 333. It is confirmed whether it is set (steps S303 and S304). If “1” indicating FULL is not set in the FULL determination flag 321 of the queues 331 and 332, the process proceeds to step S101 (No in steps S303 and S304). That is, when processing the sequential queue (queue 333) triggered by the absence of a request in the high priority queues (queues 331 and 332), the request selector 302 prioritizes the queue 331 having the highest priority after the processing of the queue 333. To be processed automatically.

  In steps S303 and S304, when “1” indicating FULL is set in both the FULL determination flags 321 of the queues 331 and 332, the request selector 302 does not store a request in the queue 333 (empty). This is confirmed (steps S303 Yes, S304 Yes, S305).

  If the queue 332 is not empty in step S305, the process proceeds to step S302 (No in step S305). That is, when processing the queue 333 triggered by the high priority queues 331 and 332 becoming FULL, the request selector 302 continues processing for the queue 333 until all the requests in the queue 333 are issued. .

  On the other hand, when the queue 333 becomes empty, the request selector 302 clears “1” set in the FULL determination flags 321 of all the high priority queues (queues 331 and 332) to “0” (step S305 Yes). , S306). After clearing the FULL determination flag 321, the process proceeds to step S <b> 101, and the request selector 302 performs the process again with priority given to the queue having a high priority.

  As described above, according to the present invention, the priority processing determination circuit 322 determines which queue is selected from among a plurality of queues. For this reason, requests between the queues are issued out-of-order. However, requests in the queue are issued in-order because they are processed in the order in which they are stacked (enqueue order).

  The priority processing determination circuit 322 uses the FULL determination flag 321 as a trigger to select a low priority queue or a sequential queue as a processing target when the high priority queue becomes FULL. As a result, it is possible to prevent the system from becoming a live block without issuing a request stored in a queue having a low priority.

  The reception unit 303 receives a request (request command, request address) from the external device 5 and stores it in the reception queue group 320. The reception queue group 320 includes a write queue 341 that stores a write request and a read queue 342 that stores a read request. The reception unit 303 stores a write request from the external device 5 in the write queue 341 and stores a read request from the external device 5 in the read queue 342. Requests in the write queue 341 are output to the system bus request transmission circuit 304 in preference to the read queue 342. Since this is a function defined by general PCI, detailed description is omitted.

  The system bus request transmission circuit 304 issues a request output from one of the write queue 341 and the read queue 342 to the CPU 1 that is a bus master or the DMA controller 2 via the system bus 4.

  The request distribution unit 301 according to the present invention resolves the address dependency between requests before enqueuing them into a queue, and distributes them to a plurality of queues. For this reason, it is not necessary to compare the address dependency between queues, and a request from the system bus 4 can be enqueued immediately. Also, since the request enqueued in a plurality of queues has already resolved the address dependency, even if the queue to be processed is arbitrarily selected, the request can be issued without conflicting access destinations. Therefore, it is possible to increase the number of queue stages in a scalable manner without worrying about mounting problems.

  Furthermore, a priority is assigned to each queue, and the request selector 302 selects a queue to be processed according to the priority. As a result, priority can be given to the request and command type of the issuer, and the request to be preferentially processed can be issued without being retained in the external bus bridge 3. For example, a read request is stored in a queue with a high priority, and a write request is stored in a queue with a low priority, so that a read request is issued to the external device 5 before a write request issued from the master first. Can do. Therefore, according to the present invention, it is possible to improve the read latency which has been a problem in the conventional configuration.

  In addition, by enqueueing a request for a specific process (for example, voice process or image process) as a command type into a queue having a high priority, a priority process for the specific process can be performed. Requests that require issue order guarantees, such as I / O requests, are stored in a sequential queue (queue 333), so that issue orders can be guaranteed in the same manner as in the prior art.

  In the present invention, since the address dependency is canceled before the requests are stored in a plurality of queues, the number of requests issued from a plurality of bus masters can be increased without increasing the logical scale as in the prior art. it can.

  It is also possible to increase the number of requests issued while guaranteeing the address dependency and priority processing of requests issued from a plurality of bus masters.

  Furthermore, it is possible to increase the number of requests issued while guaranteeing the address dependency and QoS control of requests issued from a plurality of bus masters.

  The embodiment of the present invention has been described in detail above, but the specific configuration is not limited to the above-described embodiment, and changes within a scope not departing from the gist of the present invention are included in the present invention. . In the above-described embodiment, the external bus bridge 3 including the three queues 331, 332, and 333 as the transmission queue has been described as an example. However, the number, priority, and sequential queue setting are not limited thereto.

1: CPU
2: DMA controller 3: External bus bridge 4: System bus 5: External device 100: Semiconductor integrated circuit 300: Request window 301: Request distribution unit 302: Request selector 303: Reception unit 304: System bus request transmission circuit 310: Window register 311: Base register 312: Size register 313: Request register 314: Distribution circuit 320: Reception queue group 321: FULL determination flag 322: Priority processing determination circuit 323: Selector 330: Transmission queue group 331-333: Queue 341 Write queue 342: Read queue

Claims (21)

Multiple queues,
A request distribution unit that distributes the request to one of the plurality of queues based on an access destination address of a request issued from a plurality of bus masters;
A semiconductor integrated circuit comprising: a request selector that issues a request in a queue selected from the plurality of queues to an external device. The semiconductor integrated circuit according to claim 1,
The request distribution unit distributes the request to one of the plurality of queues based on a command type of the request. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1 or 2,
The distribution unit includes a plurality of windows each having a predetermined address range, a plurality of windows associated with any of the plurality of queues, and a window in which an address matching a request address is set. And a sorting circuit for searching from the window of
The distribution circuit stores the request in a queue corresponding to a window in which an address that matches the request address is set. The semiconductor integrated circuit according to claim 3,
A predetermined command type is set for each of the plurality of windows,
The distribution circuit searches the plurality of windows for a window in which a command type that matches a request command is set.The distribution circuit includes a queue corresponding to a window in which a command type that matches a request command is set. A semiconductor integrated circuit that stores requests. The semiconductor integrated circuit according to claim 3 or 4,
The distribution circuit searches a plurality of windows in a predetermined order, and determines a queue for storing a request based on a window that first hits the request. Semiconductor integrated circuit. The semiconductor integrated circuit according to any one of claims 1 to 5,
Each of the plurality of queues is given a different priority.
The request selector preferentially selects and issues a request in the queue with a high priority to an external device. The semiconductor integrated circuit according to claim 6,
The request distribution unit stores a request that can be output without waiting for completion of the transaction in the first queue, and stores a request that is output after waiting for completion of the transaction in the second queue having a lower priority than the first queue. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 7,
The request distribution unit stores a memory access request in the first queue. The semiconductor integrated circuit according to claim 7 or 8,
The request distribution unit stores an access request for an external interface in the second queue. The semiconductor integrated circuit according to any one of claims 7 to 9,
A receiver that outputs a first response signal in response to a request selected and issued from the first queue;
The request selector extracts a next request from the first queue in response to the first response signal, and issues the next request to an external device. The semiconductor integrated circuit according to claim 10,
The receiving unit receives a completion notification of a request selected and issued from the second queue from an external device, and outputs a second response signal in response to the completion notification,
The request selector extracts a next request from the second queue in response to the second response signal, and issues the next request to an external device. The semiconductor integrated circuit according to any one of claims 6 to 11,
When a request is stored in the high priority queue, the request selector selects a request in the high priority queue until there is no request in the high priority queue, and sends the request to an external device. Issued semiconductor integrated circuit. The semiconductor integrated circuit according to claim 12, wherein
When requests are stored in all of the high priority queues, the request selector issues all of the stored requests, and then requests requests in a queue with a lower priority than the high priority queues. A semiconductor integrated circuit that is selected and issued to an external device. Preparing multiple queues;
Allocating the request to one of a plurality of queues based on an access destination address of a request issued from a plurality of bus masters;
Issuing a request in a queue selected from the plurality of queues to an external device. The request control method according to claim 14,
The distribution step includes a step of distributing the request to any of the plurality of queues based on a command type of the request. The request control method according to claim 14 or 15,
Each of the plurality of queues is given a different priority.
The step of issuing the request to an external device includes a step of preferentially selecting a request in the queue having a high priority and issuing the request to the external device. The request control method according to claim 16, wherein
The distributing step stores a request that can be output without waiting for completion of the transaction in the first queue, and a request that is output after waiting for completion of the transaction in the second queue having a lower priority than the first queue. A request control method comprising the step of storing. The request control method according to claim 17,
A receiving unit outputting a first response signal in response to a request selected from the first queue and issued;
Extracting the next request from the first queue in response to the first response signal and issuing the next request to an external device; and a request control method. The request control method according to claim 18, wherein
Receiving the notification of completion of a request selected and issued from the second queue from an external device;
The receiving unit outputting a second response signal in response to the completion notification;
Extracting a next request from the second queue in response to the second response signal and issuing the next request to an external device; and a request control method. The request control method according to any one of claims 16 to 19,
If a request is stored in the high priority queue, further selecting and issuing a request in the high priority queue to an external device until there are no more requests in the high priority queue. A request control method provided. The request control method according to claim 20, wherein
When requests are stored in all of the high priority queues, after issuing all of the stored requests, select a request in a queue with a lower priority than the high priority queue and select an external device A request control method further comprising the step of:

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