JP6852296B2 - Manufacturing method of field effect transistor - Google Patents

Description

The present invention relates to a method for manufacturing a field effect transistor.

A field effect transistor (FET) has a low gate current and a flat structure, so that it is easier to manufacture and integrate than a bipolar transistor. Therefore, FETs have become indispensable elements in integrated circuits used in current electronic devices. For example, an active matrix in which field effect transistors are arranged in a matrix is used as a drive circuit for a display such as a liquid crystal display. Has been done.

As an example of the field effect transistor, a field effect transistor having an oxide semiconductor layer is known (see, for example, Patent Document 1). Field-effect transistors having an oxide semiconductor layer are expected to have improved transistor characteristics such as increased mobility and improved switching characteristics.

By the way, an SS value (subthreshold swing value) may be used as one of the indexes indicating the switching characteristics of the field effect transistor. The SS value is defined as the increment of the gate voltage required to increase the drain current by an order of magnitude at the maximum slope of the logarithmic graph in the subthreshold region where the transfer characteristic transitions from the off region to the on region. Will be done. The smaller the SS value, the steeper the rise and the better the switching characteristics.

However, depending on the manufacturing process, the SS value of the field-effect transistor may increase, and there is a demand for a manufacturing process of the field-effect transistor capable of reducing the SS value.

An object of the present invention is to provide a method for manufacturing a field effect transistor capable of reducing the SS value.

The method for manufacturing this electric field effect transistor is a method for manufacturing an electric field effect transistor in which a first oxide layer and a second oxide layer, one of which is an oxide semiconductor layer, are adjacent to each other. The step of forming the first oxide layer from a material containing an element containing at least one of Sc, Y, and lanthanoid, and at least Ga, Sc, Y, and lanthanoid on the first oxide layer. It has a step of forming the second oxide layer with a material containing any of the elements, and the formation temperature of the second oxide layer is equal to or lower than the formation temperature of the first oxide layer. Ah is, the first oxide layer is an oxide insulating layer, said second oxide layer is an oxide semiconductor layer, the oxide insulating layer is a gate insulating layer, the gate insulating layer It is required that the element A, which is an alkaline earth metal, and the element B, which is at least one of Ga, Sc, Y, and a lanthanoid, are contained.

According to the disclosed technique, it is possible to provide a method for manufacturing a field effect transistor capable of reducing the SS value.

It is sectional drawing which illustrates the field effect transistor which concerns on 1st Embodiment. It is a figure (the 1) which illustrates the manufacturing process of the field effect transistor which concerns on 1st Embodiment. It is a figure (the 2) which illustrates the manufacturing process of the field effect transistor which concerns on 1st Embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on the modification of 1st Embodiment. It is a figure (the 1) which illustrates the manufacturing process of the field effect transistor which concerns on the modification of 1st Embodiment. It is a figure (No. 2) which illustrates the manufacturing process of the field effect transistor which concerns on the modification of 1st Embodiment. It is a block diagram which shows the structure of the television apparatus in 2nd Embodiment. It is explanatory drawing (the 1) of the television apparatus in 2nd Embodiment. It is explanatory drawing (the 2) of the television apparatus in 2nd Embodiment. It is explanatory drawing (the 3) of the television apparatus in 2nd Embodiment. It is explanatory drawing of the display element in 2nd Embodiment. It is explanatory drawing of the organic EL in the 2nd Embodiment. It is explanatory drawing (the 4) of the television apparatus in 2nd Embodiment. It is explanatory drawing (the 1) of another display element in 2nd Embodiment. It is explanatory drawing (the 2) of another display element in 2nd Embodiment.

Hereinafter, modes for carrying out the invention will be described with reference to the drawings. In each drawing, the same components may be designated by the same reference numerals and duplicate description may be omitted.

<First Embodiment>
[Structure of field effect transistor]
FIG. 1 is a cross-sectional view illustrating the field effect transistor according to the first embodiment. Referring to FIG. 1, the field effect transistor 10 has a bottom gate / top having a base material 11, a gate electrode 12, a gate insulating layer 13, a semiconductor layer 14, a source electrode 15, and a drain electrode 16. It is a contact type field effect transistor. The field-effect transistor 10 is a typical example of the field-effect transistor according to the present invention.

In the field effect transistor 10, the gate electrode 12 is formed on the insulating base material 11, and the gate insulating layer 13 is further formed so as to cover the gate electrode 12. A semiconductor layer 14 is formed on the gate insulating layer 13, and a source electrode 15 and a drain electrode 16 are formed on the semiconductor layer 14 so that a channel is formed in the semiconductor layer 14. Hereinafter, each component of the field effect transistor 10 will be described in detail.

In the present embodiment, for convenience, the semiconductor layer 14 side is the upper side or one side, and the base material 11 side is the lower side or the other side. Further, the surface of each part on the semiconductor layer 14 side is the upper surface or one surface, and the surface on the base material 11 side is the lower surface or the other surface. However, the field-effect transistor 10 can be used in an upside-down state, or can be arranged at an arbitrary angle. Further, the plan view means that the object is viewed from the normal direction of the upper surface of the base material 11, and the planar shape refers to the shape of the object viewed from the normal direction of the upper surface of the base material 11. .. Further, a cross section cut in the laminating direction of each part on the base material 11 is a vertical cross section, and a cross section cut in a direction perpendicular to the laminating direction of each part on the base material 11 (a direction parallel to the upper surface of the base material 11). It has a cross section.

The shape, structure, and size of the base material 11 are not particularly limited and may be appropriately selected depending on the intended purpose.

The material of the base material 11 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, a glass base material, a plastic base material, a film base material, or the like can be used. The glass base material is not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include non-alkali glass and silica glass. The plastic base material and the film base material are not particularly limited and may be appropriately selected depending on the intended purpose. For example, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate, etc. (PEN) and the like. The base material 11 is preferably subjected to pretreatment such as oxygen plasma, UV ozone, and UV irradiation cleaning from the viewpoint of cleaning the surface and improving the adhesion.

The gate electrode 12 is formed in a predetermined region on the base material 11. The gate electrode 12 is an electrode for applying a gate voltage. The material of the gate electrode 12 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, platinum, palladium, gold, silver, copper, zinc, aluminum, nickel, chromium, tantalum, molybdenum and titanium. Such as metals, alloys thereof, mixtures of these metals and the like. Examples thereof include conductive oxides such as indium oxide, zinc oxide, tin oxide, gallium oxide and niobium oxide, composite compounds thereof, and mixtures thereof. The average thickness of the gate electrode 12 is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably 40 nm to 2 μm, more preferably 70 nm to 1 μm.

The gate insulating layer 13 is provided between the gate electrode 12 and the semiconductor layer 14, and is an oxide insulating layer for insulating the gate electrode 12 and the semiconductor layer 14. As the material of the gate insulating layer 13, for example, element A which is an alkaline earth metal and element B which is at least one of gallium (Ga), scandium (Sc), yttrium (Y), and lanthanoid are used. At least the contained oxide film can be used.

This oxide film preferably contains element C, which is at least one of Zr (zirconium) and Hf (hafnium), and further contains other components, if necessary. The alkaline earth metal contained in the oxide film may be of one kind or two or more kinds.

Examples of alkaline earth elements include beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), and radium (Ra).

Lantanoids include lanthanum (La), cerium (Ce), placeodim (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), and dysprosium. (Dy), holmium (Ho), erybium (Er), turium (Tm), ytterbium (Yb), lutetium (Lu) can be mentioned.

The oxide film preferably contains a normal dielectric amorphous oxide or is formed of the normal dielectric amorphous oxide itself. The normal dielectric amorphous oxide is stable in the atmosphere and can stably form an amorphous structure in a wide composition range. However, crystals may be contained in a part of the oxide film.

The average thickness of the gate insulating layer 13 is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably 50 nm to 3 μm, more preferably 100 nm to 1 μm.

The semiconductor layer 14 is an oxide semiconductor layer formed on the gate insulating layer 13, and is arranged so as to face the gate electrode 12 via the gate insulating layer 13. The semiconductor layer 14 can be formed from, for example, an n-type oxide semiconductor.

The n-type oxide semiconductor constituting the semiconductor layer 14 is at least one of indium, zinc, tin, gallium, and titanium because high electric field mobility mobility can be obtained and the electron carrier concentration can be easily controlled appropriately. , It is preferable to contain an alkaline earth metal, and it is more preferable to contain indium and an alkaline earth metal.

Examples of the alkaline earth element include beryllium (Be), Mg, calcium (Ca), strontium (Sr), barium (Ba), radium (Ra) and the like.

The source electrode 15 and the drain electrode 16 are formed on the semiconductor layer 14. The source electrode 15 and the drain electrode 16 cover a part of the semiconductor layer 14 and are formed at predetermined intervals. The source electrode 15 and the drain electrode 16 are electrodes for extracting a current in response to application of a gate voltage to the gate electrode 12. In addition to the source electrode 15 and the drain electrode 16, the wiring connected to the source electrode 15 and the drain electrode 16 may be formed in the same layer.

The materials of the source electrode 15 and the drain electrode 16 are not particularly limited and may be appropriately selected depending on the intended purpose. Examples thereof include the materials exemplified in the description of the gate electrode 12. The average thickness of the source electrode 15 and the drain electrode 16 is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably 10 nm to 1 μm, more preferably 50 nm to 300 nm.

[Manufacturing method of field effect transistor]
Next, a method of manufacturing the field-effect transistor shown in FIG. 1 will be described. 2 and 3 are diagrams illustrating a manufacturing process of the field effect transistor according to the first embodiment.

First, in the step shown in FIG. 2A, the gate electrode 12 is formed on the base material 11. Specifically, a base material 11 made of a glass base material or the like is prepared. Then, a conductor film is formed on the base material 11 by a vacuum vapor deposition method or the like, and the formed conductor film is patterned by photolithography and etching to form a gate electrode 12 having a predetermined shape.

From the viewpoint of cleaning the surface of the base material 11 and improving the adhesion, it is preferable that pretreatment such as oxygen plasma, UV ozone, and UV irradiation cleaning is performed before forming the gate electrode 12. The material and thickness of the base material 11 and the gate electrode 12 can be appropriately selected as described above.

Next, in the steps shown in FIGS. 2B and 2C, a gate insulating layer 13 covering the gate electrode 12 is formed on the base material 11. For example, in the step shown in FIG. 2B, the coating liquid 130 for forming the gate insulating layer is applied by a dip coating method, a spin coating method, a die coating method, or the like, and in the step shown in FIG. 2C, the gate insulating layer is formed. A process of firing the coating liquid 130 for use at a first temperature to form the gate insulating layer 13 can be mentioned. The material and thickness of the gate insulating layer 13 can be appropriately selected as described above.

However, as a method for forming the gate insulating layer 13, in addition to the above process, for example, a sputtering method, a pulse laser deposit (PLD) method, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, etc. A vacuum process can be used.

Next, in the steps shown in FIGS. 3A and 3B, the semiconductor layer 14 is formed on the gate insulating layer 13. For example, in the step shown in FIG. 3A, the oxide semiconductor layer forming coating liquid 140 is applied by a dip coating method, a spin coating method, a die coating method, or the like, and in the step shown in FIG. 3B, the gate insulating layer is applied. A process of firing the forming coating liquid 130 at a second temperature to form the gate insulating layer 13 can be mentioned.

However, as a method for forming the semiconductor layer 14, in addition to the above process, for example, a vacuum such as a sputtering method, a pulse laser deposition (PLD) method, a chemical vapor deposition (CVD) method, or an atomic layer deposition (ALD) method is used. A process can be used.

In the manufacturing process of the present embodiment, the formation temperature (second temperature) of the semiconductor layer 14 is set to be equal to or lower than the formation temperature (first temperature) of the gate insulating layer 13. For example, when the formation temperature (first temperature) of the gate insulating layer 13 is 400 ° C., the formation temperature (second temperature) of the semiconductor layer 14 needs to be 400 ° C. or lower (for example, 350 to 400 ° C.). is there.

Next, in the step shown in FIG. 3C, the source electrode 15 and the drain electrode 16 are formed on the semiconductor layer 14. For example, a conductor film is formed on the semiconductor layer 14 by a vacuum vapor deposition method or the like. Then, a mask pattern is formed on the conductor film, and the conductor film exposed from the mask pattern is removed by etching. The conductor film coated on the mask pattern serves as the source electrode 15 and the drain electrode 16. The material and thickness of the source electrode 15 and the drain electrode 16 can be appropriately selected as described above.

As described above, in the present embodiment, when two oxide layers, one of which is an oxide semiconductor layer, are vertically adjacent to each other, an upper oxide layer (semiconductor layer 14 in the present embodiment) is formed. The temperature is set to be equal to or lower than the formation temperature of the lower oxide layer (gate insulating layer 13 in the present embodiment). This makes it possible to reduce the SS value of the field effect transistor 10. That is, it is possible to improve the switching characteristics of the field effect transistor 10.

<Modified example of the first embodiment>
In the modified example of the first embodiment, an example of a field effect transistor provided with a protective layer which is an oxide insulating layer is shown. In the modified example of the first embodiment, the description of the same component as that of the above-described embodiment may be omitted.

[Structure of field effect transistor]
FIG. 4 is a cross-sectional view illustrating the field effect transistor according to the modified example of the first embodiment. Referring to FIG. 4, the field-effect transistor 10A is different from the field-effect transistor 10 (see FIG. 1) in that the protective layer 17 is provided. The field-effect transistor 10A is a typical example of the field-effect transistor according to the present invention.

The protective layer 17 is an oxide insulating layer provided on the semiconductor layer 14 so as to cover the source electrode 15 and the drain electrode 16.

Examples of the material of the protective layer 17 include element A, which is an alkaline earth metal exemplified as the material of the gate insulating layer 13, and at least gallium (Ga), scandium (Sc), yttrium (Y), and lanthanoid. An oxide film containing at least one of the B elements can be used. The average thickness of the protective layer 17 is not particularly limited and may be appropriately selected depending on the intended purpose, but is preferably 50 nm to 3 μm, more preferably 100 nm to 1 μm.

The protective layer 17 has a function of isolating and protecting at least the semiconductor layer 14 from moisture, oxygen, and the like in the atmosphere. However, the protective layer 17 has a function of protecting not only the semiconductor layer 14 but also other components of the field effect transistor 10A (for example, the gate insulating layer 13, the source electrode 15, the drain electrode 16, and the gate electrode 12). You may. Further, the protective layer 17 may have a function of protecting at least a part of the field effect transistor 10A from the material of the layer formed on the field effect transistor 10A and the formation process thereof.

[Manufacturing method of field effect transistor]
Next, a method of manufacturing the field-effect transistor shown in FIG. 4 will be described. 5 and 6 are diagrams illustrating a manufacturing process of a field effect transistor according to a modified example of the first embodiment.

First, in the step shown in FIG. 5A, the gate electrode 12 is formed on the base material 11 in the same manner as in the step shown in FIG. 2A. Next, in the step shown in FIG. 5B, the gate insulating layer 13 covering the gate electrode 12 is formed on the base material 11. The method for forming the gate insulating layer 13 is not particularly limited and may be appropriately selected depending on the intended purpose. For example, a sputtering method, a pulse laser deposit (PLD) method, a chemical vapor deposition (CVD) method, or an atomic layer deposition method can be used. A vacuum process such as a layer deposition (ALD) method can be used. As the material of the gate insulating layer 13, for example, SiO ₂ or the like can be used.

Next, in the steps shown in FIGS. 5 (c) and 5 (d), the semiconductor layer 14 is formed on the gate insulating layer 13 in the same manner as in the steps shown in FIGS. 3 (a) and 3 (b). .. Next, in the step shown in FIG. 6A, the source electrode 15 and the drain electrode 16 are formed on the semiconductor layer 14 in the same manner as in the step shown in FIG. 3C.

Next, in the steps shown in FIGS. 6 (b) and 6 (c), a protective layer 17 covering the source electrode 15 and the drain electrode 16 is formed on the semiconductor layer 14. For example, in the step shown in FIG. 6 (b), the protective layer forming coating liquid 170 is applied by a dip coating method, a spin coating method, a die coating method, or the like, and in the step shown in FIG. 6 (c), the protective layer forming coating is applied. A process of firing the liquid 170 at a third temperature to form the protective layer 17 can be mentioned. The material and thickness of the protective layer 17 can be appropriately selected as described above.

However, as a method for forming the protective layer 17, in addition to the above processes, for example, a vacuum such as a sputtering method, a pulse laser deposition (PLD) method, a chemical vapor deposition (CVD) method, or an atomic layer deposition (ALD) method is used. A process can be used.

In the manufacturing process of the present embodiment, the formation temperature (third temperature) of the protective layer 17 is set to be equal to or lower than the formation temperature (second temperature) of the semiconductor layer 14. For example, when the formation temperature (second temperature) of the semiconductor layer 14 is 400 ° C., the formation temperature (third temperature) of the protective layer 17 needs to be 400 ° C. or lower (for example, 350 to 400 ° C.). As described above, in the present embodiment, when two oxide layers, one of which is an oxide semiconductor layer, are vertically adjacent to each other, an upper oxide layer (protective layer 17 in the present embodiment) is formed. The temperature is set to be equal to or lower than the formation temperature of the lower oxide layer (semiconductor layer 14 in the present embodiment). This makes it possible to reduce the SS value of the field effect transistor 10A. That is, it is possible to improve the switching characteristics of the field effect transistor 10A.

<Example 1>
In Example 1, a bottom gate / top contact type field effect transistor 10 was manufactured.

-Formation of gate electrode 12-
First, a glass base material was prepared as the base material 11, and the gate electrode 12 was formed on the base material 11. Specifically, a Cr / Au laminated film was formed on the base material 11 by a vacuum vapor deposition method. After that, a photoresist was applied onto the Cr / Au laminated film, and a resist pattern was formed by prebaking, exposure with an exposure apparatus, and development. Then, the Cr / Au laminated film in the region where the resist pattern was not formed was dissolved and removed to form the gate electrode 12 made of the Cr / Au laminated film.

-Formation of gate insulating layer 13-
Next, a gate insulating layer 13 which is an oxide layer was formed on the base material 11 so as to cover the gate electrode 12. Specifically, first, 1.2 mL of cyclohexylbenzene, 1.95 mL of a lanthanumene 2-ethylhexanoate solution (La content 7%, Wako 122-03371, manufactured by Wako Chemical Co., Ltd.) and strontium 2-ethylhexanoate are added. Toluene solution (Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.) 0.57 mL and 2-ethylhexanoic acid zirconium oxide mineral spirit solution (Zr content 12%, Wako 269-01116, manufactured by Wako Chemical Co., Ltd.) ) 0.09 mL was mixed to prepare a coating solution 130 for forming a gate insulating layer.

Next, the coating liquid 130 for forming the gate insulating layer was dropped onto the base material 11 and spin-coated under predetermined conditions. Then, the base material 11 to which the coating liquid 130 for forming the gate insulating layer was dropped was heated at about 120 ° C. for about 1 hour using an oven (drying step). Next, the base material 11 was heated at about 400 ° C. for about 3 hours using an oven to form the gate insulating layer 13 which is an oxide insulating layer from the coating liquid 130 for forming the gate insulating layer (firing step).

-Formation of semiconductor layer 14-
Next, the semiconductor layer 14 was formed on the gate insulating layer 13. Specifically, first, weighed indium nitrate of _{3.55g (In (NO 3) 3} · 3H 2 O) and 0.139g of strontium chloride _{(SrCl 2 · 6H 2 O)} , 1,2- propanediol 20 mL and 20 mL of ethylene glycol monomethyl ether were added and mixed and dissolved at room temperature to prepare a coating liquid 140 for forming an oxide semiconductor layer.

Next, the oxide semiconductor layer forming coating liquid 140 was applied onto the gate insulating layer 13 in a predetermined pattern using an inkjet device. Then, the base material 11 was heated on a hot plate heated to about 120 ° C. for about 10 minutes (drying step). Next, the base material 11 was heated at about 400 ° C. for about 1 hour using an oven to form the semiconductor layer 14 which is an oxide semiconductor layer from the oxide semiconductor layer forming coating liquid 140 (firing step).

-Formation of source electrode 15 and drain electrode 16-
Next, an Au film was formed on the semiconductor layer 14 by using a shadow mask and a vacuum vapor deposition method to form a source electrode 15 and a drain electrode 16 having a predetermined pattern. Through the above steps, the field effect transistor 10 was completed.

-Transistor performance evaluation-
The obtained field effect transistor 10 was evaluated for transistor performance using a semiconductor parameter analyzer device (semiconductor parameter analyzer B1500A manufactured by Agilent Technologies). Specifically, the source / drain voltage Vds was set to 10V, the gate voltage was changed from Vg = −15V to + 15V, and the current-voltage characteristic (transmission characteristic) was evaluated. Then, the SS value was calculated.

<Example 2>
In Example 2, the heating conditions in the oven when forming the semiconductor layer 14 (in Example 1, about 400 ° C. for about 1 hour) were changed to about 350 ° C. for about 1 hour. The bottom gate / top contact type field effect transistor 10 shown in FIG. 1 was manufactured by the same method. Moreover, the SS value was calculated in the same manner as in Example 1.

<Comparative example 1>
In Comparative Example 1, the heating conditions in the oven when forming the semiconductor layer 14 (in Example 1, about 400 ° C. for about 1 hour) were changed to about 450 ° C. for about 1 hour, except that the heating conditions were the same as in Example 1. The bottom gate / top contact type field effect transistor 10 shown in FIG. 1 was manufactured by the same method. Moreover, the SS value was calculated in the same manner as in Example 1.

<Summary of results of Examples 1 and 2 and Comparative Example 1>

実施例１及び２、比較例１の結果を表１にまとめた。表１に示すように、実施例１及び２ではＳＳ値が良好な値であったのに対し、比較例１ではＳＳ値が実施例１及び２の２倍程度の大きな値となった。

The results of Examples 1 and 2 and Comparative Example 1 are summarized in Table 1. As shown in Table 1, the SS value was a good value in Examples 1 and 2, whereas the SS value in Comparative Example 1 was about twice as large as that of Examples 1 and 2.

In the manufacturing methods of Examples 1 and 2, the SS value is determined so that the temperature of the manufacturing process of the semiconductor layer 14 (upper layer) in the subsequent process is equal to or lower than the temperature of the manufacturing process of the gate insulating layer 13 (lower layer) in the previous process. It is considered that it was reduced. On the other hand, in Comparative Example 1, the temperature of the manufacturing process of the semiconductor layer 14 (upper layer) in the subsequent process is higher than the temperature of the manufacturing process of the gate insulating layer 13 (lower layer) in the previous process, which causes an increase in the SS value. It is thought that it was.

<Example 3>
In Example 3, a bottom gate / top contact type field effect transistor 10A was produced.

-Formation of gate electrode 12-
First, a glass base material was prepared as the base material 11, and the gate electrode 12 was formed on the base material 11 in the same manner as in Example 1.

-Formation of gate insulating layer 13-
_{Next, a SiO 2} film was formed on the base material 11 by RF sputtering so as to cover the gate electrode 12 so that the thickness was about 200 nm, and the gate insulating layer 13 was formed.

-Formation of semiconductor layer 14-
Next, the semiconductor layer 14 was formed on the gate insulating layer 13 in the same manner as in Example 1.

-Formation of source electrode 15 and drain electrode 16-
Next, a source electrode 15 and a drain electrode 16 having a predetermined pattern were formed on the semiconductor layer 14 in the same manner as in Example 1.

-Formation of protective layer 17-
Next, a protective layer 17 which is an oxide layer was formed on the semiconductor layer 14 so as to cover the source electrode 15 and the drain electrode 16. Specifically, first, 0.99 mL of a lanthanum 2-ethylhexanoate toluene solution (La content 7%, Wako 122-033371, manufactured by Wako Chemical Co., Ltd.) and a strontium 2-ethylhexanoate toluene solution (La content 7%, manufactured by Wako Chemical Co., Ltd.) are added to 1 mL of toluene. A coating solution 170 for forming a protective layer was prepared by mixing with 0.27 mL of Sr content 2%, Wako 195-09561, manufactured by Wako Chemical Co., Ltd.).

Next, a coating liquid 170 for forming a protective layer was dropped onto the base material 11, and spin coating was performed under predetermined conditions. Then, the base material 11 to which the coating liquid 170 for forming the protective layer was dropped was heated at about 120 ° C. for about 1 hour using an oven (drying step). Next, the base material 11 was heated at about 400 ° C. for about 1 hour using an oven to form the protective layer 17 which is an oxide insulating layer from the coating liquid 170 for forming the protective layer (firing step). Through the above steps, the field effect transistor 10A was completed.

-Transistor performance evaluation-
For the obtained field effect transistor 10A, the SS value was calculated in the same manner as in Example 1.

<Example 4>
In Example 4, the heating conditions in the oven for forming the protective layer 17 (in Example 3, about 400 ° C. for about 1 hour) were changed to about 350 ° C. for about 1 hour. The bottom gate / top contact type field effect transistor 10A shown in FIG. 4 was produced by the same method. Moreover, the SS value was calculated in the same manner as in Example 3.

<Comparative example 2>
In Comparative Example 2, the heating conditions in the oven when forming the protective layer 17 (in Example 3, about 400 ° C. for about 1 hour) were changed to about 450 ° C. for about 1 hour, except that the heating conditions were the same as in Example 3. The bottom gate / top contact type field effect transistor 10A shown in FIG. 4 was produced by the same method. Moreover, the SS value was calculated in the same manner as in Example 3.

<Summary of results of Examples 3 and 4 and Comparative Example 2>

実施例３及び４、比較例２の結果を表２にまとめた。表２に示すように、実施例３及び４ではＳＳ値が良好な値であったのに対し、比較例２ではＳＳ値が実施例３及び４の２倍程度の大きな値となった。

The results of Examples 3 and 4 and Comparative Example 2 are summarized in Table 2. As shown in Table 2, the SS value was a good value in Examples 3 and 4, whereas the SS value in Comparative Example 2 was about twice as large as that of Examples 3 and 4.

In the manufacturing methods of Examples 3 and 4, the SS value is reduced when the temperature of the manufacturing process of the protective layer 17 (upper layer) in the subsequent process is lower than the temperature of the manufacturing process of the semiconductor layer 14 (lower layer) in the previous process. It is probable that it was made. On the other hand, in Comparative Example 1, the temperature of the manufacturing process of the protective layer 17 (upper layer) in the subsequent process was higher than the temperature of the manufacturing process of the semiconductor layer 14 (lower layer) in the previous process, which resulted in an increase in the SS value. It is considered to be.

As described above, from the results of Examples 1 to 4 and Comparative Examples 1 and 2, when two oxide layers, one of which is an oxide semiconductor layer, are vertically adjacent to each other in the field effect transistor, the upper layer is used. The SS value can be reduced by setting the formation temperature of the oxide layer of the above layer to be equal to or lower than the formation temperature of the lower oxide layer. That is, it is possible to improve the switching characteristics of the field effect transistor.

<Second Embodiment>
The second embodiment shows an example of a display element, a display device, and a system using the field effect transistor according to the first embodiment. In the second embodiment, the description of the same components as those in the above-described embodiment may be omitted.

(Display element)
The display element according to the second embodiment has at least an optical control element, a drive circuit for driving the optical control element, and, if necessary, other members. The optical control element is not particularly limited as long as it is an element that controls the optical output according to the drive signal, and can be appropriately selected according to the purpose. For example, an electroluminescence (EL) element or an electrochromic (EC) element. ) Elements, liquid crystal elements, electrophoresis elements, electrowetting elements and the like.

The drive circuit is not particularly limited as long as it has the field-effect transistor according to the first embodiment, and can be appropriately selected depending on the intended purpose. The other members are not particularly limited and may be appropriately selected depending on the intended purpose.

Since the display element according to the second embodiment has the field effect transistor according to the first embodiment, the SS value is low and good switching characteristics can be obtained. As a result, high quality display can be performed.

(Display device)
The display device according to the second embodiment has at least a plurality of display elements, a plurality of wirings, and a display control device according to the second embodiment, and further, if necessary, other members. Has. The plurality of display elements are not particularly limited as long as they are the plurality of display elements according to the second embodiment arranged in a matrix, and can be appropriately selected depending on the intended purpose.

The plurality of wirings are not particularly limited as long as the gate voltage and the image data signal can be individually applied to each field effect transistor in the plurality of display elements, and can be appropriately selected depending on the intended purpose.

The display control device is not particularly limited as long as the gate voltage and signal voltage of each field effect transistor can be individually controlled via a plurality of wirings according to the image data, and is appropriately selected according to the purpose. can do. The other members are not particularly limited and may be appropriately selected depending on the intended purpose.

Since the display device according to the second embodiment has a display element including the field-effect transistor according to the first embodiment, it is possible to display a high-quality image.

(system)
The system according to the second embodiment includes at least a display device according to the second embodiment and an image data creation device. The image data creation device creates image data based on the image information to be displayed, and outputs the image data to the display device.

Since the system includes the display device according to the second embodiment, it is possible to display image information in high definition.

Hereinafter, the display element, the display device, and the system according to the second embodiment will be specifically described.

FIG. 7 shows a schematic configuration of the television device 500 as the system according to the second embodiment. The connection line in FIG. 7 shows a typical signal or information flow, and does not represent all the connection relationships of each block.

The television device 500 according to the second embodiment includes a main control device 501, a tuner 503, an AD converter (ADC) 504, a demodulation circuit 505, a TS (Transport Stream) decoder 506, an audio decoder 511, and a DA converter (DAC). 512, audio output circuit 513, speaker 514, video decoder 521, video / OSD synthesis circuit 522, video output circuit 523, display device 524, OSD drawing circuit 525, memory 531, operation device 532, drive interface (drive IF) 541, It includes a hard disk device 542, an optical disk device 543, an IR receiver 551, a communication control device 552, and the like.

The main control device 501 controls the entire television device 500, and is composed of a CPU, a flash ROM, a RAM, and the like. The flash ROM stores a program written in a code that can be deciphered by the CPU, various data used for processing by the CPU, and the like. The RAM is a working memory.

The tuner 503 selects the broadcast of a preset channel from the broadcast waves received by the antenna 610. The ADC 504 converts the output signal (analog information) of the tuner 503 into digital information. The demodulation circuit 505 demodulates the digital information from the ADC 504.

The TS decoder 506 TS-decodes the output signal of the demodulation circuit 505 and separates the audio information and the video information. The audio decoder 511 decodes the audio information from the TS decoder 506. The DA converter (DAC) 512 converts the output signal of the audio decoder 511 into an analog signal.

The audio output circuit 513 outputs the output signal of the DA converter (DAC) 512 to the speaker 514. The video decoder 521 decodes the video information from the TS decoder 506. The video / OSD synthesis circuit 522 synthesizes the output signal of the video decoder 521 and the output signal of the OSD drawing circuit 525.

The video output circuit 523 outputs the output signal of the video / OSD synthesis circuit 522 to the display device 524. The OSD drawing circuit 525 includes a character generator for displaying characters and figures on the screen of the display device 524, and generates a signal including display information in response to an instruction from the operating device 532 and the IR receiver 551. To do.

AV (Audio-Visual) data and the like are temporarily stored in the memory 531. The operation device 532 includes an input medium (not shown) such as a control panel, and notifies the main control device 501 of various information input by the user. The drive IF541 is a bidirectional communication interface, and conforms to ATAPI (AT Attachment Packet Interface) as an example.

The hard disk device 542 is composed of a hard disk, a drive device for driving the hard disk, and the like. The drive device records the data on the hard disk and reproduces the data recorded on the hard disk. The optical disk device 543 records data on an optical disk (for example, a DVD) and reproduces the data recorded on the optical disk.

The IR receiver 551 receives an optical signal from the remote controller transmitter 620 and notifies the main control device 501. The communication control device 552 controls communication with the Internet. Various information can be obtained via the Internet.

The display device 524 has a display device 700 and a display control device 780, as shown in FIG. 8 as an example. As an example, as shown in FIG. 9, the display 700 has a display 710 in which a plurality of (here, n × m) display elements 702 are arranged in a matrix.

Further, as shown in FIG. 10 as an example, the display 710 has n scanning lines (X0, X1, X2, X3, ..., Xn) arranged at equal intervals along the X-axis direction. -2, Xn-1), m data lines (Y0, Y1, Y2, Y3, ..., Ym-1) arranged at equal intervals along the Y-axis direction, in the Y-axis direction It has m current supply lines (Y0i, Y1i, Y2i, Y3i, ..., Ym-1i) arranged at equal intervals along the line. Then, the display element 702 can be specified by the scanning line and the data line.

As an example, each display element 702 has an organic EL (electroluminescence) element 750 and a drive circuit 720 for causing the organic EL element 750 to emit light. That is, the display 710 is a so-called active matrix type organic EL display. The display 710 is a color-compatible 32-inch display. The size is not limited to this.

As shown in FIG. 12, the organic EL element 750 has an organic EL thin film layer 740, a cathode 712, and an anode 714.

The organic EL element 750 can be arranged next to the field effect transistor, for example. In this case, the organic EL element 750 and the field effect transistor can be formed on the same base material. However, the present invention is not limited to this, and for example, the organic EL element 750 may be arranged on the field effect transistor. In this case, since transparency is required for the gate electrode, ITO, In ₂ O ₃ , SnO ₂ , ZnO, and Ga-added ZnO, and Al-added ZnO and Sb are added to the gate electrode. A transparent oxide having conductivity such as SnO _{2 is used.}

In the organic EL element 750, aluminum (Al) is used for the cathode 712. In addition, magnesium (Mg) -silver (Ag) alloy, aluminum (Al) -lithium (Li) alloy, ITO (Indium Tin Oxide) and the like may be used. ITO is used for the anode 714. In addition, _{conductive oxides such as In 2} O ₃ , SnO ₂ , and ZnO, silver (Ag) -neodymium (Nd) alloys, and the like may be used.

The organic EL thin film layer 740 has an electron transport layer 742, a light emitting layer 744, and a hole transport layer 746. Then, the cathode 712 is connected to the electron transport layer 742, and the anode 714 is connected to the hole transport layer 746. When a predetermined voltage is applied between the anode 714 and the cathode 712, the light emitting layer 744 emits light.

Further, as shown in FIG. 11, the drive circuit 720 has two field-effect transistors 810 and 820 and a capacitor 830. The field effect transistor 810 operates as a switch element. The gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. Further, the drain electrode D is connected to one terminal of the capacitor 830.

The capacitor 830 is for storing the state of the field effect transistor 810, that is, data. The other terminal of the capacitor 830 is connected to a predetermined current supply line.

The field effect transistor 820 is for supplying a large current to the organic EL element 750. The gate electrode G is connected to the drain electrode D of the field effect transistor 810. The drain electrode D is connected to the anode 714 of the organic EL element 750, and the source electrode S is connected to a predetermined current supply line.

Therefore, when the field-effect transistor 810 is turned on, the organic EL element 750 is driven by the field-effect transistor 820.

The display control device 780 includes an image data processing circuit 782, a scanning line driving circuit 784, and a data line driving circuit 786, as shown in FIG. 13 as an example.

The image data processing circuit 782 determines the brightness of the plurality of display elements 702 in the display 710 based on the output signal of the video output circuit 523. The scanning line drive circuit 784 individually applies a voltage to n scanning lines in response to an instruction from the image data processing circuit 782. The data line drive circuit 786 individually applies a voltage to m data lines in response to an instruction from the image data processing circuit 782.

As is clear from the above description, in the television device 500 according to the present embodiment, the image data creation device is configured by the video decoder 521, the video / OSD synthesis circuit 522, the video output circuit 523, and the OSD drawing circuit 525. ing.

Further, in the above, the case where the optical control element is an organic EL element has been described, but the present invention is not limited to this, and a liquid crystal element, an electrochromic element, an electrophoresis element, or an electrowetting element may be used.

For example, when the optical control element is a liquid crystal element, a liquid crystal display is used as the display 710. In this case, as shown in FIG. 14, the current supply line in the display element 703 becomes unnecessary.

Further, in this case, as shown in FIG. 15 as an example, the drive circuit 730 is composed of only one field effect transistor 840 similar to the field effect transistor (810, 820) shown in FIG. Can be done. In the field effect transistor 840, the gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. Further, the drain electrode D is connected to the pixel electrode of the liquid crystal element 770 and the capacitor 760. Reference numerals 762 and 772 in FIG. 15 are counter electrodes (common electrodes) of the capacitor 760 and the liquid crystal element 770, respectively.

Further, in the above embodiment, the case where the system is a television device has been described, but the present invention is not limited to this. In short, the display device 524 may be provided as a device for displaying images and information. For example, it may be a computer system in which a computer (including a personal computer) and a display device 524 are connected.

Further, the display device 524 is used as a display means in a mobile phone, a portable music playback device, a portable video playback device, an electronic BOOK, a portable information device such as a PDA (Personal Digital Assistant), and an imaging device such as a still camera or a video camera. be able to. Further, the display device 524 can be used as a display means for displaying various information in a mobile system such as a car, an aircraft, a train, or a ship. Further, the display device 524 can be used as a display means for displaying various information in the measuring device, the analyzer, the medical device, and the advertising medium.

Although the preferred embodiments and the like have been described in detail above, the embodiments are not limited to the above-described embodiments and the like, and various embodiments and the like described above are used without departing from the scope of the claims. Modifications and substitutions can be added.

For example, in the first embodiment and its modification, the bottom gate / top contact type field effect transistor has been described as an example, but the present invention describes the bottom gate / bottom contact type field effect transistor and the top. It is also applicable to gate / top contact type field effect transistors and top gate / bottom contact type field effect transistors.

Further, in the first embodiment and its modification, the case where the gate insulating layer and the semiconductor layer are adjacent to each other and the case where the semiconductor layer and the protective layer are adjacent to each other have been described as an example, but the present invention is any one of them. In the case where two oxide layers, which are oxide semiconductor layers, are adjacent to each other on the upper and lower sides, it can be applied to other than the above examples. For example, a barrier layer which is an oxide layer is provided on the flexible base material, and an oxide semiconductor layer is provided on the barrier layer.

10, 10A field effect transistor 11 base material 12 gate electrode 13 gate insulating layer 14 semiconductor layer 15 source electrode 16 drain electrode 17 protective layer

Patent No. 5118811

Claims (9)

A method for manufacturing a field-effect transistor in which a first oxide layer and a second oxide layer, one of which is an oxide semiconductor layer, are adjacent to each other.
A step of forming the first oxide layer from a material containing an element that is at least one of Ga, Sc, Y, and a lanthanoid.
A step of forming the second oxide layer on the first oxide layer with a material containing an element containing at least one of Ga, Sc, Y, and a lanthanoid.
Forming temperature of the second oxide layer state, and are forming temperature below the first oxide layer,
The first oxide layer is an oxide insulating layer, and the second oxide layer is an oxide semiconductor layer.
The oxide insulating layer is a gate insulating layer.
A method for producing a field-effect transistor, wherein the gate insulating layer contains an element A, which is an alkaline earth metal, and an element B, which is at least one of Ga, Sc, Y, and a lanthanoid. .. A method for manufacturing a field-effect transistor in which a first oxide layer and a second oxide layer, one of which is an oxide semiconductor layer, are adjacent to each other.
A step of forming the first oxide layer from a material containing an element that is at least one of Ga, Sc, Y, and a lanthanoid.
A step of forming the second oxide layer on the first oxide layer with a material containing an element containing at least one of Ga, Sc, Y, and a lanthanoid.
Forming temperature of the second oxide layer state, and are forming temperature below the first oxide layer,
The first oxide layer is an oxide semiconductor layer, and the second oxide layer is an oxide insulating layer.
The oxide insulating layer is a protective layer,
A method for producing a field-effect transistor, wherein the protective layer contains an element A, which is an alkaline earth metal, and an element B, which is at least one of Ga, Sc, Y, and a lanthanoid. A method for manufacturing a field-effect transistor in which a first oxide layer and a second oxide layer, one of which is an oxide semiconductor layer, are adjacent to each other.
A step of forming the first oxide layer from a material containing an element containing at least one of Sc, Y, and a lanthanoid, and
It comprises a step of forming the second oxide layer on the first oxide layer with a material containing an element which is at least one of Sc, Y, and a lanthanoid.
A method for manufacturing a field-effect transistor, wherein the formation temperature of the second oxide layer is equal to or lower than the formation temperature of the first oxide layer. The method for manufacturing a field-effect transistor according to claim 3 , wherein the first oxide layer is an oxide insulating layer and the second oxide layer is an oxide semiconductor layer. The oxide insulating layer is a gate insulating layer.
The field effect type according to claim 4 , wherein the gate insulating layer contains an element A which is an alkaline earth metal and an element B which is at least one of Sc, Y, and a lanthanoid. Transistor manufacturing method. The method for manufacturing a field-effect transistor according to claim 3 , wherein the first oxide layer is an oxide semiconductor layer, and the second oxide layer is an oxide insulating layer. The oxide insulating layer is a protective layer,
The field-effect transistor according to claim 6 , wherein the protective layer contains an element A which is an alkaline earth metal and an element B which is at least one of Sc, Y, and a lanthanoid. Manufacturing method. In the step of forming the first oxide layer,
A first oxide layer forming coating solution is applied, of claims 1 to 7 and heating the first oxide layer forming coating liquid and forming a first oxide layer The method for manufacturing a field effect transistor according to any one of the following items. In the step of forming the second oxide layer,
Claims 1 to 8 , wherein the coating liquid for forming the second oxide layer is applied, and the coating liquid for forming the second oxide layer is heated to form the second oxide layer. The method for manufacturing a field effect transistor according to any one of the following items.

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