JP2019161182A - Field-effect transistor and method of manufacturing the same, display element, display device, system - Google Patents

Abstract

To provide a field-effect transistor of a double gate structure, in which a pin hole is hardly generated and variation in a threshold voltage can be suppressed.SOLUTION: The field-effect transistor includes: a first gate electrode formed on a base material; a first gate insulation layer formed on the first gate electrode; an active layer formed on the first gate electrode; a second gate insulation layer formed on the active layer; a second gate electrode formed on the second gate insulation layer; and a source electrode and drain electrode formed so as to connect with the active layer. Each of the first and second insulation layers is an oxide film including Ath element being an alkali earth metal, and Bth element being at least any one of Ga, Sc, Y, and lanthanoid.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a field effect transistor, a manufacturing method thereof, a display element, a display device, and a system.

  Liquid crystal display (LCD), organic EL (electroluminescence) display (OLED), flat and thin displays such as electronic paper (Flat Panel Display: FPD) use amorphous silicon or polycrystalline silicon as the active layer It is driven by a drive circuit including a field effect transistor.

In the development of FPD, attention is paid to the technology for manufacturing field effect transistors using oxide semiconductor films with high carrier mobility and small variation between elements in the channel formation region, and applying them to electronic devices, optical devices, etc. Has been. For example, a field-effect transistor using zinc oxide (ZnO), In ₂ O ₃ , In—Ga—Zn—O, or the like as an oxide semiconductor film has been proposed.

In addition, a field effect transistor having a double gate structure has been proposed (see, for example, Patent Document 1). In this field effect transistor, it is described that SiO ₂ is formed as the first gate insulating layer and the second gate insulating layer in order to suppress the fluctuation of the threshold voltage, and the vapor phase method is preferable as the film forming method. Yes. However, it was found that in SiO _{2 formed} by the vapor phase method, pinholes are likely to occur, and the threshold voltage fluctuation is adversely affected.

  An object of the present invention is to provide a field effect transistor having a double gate structure in which pinholes hardly occur and fluctuations in threshold voltage can be suppressed.

  The field effect transistor includes a first gate electrode formed on a base material, a first gate insulating layer formed on the first gate electrode, and an active layer formed on the first gate insulating layer. A second gate insulating layer formed on the active layer, a second gate electrode formed on the second gate insulating layer, and a source and drain electrode formed so as to be connected to the active layer, Wherein the first gate insulating layer and the second gate insulating layer are an A element that is an alkaline earth metal, and a B element that is at least one of Ga, Sc, Y, and a lanthanoid, It is a requirement that the oxide film contains.

  According to the disclosed technique, it is possible to provide a field effect transistor having a double gate structure in which pinholes are hardly generated and fluctuations in threshold voltage can be suppressed.

1 is a cross-sectional view illustrating a field effect transistor according to a first embodiment. It is a figure which illustrates the manufacturing process of the field effect transistor which concerns on 1st Embodiment. It is sectional drawing which illustrates the field effect transistor which concerns on the modification of 1st Embodiment. It is a block diagram which shows the structure of the television apparatus which concerns on 2nd Embodiment. It is explanatory drawing (the 1) of the television apparatus which concerns on 2nd Embodiment. It is explanatory drawing (the 2) of the television apparatus which concerns on 2nd Embodiment. It is explanatory drawing (the 3) of the television apparatus which concerns on 2nd Embodiment. It is explanatory drawing of the display element which concerns on 2nd Embodiment. It is explanatory drawing of organic EL which concerns on 2nd Embodiment. Explanatory drawing of the television apparatus which concerns on 2nd Embodiment (the 4) It is explanatory drawing (the 1) of the other display element which concerns on 2nd Embodiment. It is explanatory drawing (the 2) of the other display element which concerns on 2nd Embodiment.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description may be omitted.

<First Embodiment>
[Structure of field effect transistor]
FIG. 1 is a cross-sectional view illustrating a field effect transistor according to the first embodiment. Referring to FIG. 1, a field effect transistor 10 includes a substrate 11, a first gate electrode 12, a first gate insulating layer 13, an active layer 14, a second gate insulating layer 15, and a second gate. This is a double-gate field effect transistor having an electrode 16, a source electrode 17, and a drain electrode 18. The field effect transistor 10 is a typical example of a semiconductor device according to the present invention.

  In the field effect transistor 10, a first gate electrode 12 is formed on an insulating substrate 11, and a first gate insulating layer 13 is formed so as to cover the first gate electrode 12. An active layer 14 is formed on the first gate insulating layer 13, and a second gate insulating layer 15 is formed so as to cover the active layer 14. Further, a second gate electrode 16, a source electrode 17, and a drain electrode 18 are formed on the second gate insulating layer 15. The source electrode 17 and the drain electrode 18 are connected to the active layer 14 through through holes formed in the second gate insulating layer 15. Hereinafter, each component of the field effect transistor 10 will be described in detail.

  In the present embodiment, for convenience, the second gate electrode 16 side is defined as the upper side or one side, and the substrate 11 side is defined as the lower side or the other side. Also, the surface on the second gate electrode 16 side of each part is the upper surface or one surface, and the surface on the substrate 11 side is the lower surface or the other surface. However, the field effect transistor 10 can be used upside down, or can be arranged at an arbitrary angle. Moreover, planar view refers to viewing the object from the normal direction of the upper surface of the base material 11, and planar shape refers to the shape of the object viewed from the normal direction of the upper surface of the base material 11. .

  There is no restriction | limiting in particular as a shape of the base material 11, a structure, and a magnitude | size, According to the objective, it can select suitably. There is no restriction | limiting in particular as a material of the base material 11, Although it can select suitably according to the objective, For example, a glass base material, a ceramic base material, a plastic base material, a film base material etc. can be used.

  There is no restriction | limiting in particular as a glass base material, Although it can select suitably according to the objective, For example, an alkali free glass, a silica glass, etc. are mentioned. Moreover, there is no restriction | limiting in particular as a plastic base material or a film base material, Although it can select suitably according to the objective, For example, a polycarbonate (PC), a polyimide (PI), a polyethylene terephthalate (PET), a polyethylene naphthalate (PEN) and the like.

  The first gate electrode 12 is formed in a predetermined region on the base material 11. The first gate electrode 12 is one gate electrode constituting a double gate. There is no restriction | limiting in particular as a material of the 1st gate electrode 12, Although it can select suitably according to the objective, For example, aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), copper (Cu), zinc (Zn), nickel (Ni), chromium (Cr), tantalum (Ta), molybdenum (Mo), titanium (Ti) and other metals, alloys thereof, and mixtures of these metals Etc. can be used. In addition, conductive oxides such as indium oxide, zinc oxide, tin oxide, gallium oxide, and niobium oxide, composite compounds thereof, mixtures thereof, and the like may be used. Further, an organic conductor such as polyethylene dioxythiophene (PEDOT) or polyaniline (PANI) may be used. There is no restriction | limiting in particular as an average film thickness of the 1st gate electrode 12, Although it can select suitably according to the objective, 10 nm-1 micrometer are preferable and 50 nm-300 nm are more preferable.

  The first gate insulating layer 13 is a layer that is provided between the first gate electrode 12 and the active layer 14 and insulates the first gate electrode 12 and the active layer 14. There is no restriction | limiting in particular as an average film thickness of the 1st gate insulating layer 13, Although it can select suitably according to the objective, 50 nm-3 micrometers are preferable, and 100 nm-1 micrometer are more preferable.

  The active layer 14 is formed on the first gate insulating layer 13. A part of the active layer 14 becomes a channel region. There is no restriction | limiting in particular as an average film thickness of the active layer 14, Although it can select suitably according to the objective, 5 nm-1 micrometer are preferable and 10 nm-0.5 micrometer are more preferable.

  There is no restriction | limiting in particular as a material of the active layer 14, Although it can select suitably according to the objective, For example, a polycrystalline silicon (p-Si), an amorphous silicon (a-Si), In-Ga-Zn-. Examples thereof include oxide semiconductors such as O and organic semiconductors such as pentacene. Among these, it is preferable to use an oxide semiconductor from the viewpoint of the stability of the interface with the first gate insulating layer 13.

  The second gate insulating layer 15 is provided between the active layer 14 and the second gate electrode 16 and is a layer for insulating the active layer 14 and the second gate electrode 16. There is no restriction | limiting in particular as an average film thickness of the 2nd gate insulating layer 15, Although it can select suitably according to the objective, 50 nm-3 micrometers are preferable, and 100 nm-1 micrometer are more preferable.

  The second gate electrode 16 is formed on the second gate insulating layer 15 in a region overlapping with the first gate electrode 12 and the active layer 14 in plan view. The second gate electrode 16 is the other gate electrode constituting a double gate. There is no restriction | limiting in particular as a material of the 2nd gate electrode 16, Although it can select suitably according to the objective, For example, aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), silver (Ag), copper (Cu), zinc (Zn), nickel (Ni), chromium (Cr), tantalum (Ta), molybdenum (Mo), titanium (Ti) and other metals, alloys thereof, and mixtures of these metals Etc. can be used. In addition, conductive oxides such as indium oxide, zinc oxide, tin oxide, gallium oxide, and niobium oxide, composite compounds thereof, mixtures thereof, and the like may be used. Further, an organic conductor such as polyethylene dioxythiophene (PEDOT) or polyaniline (PANI) may be used. There is no restriction | limiting in particular as an average film thickness of the 2nd gate electrode 16, Although it can select suitably according to the objective, 10 nm-1 micrometer are preferable and 50 nm-300 nm are more preferable.

  The source electrode 17 and the drain electrode 18 are formed on the second gate insulating layer 15. The source electrode 17 and the drain electrode 18 are formed at a predetermined interval with the second gate electrode 16 interposed therebetween. The source electrode 17 and the drain electrode 18 are electrodes for taking out a current in response to application of a gate voltage to the first gate electrode 12. Note that the wiring connected to the source electrode 17 and the drain electrode 18 may be formed in the same layer together with the source electrode 17 and the drain electrode 18.

  The material of the source electrode 17 and the drain electrode 18 is not particularly limited and can be appropriately selected depending on the purpose. For example, aluminum (Al), platinum (Pt), palladium (Pd), gold (Au) , Silver (Ag), Copper (Cu), Zinc (Zn), Nickel (Ni), Chromium (Cr), Tantalum (Ta), Molybdenum (Mo), Titanium (Ti), etc., alloys thereof, these metals A mixture of the above can be used.

  In addition, conductive oxides such as indium oxide, zinc oxide, tin oxide, gallium oxide, and niobium oxide, composite compounds thereof, mixtures thereof, and the like may be used. Further, an organic conductor such as polyethylene dioxythiophene (PEDOT) or polyaniline (PANI) may be used. There is no restriction | limiting in particular as an average film thickness of the source electrode 17 and the drain electrode 18, Although it can select suitably according to the objective, 10 nm-1 micrometer are preferable and 50 nm-300 nm are more preferable.

  The first gate insulating layer 13 and the second gate insulating layer 15 are oxides. An oxide used in this embodiment (hereinafter referred to as a first oxide) includes an element A that is an alkaline earth metal, gallium (Ga), scandium (Sc), yttrium (Y), and a lanthanoid. It contains at least one element B and, if necessary, other components. The alkaline earth metal contained in the first oxide may be one type or two or more types.

  Examples of the alkaline earth metal include beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), and radium (Ra).

  Lanthanoids include lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium. (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

  The first oxide is preferably a paraelectric amorphous oxide. The paraelectric amorphous oxide is stable in the atmosphere and can stably form an amorphous structure in a wide composition range. However, crystals may be included in part of the first oxide.

  Forming the first gate insulating layer 13 and the second gate insulating layer 15 with an amorphous material is a preferable form in terms of improving the characteristics of the transistor. This is because if the first gate insulating layer 13 and the second gate insulating layer 15 are formed of a crystalline material, the leakage current due to the crystal grain boundary cannot be suppressed low, leading to deterioration of transistor characteristics.

  In addition, it is necessary that the first gate insulating layer 13 and the second gate insulating layer 15 are paraelectric in terms of reducing hysteresis in the transfer characteristics of the transistor. The exception is the special case where the transistor is used for a memory or the like, but it is not preferable that hysteresis exists in a device that normally uses the switching characteristics of the transistor.

  A paraelectric material is a dielectric material other than a piezoelectric material, pyroelectric material, or ferroelectric material, that is, a dielectric material that does not generate polarization due to pressure or has spontaneous polarization in the absence of an external electric field. Point to. In addition, the piezoelectric body, pyroelectric body and ferroelectric body need to be crystals in order to exhibit their characteristics. That is, when the first gate insulating layer 13 and the second gate insulating layer 15 are formed of an amorphous material, the first gate insulating layer 13 and the second gate insulating layer 15 inevitably become a paraelectric material.

  Alkaline earth metal oxides easily react with moisture and carbon dioxide in the atmosphere and easily change to hydroxides and carbonates, and are not suitable for application to electronic devices alone. In addition, simple oxides such as Ga, Sc, Y, and lanthanoids are easily crystallized, and leakage current becomes a problem. However, the first oxide is suitable for the first gate insulating layer 13 and the second gate insulating layer 15 because it is stable in the atmosphere and can form a paraelectric amorphous film in a wide composition region.

  Ce is specifically tetravalent among lanthanoids and forms crystals with a perovskite structure with an alkaline earth metal. Therefore, in order to obtain an amorphous phase, the element B is preferably not Ce.

  A crystal phase such as a spinel structure exists between the alkaline earth metal oxide and the Ga oxide, but these crystals do not precipitate unless the temperature is very high compared to the perovskite structure crystal (generally 1000 ° C. or more). ). In addition, the existence of a stable crystal phase has not been reported between the alkaline earth metal oxide and the oxide composed of Sc, Y, and lanthanoid, and crystal precipitation from the amorphous phase even after a high temperature post-process. Is rare. Furthermore, when an oxide containing an alkaline earth metal and Ga, Sc, Y, and a lanthanoid is composed of three or more kinds of metal elements, the amorphous phase is further stabilized.

  From the viewpoint of producing a high dielectric constant film, it is preferable to increase the composition ratio of elements such as Ba, Sr, Lu, and La. Further, since the first oxide has an excellent barrier property against moisture and oxygen in the atmosphere, it can also be used as a material for an interlayer insulating film.

  The first oxide preferably further includes a C element that is at least one of Al, Ti, Zr, Hf, Nb, and Ta. As a result, the amorphous phase is further stabilized, and thermal stability, heat resistance, and denseness can be further improved.

  The composition ratio of the element A, which is an alkaline earth metal in the first oxide, to the element B, which is at least one of Ga, Sc, Y, and a lanthanoid, is not particularly limited and depends on the purpose. However, the following range is preferable.

In the first oxide, as a composition ratio (element A: element B) of an element A that is an alkaline earth metal and element B that is at least one of Ga, Sc, Y, and a lanthanoid the oxide _{(BeO, MgO, CaO, SrO} , BaO, Ga 2 O 3, Sc 2 O 3, Y 2 O 3, La 2 O 3, Ce 2 O 3, Pr 2 O 3, Nd 2 O 3, Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , in lu ₂ O ₃₎ in terms of, 10.0mol% ~67.0mol%: 33.0mol% ~90.0mol% is preferred.

  An element A which is an alkaline earth metal in the first oxide, an element B which is at least one of Ga, Sc, Y, and a lanthanoid, and Al, Ti, Zr, Hf, Nb, and Ta. There is no restriction | limiting in particular as a composition ratio with the C element which is at least any one, Although it can select suitably according to the objective, It is preferable that it is the following ranges.

In the first oxide, an A element that is an alkaline earth metal, a B element that is at least one of Ga, Sc, Y, and a lanthanoid, Al, Ti, Zr, Hf, Nb, and Ta As the composition ratio (A element: B element: C element) with at least one of the above elements, oxides (BeO, MgO, CaO, SrO, BaO, Ga ₂ O ₃ , Sc ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₃ , Ce ₂ O ₃ , Pr ₂ O ₃ , Nd ₂ O ₃ , Pm ₂ O ₃ , Sm ₂ O ₃ , Eu ₂ O ₃ , Gd ₂ O ₃ , Tb ₂ O ₃ , Dy ₂ O ₃ , Ho ₂ O ₃ , Er ₂ O ₃ , Tm ₂ O ₃ , Yb ₂ O ₃ , Lu ₂ O ₃ , Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfO ₂ , Nb ₂ O ₅ , Ta ₂ in O ₅₎ conversion, 5.0mol% ~22.0m l%: 33.0mol% ~90.0mol: 5.0mol% ~45.0mol% is preferred.

Oxide in the first oxide _{(BeO, MgO, CaO, SrO} , BaO, Ga 2 O 3, Sc 2 O 3, Y 2 O 3, La 2 O 3, Ce 2 O 3, Pr 2 O 3, _{Nd 2 O 3, Pm 2 O} 3, Sm 2 O 3, Eu 2 O 3, Gd 2 O 3, Tb 2 O 3, Dy 2 O 3, Ho 2 O 3, Er 2 O 3, Tm 2 O 3, The ratio of Yb ₂ O ₃ , Lu ₂ O ₃ , Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfO ₂ , Nb ₂ O ₅ , Ta ₂ O ₅ ) is, for example, fluorescent X-ray analysis, electron beam microanalysis ( EPMA), dielectric-coupled plasma emission spectroscopy (ICP-AES), and the like can be calculated by analyzing the cation element of oxide.

[Method for Manufacturing Field Effect Transistor]
Next, a method for manufacturing the field effect transistor shown in FIG. 1 will be described. FIG. 2 is a diagram illustrating a manufacturing process of the field effect transistor according to the first embodiment.

  First, in the step shown in FIG. 2A, the base material 11 is prepared. Then, a first gate electrode 12 having a predetermined shape is formed on the substrate 11. From the viewpoint of cleaning the surface of the substrate 11 and improving adhesion, it is preferable to perform pretreatment such as oxygen plasma, UV ozone, and UV irradiation cleaning before forming the first gate electrode 12. The material and thickness of the base material 11 and the first gate electrode 12 can be appropriately selected as described above.

  There is no restriction | limiting in particular as a formation method of the 1st gate electrode 12, According to the objective, it can select suitably, For example, film-forming by a sputtering method, a vacuum evaporation method, a dip coating method, a spin coat method, a die coat method etc. Subsequently, a method of patterning by photolithography can be mentioned. Another example is a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, or gravure.

  Next, in the step shown in FIG. 2B, the first gate insulating layer 13 that covers the first gate electrode 12 is formed on the base material 11. There is no restriction | limiting in particular as a formation method of the 1st gate insulating layer 13, According to the objective, it can select suitably, For example, a sputtering method, a pulse laser deposition (PLD) method, a chemical vapor deposition (CVD) method And vacuum processes such as atomic layer deposition (ALD). As another example of the method of forming the first gate insulating layer 13, a coating liquid (gate insulating layer forming coating liquid) containing a first oxide precursor is prepared, and the gate insulating layer forming coating liquid is prepared. The method of apply | coating or printing on a to-be-coated article, and baking this on suitable conditions is mentioned.

  Next, in a step shown in FIG. 2C, an active layer 14 having a predetermined shape is formed on the first gate insulating layer 13. There is no restriction | limiting in particular as a formation method of the active layer 14, According to the objective, it can select suitably, For example, after film-forming by a sputtering method, a vacuum evaporation method, a dip coating method, a spin coat method, a die coating method etc., There is a method of patterning by photolithography. Another example is a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, or gravure. The material and thickness of the active layer 14 can be appropriately selected as described above.

  Next, in the step shown in FIG. 2D, a second gate insulating layer 15 that covers the active layer 14 is formed on the first gate insulating layer 13. There is no restriction | limiting in particular as a formation method of the 2nd gate insulating layer 15, According to the objective, it can select suitably, For example, a sputtering method, a pulse laser deposition (PLD) method, a chemical vapor deposition (CVD) method And vacuum processes such as atomic layer deposition (ALD). As another example of the method of forming the second gate insulating layer 15, a coating liquid (gate insulating layer forming coating liquid) containing a first oxide precursor is prepared, and the gate insulating layer forming coating liquid is prepared. The method of apply | coating or printing on a to-be-coated article, and baking this on suitable conditions is mentioned.

  Next, in the step shown in FIG. 2E, a second gate electrode 16 having a predetermined shape is formed on the second gate insulating layer 15. The material and thickness of the second gate electrode 16 can be appropriately selected as described above.

  There is no restriction | limiting in particular as a formation method of the 2nd gate electrode 16, According to the objective, it can select suitably, For example, film-forming by a sputtering method, a vacuum evaporation method, a dip coating method, a spin coat method, a die coat method etc. Subsequently, a method of patterning by photolithography can be mentioned. Another example is a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, or gravure.

  Next, in the step shown in FIG. 2F, a source electrode 17 and a drain electrode 18 having a predetermined shape are formed on the second gate insulating layer 15. Specifically, first, a through hole that penetrates the second gate insulating layer 15 and exposes the surface of the active layer 14 is formed by etching, laser processing, or the like. Thereafter, the through hole is filled, and the source electrode 17 and the drain electrode 18 extending from the through hole to the second gate insulating layer 15 are formed. Although not shown, when a conductive film pattern is formed between the through hole and the active layer 14, the conductive film pattern can be used as a source electrode and a drain electrode, and the conductive film filled in the through hole can be used as a lead-out wiring. It is.

  There is no restriction | limiting in particular as a formation method of the source electrode 17 and the drain electrode 18, According to the objective, it can select suitably, For example, a sputtering method, a vacuum evaporation method, a dip coating method, a spin coat method, a die coat method etc. There is a method of patterning by photolithography after film formation. Another example is a method of directly forming a desired shape by a printing process such as ink jet, nanoimprint, or gravure. The material and thickness of the source electrode 17 and the drain electrode 18 can be appropriately selected as described above. Through the above steps, the field effect transistor 10 is completed.

  As described above, in the field effect transistor 10 according to the present exemplary embodiment, the first gate insulating layer 13 and the second gate insulating layer 15 include the element A that is an alkaline earth metal, Ga, Sc, Y, and An oxide film (first oxide film) containing a B element which is at least one of lanthanoids is used.

According to the study by the inventors, the use of the first oxide film as the first gate insulating layer 13 and the second gate insulating layer 15 causes the generation of pinholes as compared with the case where the SiO ₂ insulating film is used. Can be suppressed.

That is, when a pinhole is generated using an SiO ₂ insulating film as the first gate insulating layer 13 and the second gate insulating layer 15, the threshold voltage fluctuation cannot be suppressed, and the double-gate field effect transistor functions normally. No longer. On the other hand, by using the first oxide film as the first gate insulating layer 13 and the second gate insulating layer 15, it is possible to suppress the generation of pinholes, and thus it is possible to suppress fluctuations in the threshold voltage. Become. Further, by suppressing the generation of pinholes, the generation of leakage current can be suppressed.

<Modification of First Embodiment>
The modification of the first embodiment shows an example of a field effect transistor having a layer structure different from that of the first embodiment. In the modification of the first embodiment, the description of the same components as those of the already described embodiments may be omitted.

  FIG. 3 is a cross-sectional view illustrating a field effect transistor according to a modification of the first embodiment. Each field effect transistor 10A shown in FIG. 3 is a typical example of a semiconductor device according to the present invention.

  In the field effect transistor 10A shown in FIG. 3, an interlayer insulating film 19 that covers the second gate electrode 16 is provided on the second gate insulating layer 15, and a source electrode 17 and a drain electrode 18 are provided on the interlayer insulating film 19. This is different from the field effect transistor 10 (see FIG. 1). In the field effect transistor 10 </ b> A, the source electrode 17 and the drain electrode 18 are connected to the active layer 14 through through-holes formed in the second gate insulating layer 15 and the interlayer insulating film 19.

As the material of the interlayer insulating film 19 is not particularly limited and may be appropriately selected depending on the purpose, for example, it may be a silicon oxide film (SiO ₂₎ or the like. There is no restriction | limiting in particular as an average film thickness of the interlayer insulation film 19, Although it can select suitably according to the objective, 50 nm-3 micrometers are preferable, and 100 nm-1 micrometer are more preferable. There is no restriction | limiting in particular as a formation method of the interlayer insulation film 19, Although it can select suitably according to the objective, For example, plasma CVD method etc. can be used.

  In FIG. 3, the planar shape of the interlayer insulating film 19 is matched with the planar shape of the second gate insulating layer 15, but this is not limitative. For example, the planar shape of the interlayer insulating film 19 may be smaller than the planar shape of the second gate insulating layer 15. Alternatively, the planar shape of the interlayer insulating film 19 may be made larger than the planar shape of the second gate insulating layer 15 to cover the side surface of the second gate insulating layer 15.

  As described above, an interlayer insulating film may be provided over the second gate insulating layer. By providing an interlayer insulating film on the second gate insulating layer, field effect transistor components (active layer, first gate electrode, second gate electrode, etc.) are protected from moisture, oxygen, hydrogen, etc. in the atmosphere. can do. Further, by providing an interlayer insulating film on the second gate insulating layer, the field effect transistor can be protected from the material of the layer formed on the field effect transistor and the formation process thereof. Other effects are the same as those in the first embodiment.

<Second Embodiment>
In the second embodiment, an example of a display element, an image display device, and a system using the field effect transistor according to the first embodiment is shown. In the second embodiment, description of the same components as those of the already described embodiments may be omitted.

(Display element)
The display element according to the second embodiment includes at least a light control element and a drive circuit that drives the light control element, and further includes other members as necessary. The light control element is not particularly limited as long as it is an element that controls the light output according to the drive signal, and can be appropriately selected according to the purpose. For example, an electroluminescence (EL) element, an electrochromic (EC) ) Elements, liquid crystal elements, electrophoretic elements, electrowetting elements and the like.

  The drive circuit is not particularly limited as long as it has the field effect transistor according to the first embodiment, and can be appropriately selected according to the purpose. There is no restriction | limiting in particular as another member, According to the objective, it can select suitably.

  Since the display element according to the second embodiment includes the field-effect transistor according to the first embodiment, it is possible to suppress fluctuations in threshold voltage and good transistor characteristics. As a result, high quality display can be performed.

(Image display device)
The image display device according to the second embodiment includes at least a plurality of display elements according to the second embodiment, a plurality of wirings, and a display control device. It has a member. The plurality of display elements are not particularly limited as long as they are the display elements according to the plurality of second embodiments arranged in a matrix, and can be appropriately selected according to the purpose.

  The plurality of wirings are not particularly limited and can be appropriately selected depending on the purpose as long as the gate voltage and the image data signal can be individually applied to each field effect transistor in the plurality of display elements.

  The display control device is not particularly limited as long as the gate voltage and signal voltage of each field effect transistor can be individually controlled via a plurality of wirings according to image data, and is appropriately selected according to the purpose. can do. There is no restriction | limiting in particular as another member, According to the objective, it can select suitably.

  Since the image display device according to the second embodiment includes the display element including the field effect transistor according to the first embodiment, it is possible to display a high-quality image.

(system)
The system according to the second embodiment includes at least an image display device according to the second embodiment and an image data creation device. The image data creation device creates image data based on the image information to be displayed, and outputs the image data to the image display device.

  Since the system includes the image display device according to the second embodiment, the image information can be displayed with high definition.

  Hereinafter, the display element, the image display apparatus, and the system according to the second embodiment will be specifically described.

  FIG. 4 shows a schematic configuration of a television apparatus 500 as a system according to the second embodiment. In addition, the connection line in FIG. 4 shows the flow of a typical signal and information, and does not show all the connection relations of each block.

  A television apparatus 500 according to the second embodiment includes a main controller 501, a tuner 503, an AD converter (ADC) 504, a demodulation circuit 505, a TS (Transport Stream) decoder 506, an audio decoder 511, and a DA converter (DAC). 512, audio output circuit 513, speaker 514, video decoder 521, video / OSD synthesis circuit 522, video output circuit 523, image display device 524, OSD drawing circuit 525, memory 531, operation device 532, drive interface (drive IF) 541 A hard disk device 542, an optical disk device 543, an IR light receiver 551, a communication control device 552, and the like.

  The main control device 501 controls the entire television device 500 and includes a CPU, a flash ROM, a RAM, and the like. The flash ROM stores a program written in a code readable by the CPU, various data used for processing by the CPU, and the like. The RAM is a working memory.

  The tuner 503 selects a preset channel broadcast from the broadcast waves received by the antenna 610. The ADC 504 converts the output signal (analog information) of the tuner 503 into digital information. The demodulation circuit 505 demodulates the digital information from the ADC 504.

  The TS decoder 506 performs TS decoding on the output signal of the demodulation circuit 505 and separates audio information and video information. The audio decoder 511 decodes the audio information from the TS decoder 506. The DA converter (DAC) 512 converts the output signal of the audio decoder 511 into an analog signal.

  The audio output circuit 513 outputs the output signal of the DA converter (DAC) 512 to the speaker 514. The video decoder 521 decodes the video information from the TS decoder 506. The video / OSD synthesis circuit 522 synthesizes the output signal of the video decoder 521 and the output signal of the OSD drawing circuit 525.

  The video output circuit 523 outputs the output signal of the video / OSD synthesis circuit 522 to the image display device 524. The OSD drawing circuit 525 includes a character generator for displaying characters and figures on the screen of the image display device 524, and a signal including display information in response to an instruction from the operation device 532 or the IR light receiver 551. Generate.

  The memory 531 temporarily stores AV (Audio-Visual) data and the like. The operating device 532 includes an input medium (not shown) such as a control panel, for example, and notifies the main controller 501 of various information input by the user. The drive IF 541 is a bi-directional communication interface, and is compliant with ATAPI (AT Attachment Packet Interface) as an example.

  The hard disk device 542 includes a hard disk and a drive device for driving the hard disk. The drive device records data on the hard disk and reproduces data recorded on the hard disk. The optical disk device 543 records data on an optical disk (for example, DVD) and reproduces data recorded on the optical disk.

  The IR light receiver 551 receives the optical signal from the remote control transmitter 620 and notifies the main controller 501 of it. The communication control device 552 controls communication with the Internet. Various information can be acquired via the Internet.

  As shown in FIG. 5 as an example, the image display device 524 includes a display 700 and a display control device 780. As shown in FIG. 6 as an example, the display 700 includes a display 710 in which a plurality of (here, n × m) display elements 702 are arranged in a matrix.

  In addition, as shown in FIG. 7 as an example, the display 710 includes n scanning lines (X0, X1, X2, X3,..., Xn) arranged at equal intervals along the X-axis direction. -2, Xn-1), m data lines (Y0, Y1, Y2, Y3, ..., Ym-1) arranged at equal intervals along the Y-axis direction, in the Y-axis direction M current supply lines (Y0i, Y1i, Y2i, Y3i,..., Ym-1i) arranged at equal intervals along the line. The display element 702 can be specified by the scan line and the data line.

  As shown in FIG. 8 as an example, each display element 702 includes an organic EL (electroluminescence) element 750 and a drive circuit 720 for causing the organic EL element 750 to emit light. That is, the display 710 is a so-called active matrix type organic EL display. The display 710 is a color-compatible 32-inch display. The size is not limited to this.

  As an example, the organic EL element 750 includes an organic EL thin film layer 740, a cathode 712, and an anode 714, as shown in FIG.

The organic EL element 750 can be disposed beside a field effect transistor, for example. In this case, the organic EL element 750 and the field effect transistor can be formed on the same substrate. However, it is not limited to this, For example, the organic EL element 750 may be arrange | positioned on a field effect transistor. In this case, since the gate electrode needs to be transparent, the gate electrode was added with ITO (Indium Tin Oxide), In ₂ O ₃ , SnO ₂ , ZnO, Ga added ZnO, Al. A transparent oxide having conductivity such as SnO ₂ to which ZnO or Sb is added is used.

In the organic EL element 750, Al is used for the cathode 712. Note that an Mg—Ag alloy, an Al—Li alloy, ITO, or the like may be used. ITO is used for the anode 714. Note that a conductive oxide such as In ₂ O ₃ , SnO ₂ , or ZnO, an Ag—Nd alloy, or the like may be used.

  The organic EL thin film layer 740 includes an electron transport layer 742, a light emitting layer 744, and a hole transport layer 746. A cathode 712 is connected to the electron transport layer 742, and an anode 714 is connected to the hole transport layer 746. When a predetermined voltage is applied between the anode 714 and the cathode 712, the light emitting layer 744 emits light.

  As shown in FIG. 8, the drive circuit 720 includes two field effect transistors 810 and 820 and a capacitor 830. The field effect transistor 810 operates as a switch element. The gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. The drain electrode D is connected to one terminal of the capacitor 830.

  The capacitor 830 is for storing the state of the field effect transistor 810, that is, data. The other terminal of the capacitor 830 is connected to a predetermined current supply line.

  The field effect transistor 820 is for supplying a large current to the organic EL element 750. The gate electrode G is connected to the drain electrode D of the field effect transistor 810. The drain electrode D is connected to the anode 714 of the organic EL element 750, and the source electrode S is connected to a predetermined current supply line.

  Therefore, when the field effect transistor 810 is turned on, the organic EL element 750 is driven by the field effect transistor 820.

  As an example, the display control device 780 includes an image data processing circuit 782, a scanning line driving circuit 784, and a data line driving circuit 786, as shown in FIG.

  The image data processing circuit 782 determines the brightness of the plurality of display elements 702 in the display 710 based on the output signal of the video output circuit 523. The scanning line driving circuit 784 individually applies voltages to the n scanning lines in accordance with an instruction from the image data processing circuit 782. The data line driving circuit 786 individually applies voltages to the m data lines in accordance with an instruction from the image data processing circuit 782.

  As is clear from the above description, in the television apparatus 500 according to the present embodiment, the video decoder 521, the video / OSD synthesis circuit 522, the video output circuit 523, and the OSD drawing circuit 525 constitute an image data creation apparatus. ing.

  In the above description, the light control element is an organic EL element. However, the present invention is not limited to this, and a liquid crystal element, an electrochromic element, an electrophoretic element, or an electrowetting element may be used.

  For example, when the light control element is a liquid crystal element, a liquid crystal display is used as the display 710. In this case, as shown in FIG. 11, the current supply line in the display element 703 is not necessary.

  In this case, as shown in FIG. 12 as an example, the drive circuit 730 is composed of only one field effect transistor 840 similar to the field effect transistor (810, 820) shown in FIG. Can do. In the field effect transistor 840, the gate electrode G is connected to a predetermined scanning line, and the source electrode S is connected to a predetermined data line. The drain electrode D is connected to the pixel electrode of the liquid crystal element 770 and the capacitor 760. Note that reference numerals 762 and 772 in FIG. 12 denote a counter electrode (common electrode) of the capacitor 760 and the liquid crystal element 770, respectively.

  In the above embodiment, the case where the system is a television apparatus has been described. However, the present invention is not limited to this. In short, the image display device 524 may be provided as a device for displaying images and information. For example, a computer system in which a computer (including a personal computer) and an image display device 524 are connected may be used.

  In addition, an image display device 524 is provided as a display means in a portable information device such as a mobile phone, a portable music playback device, a portable video playback device, an electronic BOOK, a PDA (Personal Digital Assistant), or an imaging device such as a still camera or a video camera. Can be used. Further, the image display device 524 can be used as a display unit for various information in a mobile system such as a car, an aircraft, a train, and a ship. Furthermore, the image display device 524 can be used as a display unit for various information in a measurement device, an analysis device, a medical device, and an advertising medium.

[Example 1]
In Example 1, the field effect transistor 10 shown in FIG. 1 was produced.

(Formation of the first gate electrode)
First, the first gate electrode 12 was formed on the substrate 11. Specifically, an Al alloy film as a conductive film was formed on a glass substrate 11 by DC sputtering. Then, the Al alloy film was patterned by photolithography and etching to obtain the first gate electrode 12.

(Formation of first gate insulating layer)
Next, the first gate insulating layer 13 was formed. Specifically, a predetermined solution was mixed to prepare a coating solution for forming a gate insulating layer, which was dropped onto the substrate 11 and the first gate electrode 12 and spin-coated. Subsequently, after drying in the air, firing was performed in an O ₂ atmosphere to obtain a LaSrO insulating film as the first gate insulating layer 13.

(Formation of active layer)
Next, the active layer 14 was formed. Specifically, a coating solution for forming an active layer was prepared by mixing a predetermined solution, dropped onto the first gate insulating layer 13 and spin-coated. Subsequently, after drying in the air, firing was performed in an O ₂ atmosphere to form an InGaZnO film. Then, the InGaZnO film was patterned by photolithography and etching to obtain an active layer 14.

(Formation of second gate insulating layer)
Next, the second gate insulating layer 15 was formed. Specifically, a coating solution for forming a gate insulating layer was prepared by mixing a predetermined solution, and dropped onto the first gate insulating layer 13 and the active layer 14 and spin-coated. Subsequently, after drying in the air, firing was performed in an O ₂ atmosphere to obtain a LaSrO insulating film as the second gate insulating layer 15.

(Formation of second gate electrode)
Next, the second gate electrode 16 was formed on the second gate insulating layer 15. Specifically, an Al alloy film as a conductive film was formed on the second gate insulating layer 15 by DC sputtering. Then, the Al alloy film was patterned by photolithography and etching to obtain the second gate electrode 16.

(Formation of source electrode and drain electrode)
Next, the source electrode 17 and the drain electrode 18 were formed on the second gate insulating layer 15. Specifically, after forming a through hole that penetrates the second gate insulating layer 15 and exposes the surface of the active layer 14, a Ti film that is a conductive film is formed in the through hole and on the second gate insulating layer by DC sputtering. Was deposited. Then, the Ti film was patterned by photolithography and etching to obtain the source electrode 17 and the drain electrode 18.

[Example 2]
In Example 2, the field effect transistor 10A shown in FIG. 3 was produced.

  First, the first gate electrode 12, the first gate insulating layer 13, the active layer 14, the second gate insulating layer 15, and the second gate electrode 16 were formed on the base material 11 in the same manner as in Example 1. .

(Formation of interlayer insulation film)
Next, an interlayer insulating film 19 was formed. Specifically, a 200 nm thick SiO ₂ insulating film was formed as the interlayer insulating film 19 on the second gate insulating layer 15 and the second gate electrode 16 by plasma CVD.

(Formation of source electrode and drain electrode)
Next, the source electrode 17 and the drain electrode 18 were formed on the interlayer insulating film 19. Specifically, after forming a through hole that penetrates the second gate insulating layer 15 and the interlayer insulating film 19 and exposes the surface of the active layer 14, a conductive film is formed in the through hole and on the interlayer insulating film 19 by DC sputtering. A Ti film was formed. Then, the Ti film was patterned by photolithography and etching to obtain the source electrode 17 and the drain electrode 18.

[Examples 3 to 8]
From Example 1, the composition of the first gate insulating layer 13, the active layer 14, and the second gate insulating layer 15 is changed to the composition shown in Table 1, and the field effect type shown in FIG. A transistor 10 was manufactured.

[Comparative example]
As the first gate insulating layer 13 and the second gate insulating layer 15, SiO ₂ insulating films were formed by plasma CVD. Except for this, a field effect transistor was fabricated in exactly the same process as in Example 1.

[Evaluation]
Regarding the field effect transistors of Examples 1 to 8 and Comparative Example, the presence / absence of pinholes in the first gate insulating layer 13 and the second gate insulating layer 15 was confirmed, and the results are shown in Table 1. The presence / absence of a pinhole was confirmed by an atomic force microscope (AFM).

表１に示すように、第１ゲート絶縁層１３及び第２ゲート絶縁層１５としてＳｉＯ_２絶縁膜を用いた場合（比較例）には、第１ゲート絶縁層１３及び第２ゲート絶縁層１５にピンホールの発生が確認できた。

As shown in Table 1, when a SiO ₂ insulating film is used as the first gate insulating layer 13 and the second gate insulating layer 15 (comparative example), the first gate insulating layer 13 and the second gate insulating layer 15 The occurrence of pinholes was confirmed.

  On the other hand, as the first gate insulating layer 13 and the second gate insulating layer 15, an oxide film containing an A element that is an alkaline earth metal and a B element that is at least one of Ga, Sc, Y, and a lanthanoid In the case of using (Examples 1 to 8), generation of pinholes in the first gate insulating layer 13 and the second gate insulating layer 15 could not be confirmed.

  As described above, by using an oxide film including the element A that is an alkaline earth metal and the element B that is at least one of Ga, Sc, Y, and a lanthanoid, pinholes are less likely to occur. It was confirmed that the first gate insulating layer 13 and the second gate insulating layer 15 can be formed. Thereby, it is possible to realize a field effect transistor in which fluctuation of the threshold voltage is suppressed.

  The preferred embodiments and the like have been described in detail above, but the present invention is not limited to the above-described embodiments and the like, and various modifications can be made to the above-described embodiments and the like without departing from the scope described in the claims. Variations and substitutions can be added.

DESCRIPTION OF SYMBOLS 10, 10A Field effect transistor 11 Base material 12 1st gate electrode 13 1st gate insulating layer 14 Active layer 15 2nd gate insulating layer 16 2nd gate electrode 17 Source electrode 18 Drain electrode 19 Interlayer insulating film

JP 2009-176865 A

Claims (7)

A first gate electrode formed on the substrate;
A first gate insulating layer formed on the first gate electrode;
An active layer formed on the first gate insulating layer;
A second gate insulating layer formed on the active layer;
A second gate electrode formed on the second gate insulating layer;
A source and drain electrode formed to connect to the active layer,
The first gate insulating layer and the second gate insulating layer each include an oxide film including an element A that is an alkaline earth metal and a element B that is at least one of Ga, Sc, Y, and a lanthanoid. A field effect transistor.   The field effect transistor according to claim 1, wherein the active layer is an oxide semiconductor. A light control element whose light output is controlled according to a drive signal;
A display element comprising: the field effect transistor according to claim 1; and a drive circuit that drives the light control element.   The display element according to claim 3, wherein the light control element is an electroluminescence element, an electrochromic element, a liquid crystal element, an electrophoretic element, or an electrowetting element. A display device in which a plurality of display elements according to claim 3 or 4 are arranged in a matrix,
A display control device for individually controlling each of the display elements. A display device according to claim 5;
An image data creation device for supplying image data to the display device. Forming a first gate electrode on a substrate;
Forming a first gate insulating layer on the first gate electrode;
Forming an active layer on the first gate insulating layer;
Forming a second gate insulating layer on the active layer;
Forming a second gate electrode on the second gate insulating layer;
Forming source and drain electrodes connected to the active layer,
The first gate insulating layer and the second gate insulating layer each include an oxide film including an element A that is an alkaline earth metal and a element B that is at least one of Ga, Sc, Y, and a lanthanoid. A method of manufacturing a field effect transistor.

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