JP6836271B2 - Semiconductor devices and their control methods - Google Patents

Description

The present invention relates to a semiconductor device including, for example, a protected semiconductor integrated circuit (hereinafter, the semiconductor integrated circuit is referred to as an IC and the protected semiconductor integrated circuit is referred to as a protected IC) and a control method thereof.

As an IC for protecting a secondary battery, a protection IC of a type that detects an overvoltage or an overcurrent of the battery and turns off the field effect transistor of the charge / discharge path is known (see, for example, Patent Document 1). In this type of protection IC, if the overvoltage or overcurrent state is resolved, the field effect transistor can be turned on and used again. On the other hand, there is a type of protection IC that blows the fuse in the charge / discharge path to cut the charge / discharge path. In this case, it is already known that the fuse is blown and becomes unusable.

However, in the conventional protection ICs, the terminals of a plurality of secondary batteries connected in series in advance are connected to each connection terminal of the board on which the IC is mounted, one by one, for example, by soldering with a wire or the like. In the case of wire, if a specific connection terminal is opened in the middle of the connection work, there is a possibility that an overvoltage or the like may be erroneously detected or a voltage exceeding the withstand voltage of the IC may be applied.

Here, the type of protection IC that controls the field effect transistor by the detection signal of the protection IC does not cause a big problem if only erroneous detection is performed, but the type of protection IC that blows the fuse cannot be used once it is detected. It will be in a state. In order to prevent this, it is necessary to limit the connection order of each secondary battery to each connection terminal of the IC, and there is a problem that the efficiency of the assembly work is poor.

An object of the present invention is to solve the above problems and to provide a semiconductor device capable of preventing erroneous detection of a protective IC when a secondary battery is connected to each connection terminal of a substrate on which a protective IC is mounted. There is.

The semiconductor device according to one aspect of the present invention is
A semiconductor device that protects a plurality of batteries connected in series with each other, and is one of a positive electrode detection terminal, at least one intermediate detection terminal, and a negative electrode detection terminal when the plurality of batteries are connected. A semiconductor device that outputs a first detection signal when any of the voltages between detection terminals adjacent to each other or each corresponding voltage corresponding to each voltage exceeds a predetermined threshold voltage. There,
A control circuit that detects each current flowing through the detection terminal of the positive electrode and the at least one intermediate detection terminal and controls the currents so that they are substantially the same as each other.
A rectifying element connected so that a current flows from the detection terminal of the negative electrode toward an intermediate detection terminal adjacent to the detection terminal of the negative electrode.
The voltage of the intermediate detection terminal having a ground terminal connected to the reference potential of the semiconductor substrate and adjacent to the detection terminal of the negative electrode is compared with the voltage of the detection terminal of the negative electrode, and the detection terminal of the negative electrode is described as described above. A comparison circuit that outputs a second detection signal when it detects that the battery is not connected,
It is characterized by including an output circuit for stopping the output of the first detection signal based on the second detection signal.

According to the semiconductor device according to the present invention, when the secondary battery is connected to each connection terminal of the substrate on which the protection IC is mounted, erroneous detection of the protection IC can be prevented.

It is a circuit diagram which shows the protection IC 30 and its peripheral circuit which concerns on a comparative example. It is a circuit diagram which shows the detailed structure of the overvoltage detection circuit 31-34 of FIG. It is a circuit diagram which shows the structural example of the protection IC 30A which concerns on Embodiment 1 of this invention. It is a circuit diagram which shows the structural example of the level shift circuit 36-38 of FIG. It is a circuit diagram which shows the structural example of the protection IC30B which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the structural example of the protection IC30C which concerns on Embodiment 3 of this invention. It is a circuit diagram which shows the structural example of the protection IC30D which concerns on Embodiment 4 of this invention. FIG. 5 is a schematic block diagram for explaining an operation when the detection terminal D2 is open in the protection IC 30 according to the comparative example. FIG. 5 is a schematic block diagram for explaining the possibility that the voltage Va between the detection terminals D1 and D2 in the protection IC 30A of FIG. 3 is higher than half the value of the total voltage Vt of the batteries B1 and B2.

Hereinafter, comparative examples and each embodiment according to the present invention will be described. In the drawings, the same reference numerals are given to the same ones, and detailed description thereof will be omitted.

Comparative example.
FIG. 1 is a circuit diagram showing a protection IC 30 and its peripheral circuits according to a comparative example. In FIG. 1, the protection IC 30 is a semiconductor device for detecting overvoltages of a plurality of secondary batteries B1 to B4, which are lithium batteries, for example, and protects the secondary batteries B1 to B4, and detects four overvoltages. A circuit 31 to 34 and an or gate 35 are provided. Here, the protection IC 30 has detection terminals D1 to D5, a signal output terminal Q1, and a power supply terminal VCS.

In FIG. 1, each terminal of a plurality of secondary batteries B1 to B4 connected in series in advance is connected to connection terminals T11 to T15 by soldering or the like using, for example, a wire. The connection terminal T11 is connected to the power supply terminal VCS via the resistor 10 and is connected to the detection terminal D1 via the resistor 11. Further, the connection terminal T11 is connected to the output terminal T1 via the fuses F1 and F2 of the fuse circuit 15. The fuse circuit 15 is configured to include two fuses F1 and F2 and a resistor 16, and the connection point of the fuses F1 and F2 is an output terminal via the resistor 16 via the drain and source of the MOS transistor 17 described later. Connected to T2. Further, the connection terminal T12 is connected to the detection terminal D2 via the resistor 12. A capacitor 21 is connected between the detection terminals D1 and D2. Further, the connection terminal T13 is connected to the detection terminal D3 via the resistor 13. A capacitor 22 is connected between the detection terminals D2 and D3. Furthermore, it is connected to the detection terminal D4 via the connection terminal T14 resistor 14. A capacitor 23 is connected between the detection terminals D3 and D4. The connection terminal T15 is connected to the detection terminal D5 and also to the output terminal T2. A capacitor 24 is connected between the detection terminals D4 and D5. Further, the capacitor 20 is connected between the power supply terminal VCS and the detection terminal D5.

The five detection terminals D1 to D5 in the battery group when the four secondary batteries B1 to B4 are connected can be classified as follows.
(1) Positive electrode detection terminal D1;
(2) Intermediate detection terminals D2 to D4;
(3) Negative electrode detection terminal D5.

Each of the overvoltage detection circuits 31 to 34 has a power supply terminal VCC1, a ground terminal GND1, and a signal output terminal Q11, respectively. In each overvoltage detection circuit 31 to 34, the voltage divided by the voltage divider circuit composed of resistors 71 and 72 is the potential of the ground terminal GND1 of each overvoltage detection circuit 31 to 34. When the voltage becomes equal to or higher than the predetermined reference voltage Vref, an H level detection signal is output from the signal output terminal Q11 to the signal output terminal Q1 via the ore gate 35. The detection signal is applied to the gate of the MOS transistor 17. On the other hand, each overvoltage detection circuit 31 to 34 outputs an L level detection signal when the divided voltage becomes less than a predetermined reference voltage Vref with reference to the potential of the ground terminal GND1 of each overvoltage detection circuit 31 to 34. Output from terminal Q11.

In each of the overvoltage detection circuits 31 to 34 according to the present embodiment, the voltage divided by the voltage divider circuit composed of the resistors 71 and 72 is divided into the voltage applied to the power supply terminal VCS1. The potential of the ground terminal GND1 of 34 is used as a reference for comparison with a predetermined reference voltage Vref, but the present invention is not limited to this, and the voltage is not divided and is applied to the voltage applied to the power supply terminal VCS1 (for example,). The corresponding voltage (in proportion, etc.) may be compared with a predetermined threshold voltage determined according to the voltage to be compared, such as the voltage dividing voltage.

FIG. 2 is a circuit diagram showing a detailed configuration of the overvoltage detection circuits 31 to 34 of FIG. In FIG. 2, the overvoltage detection circuits 31 to 34 are configured to include two resistors 71 and 72, a reference voltage generation circuit 73, and a comparator 74 which is a comparison circuit.

In the overvoltage detection circuits 31 to 34 of FIG. 2, the voltage applied to the power supply terminals VCS1 is divided by the voltage divider circuits of the resistors 71 and 72, and the voltage divider voltage is applied to the non-inverting input terminal of the comparator 74. To. The power supply voltage applied between the power supply terminal VCC1 and the ground terminal GND1 is input to the comparator 74 and the reference voltage generation circuit 73. The reference voltage generation circuit 73 generates a predetermined reference voltage Vref for determining the overvoltage of the protection IC 30 based on the power supply voltage, and outputs the voltage to the inverting input terminal of the comparator 74. The comparator 74 has an L level when the divided voltage obtained by dividing the voltage applied to the power supply terminal VCS1 is less than the reference voltage Vref with reference to the potential of the ground terminal GND1 of each overvoltage detection circuit 31 to 34. While the detection signal is output via the signal output terminal Q11, the H level detection signal is output when the voltage dividing voltage is equal to or higher than the reference voltage Vref with reference to the potential of the ground terminal GND1.

In the protection IC 30 and its peripheral circuits configured as described above, the voltage applied to any of the detection terminals D1 to D4 is divided by the voltage divider circuit consisting of resistors 71 and 72. When the voltage becomes equal to or higher than the reference voltage Vref with reference to each ground terminal GND1, an H level detection signal is output from the signal output terminal Q1 to the gate of the MOS transistor 17. At this time, the MOS transistor 17 is turned on, and a predetermined current is passed through the fuses F1 and F2 to blow the fuses, so that charging and discharging of the secondary batteries B1 to B4 are stopped, and the secondary batteries B1 to B4 are in danger of ignition. Prevents the situation.

FIG. 8 is a schematic block diagram for explaining the operation when the detection terminal D2 is open in the protection IC 30 according to the comparative example.

As shown in FIG. 8, when the detection terminal D2 of the protection IC 30 is open, the total voltage of the secondary batteries B1 and B2 is applied to both ends of the overvoltage detection circuits 31 and 32 to the impedances of the overvoltage detection circuits 31 and 32. The voltage divided by is applied. If the impedances are the same as each other, the impedances are evenly divided with respect to the overvoltage detection circuits 31 and 32, but the impedances are not always the same due to manufacturing variations and the like. For example, when the impedance of the overvoltage detection circuit 31 is 1 MΩ and the impedance of the overvoltage detection circuit 32 is 3 MΩ, a voltage of 6 V is applied to the overvoltage detection circuit 32. In this case, when the overvoltage detection circuit 32 exceeds the reference voltage Vref, the overvoltage detection state is entered, an H level detection signal is applied to the gate of the MOS transistor 17, and the fuses F1 and F2 can be erroneously detected. There is sex.

In order to solve this problem, the inventors have invented the following embodiments.

Embodiment 1.
FIG. 3 is a circuit diagram showing a configuration example of the protection IC 30A according to the first embodiment of the present invention. In FIG. 3, the protection IC 30A according to the first embodiment has a level shift circuit 36 to 38, a logic circuit 41, a latch circuit 42, and a current detection circuit A1 to a comparison with the protection IC 30 according to the comparative example of FIG. Further equipped with A4. The protection IC 30A further includes variable resistors 51 to 54, a processor (control circuit) 40, a diode 43, a comparator 44, and an inverter 45 as compared with the protection IC 30. The above differences will be described in detail below.

In FIG. 3, the current detection circuit A1 is inserted between the detection terminal D1 and the power supply terminal VCS1 of the overvoltage detection circuit 31, and the current value DA1 detected by the current detection circuit A1 is output to the processor 40. The current detection circuit A2 is inserted between the detection terminal D2 and the power supply terminal VCS1 of the overvoltage detection circuit 32, and the current value DA2 detected by the current detection circuit A2 is output to the processor 40. The current detection circuit A3 is inserted between the detection terminal D3 and the power supply terminal VCS1 of the overvoltage detection circuit 33, and the current value DA3 detected by the current detection circuit A3 is output to the processor 40. The current detection circuit A4 is inserted between the detection terminal D4 and the power supply terminal VCS1 of the overvoltage detection circuit 34, and the current value DA4 detected by the current detection circuit A4 is output to the processor 40. Here, each of the current detection circuits A1 to A4 has, for example, a minute resistance (a sufficiently small resistance value that does not affect signal detection), detects a voltage across the small resistance, and is induced by the current flowing through the minute resistance. The current is detected by detecting the voltage. As will be described in detail later, each current value DA1 to DA4 may be configured by, for example, a current detection circuit of a tester device outside the protection IC 30A.

The level shift circuit 36 is inserted between the overvoltage detection circuit 31 and the input terminal of the orgate 35, and the level shift circuit 37 is inserted between the overvoltage detection circuit 32 and the input terminal of the orgate 35. A level shift circuit 38 is inserted between the overvoltage detection circuit 33 and the input terminal of the orgate 35.

FIG. 4 is a circuit diagram showing a configuration example of the level shift circuits 36 to 38 of FIG. In FIG. 4, each level shift circuit 36 to 38 has a power supply terminal VCS2, a ground terminal GND2, a detection terminal D12, a ground terminal GND12, and a signal output terminal Q12. Each level shift circuit 36 to 38 is a known level shift circuit including an inverter 60 and four cross-coupled MOS transistors 61 to 64. Each level shift circuit 36 to 38 level shifts the input binary signal, for example, the ground potential of the binary signal input to the detection terminal D12 from the potential of the ground terminal GND12 to the potential of the ground terminal GND2. It is converted into a predetermined binary signal and output from the signal output terminal Q12.

Returning to FIG. 3, the description of the configuration of the protection IC 30A will be continued below. The or gate 35 calculates the logical sum of the four input detection signals, and outputs the calculation result signal to the latch circuit 42 via a logic circuit 41 having a predetermined delay circuit and performing a predetermined logical operation. And latch it. The latch circuit 42 outputs the latched detection signal via the signal output terminal Q1. Here, the logic circuit 41 and the latch circuit 42 are output circuits that output a detection signal.

A variable resistor 51 controllable by the processor 40 is connected between the output terminal of the current detection circuit A1 and the output terminal of the current detection circuit A2, and the output terminal of the current detection circuit A2 and the output terminal of the current detection circuit A3. A variable resistor 52 that can be controlled by the processor 40 is connected between them. A variable resistor 53 controllable by the processor 40 is connected between the output terminal of the current detection circuit A3 and the output terminal of the current detection circuit A4, and between the output terminal of the current detection circuit A4 and the detection terminal D5. , A variable resistor 54 controllable by the processor 40 is connected. Each resistance value of each of the variable resistors 51 to 54 is set to a sufficiently large resistance value that does not affect signal detection.

Further, a diode 43 is connected between the output terminal of the current detection circuit A4 and the detection terminal D5, the output terminal of the current detection circuit A4 is connected to the non-inverting input terminal of the comparator 44, and the detection terminal D5 is compared. It is connected to the inverting input terminal of the device 44. Here, the power supply ground terminal of the comparator 44 is connected to the semiconductor substrate of the protection IC 30A having a predetermined reference potential. Here, when the semiconductor substrate is a P-type substrate, the reference potential is the P-type substrate potential, and when the semiconductor substrate is the N-type substrate, the reference potential is the power supply voltage VCS. FIG. 3 shows the case of the P-type substrate potential, and the case where the P-type substrate potential is used as the reference potential will be described. In the comparator 44, the reference potential of the semiconductor substrate is connected to the positive electrode of the secondary battery B4. It is determined whether or not the potential is equal to or higher than the potential of the detection terminal D4. The comparator 44 generates an H level reset signal when the potential is equal to or higher than the potential of the detection terminal D4, and outputs the H level reset signal to the reset signal input terminal of the latch circuit 42 via the inverter 45.

The operation of the protection IC 30A configured as described above will be described in detail below with reference to the problems of the protection IC 30 according to the comparative example.

First, the problem of the protection IC 30 according to the comparative example will be described. When the detection terminal D5 is in the open state, the substrate potential of the semiconductor substrate of the protection IC 30 is not fixed. In such a case, since the protection IC 30 cannot operate normally, the signal output terminal Q1 of the protection IC 30 may be in the detection state. Therefore, it is necessary to detect that the substrate potential of the protection IC 30 is not connected and prevent malfunction. Further, as described with reference to FIG. 8, even if the substrate potential of the protection IC 30 is fixed, if the detection terminal D2 is in the open state, the signal output terminal Q1 of the protection IC 30 may be in the detection state. is there. Therefore, it is necessary to equalize the current consumption between the detection terminals D1-D2, D2-D3, D3-D4, and D4-D5 connected to the secondary batteries B1 to B4 of the protection IC 30 and to equalize the internal impedance. There is.

FIG. 9 is a schematic block diagram for explaining the possibility that the voltage Va between the detection terminals D1 and D2 is higher than the overall voltage Vt of the batteries B1 and B2 in the protection IC 30A of FIG. In FIG. 9, the current flowing through the overvoltage detection circuit 31 is Ia, the current flowing through the overvoltage detection circuit 32 is Ib, and the current flowing through the level shift circuit 37 is Ic. The impedances of the overvoltage detection circuits 31 and 32 have the same resistance value R, and the voltage applied to the overvoltage detection circuit 31 is Va, and the voltage applied to the overvoltage detection circuit 32 is Vb. Further, the total voltage of the secondary batteries B1 and B2 is defined as Vt. At this time, it is expressed by the following equation.

Ia = Ib + Ic
Ia = Va / R
Ib = Vb / R
Vt = Va + Vb

Therefore, the following equation is obtained.

Va / R = Vb / R + Ic
Va = Vb + R × Ic
Va = Vt-Vb
Vt-Vb = Vb + R × Ic
2Vb = Vt-R × Ic

Therefore, the voltages Va and Vb are expressed by the following equations.

Vb = Vt / 2-R × Ic / 2
Va = Vt / 2 + R × Ic / 2

As a result, the voltage Va becomes larger than the voltage Vt / 2. Here, even if the impedances of the overvoltage detection circuits 31 and 32 are the same, if the level shift circuit 37 passes a current Ic, the voltages of the secondary batteries B1 to B4 may not be evenly divided, resulting in an overvoltage detection state. is there.

That is, when any one or more of the detection terminals D1 to D4 are not connected, the voltage of the detection terminals D1 to D4 of the protection IC 30A is the sum of the plurality of battery voltages and the internal impedance of the protection IC 30A. It becomes the value divided by. When this internal impedance is non-uniform, even if each battery voltage is equal to or less than the specified voltage specified by the protection IC 30A, it is determined that the voltage between the detection terminals of the protection IC 30A exceeds the specified voltage, and the output terminal is used. There is a possibility that the detection signal will be detected from Q1. Therefore, it is necessary to equalize the current consumption between the detection terminals connected to the secondary batteries B1 to B4 of the protection IC 30A and to equalize the internal impedance.

Next, in the protection IC 30A according to the first embodiment, the means for detecting that the reference potential of the semiconductor substrate is not connected will be described in detail below.

If all the detection terminals D1 to D5 are connected, the current consumption flowing through the protection IC 30A flows out to the negative electrode of the secondary battery B4 through the detection terminals D5 (arrow 101). Here, if the detection terminal D5 is not connected, it flows out to the negative electrode of the secondary battery B3 via the diode 43 in the protection IC 30A and the detection terminal D4 (arrow 102). At this time, the substrate potential of the semiconductor substrate of the protection IC 30A rises to the extent that the diode 43 can be turned on. That is, when all the detection terminals D1 to D5 are connected, for example, the substrate potential, which is the P-type substrate potential, is the voltage of the secondary battery B4 rather than the detection terminal D4 connected to the positive electrode of the secondary battery B4. It is lower by the amount. However, when the detection terminal D5 is not connected, the substrate potential is higher than the detection terminal D4 connected to the positive electrode of the secondary battery B4. Therefore, it is possible to determine whether or not the detection terminal D5 is connected by determining whether or not the substrate potential is equal to or higher than the detection terminal D4 connected to the positive electrode of the secondary battery B4 by the comparator 44. it can. Based on the detection signal of this determination result, when the detection terminal D5 is not connected, the signal output terminal Q1 is fixed to the L level undetected state, so that the H level detection signal from the signal output terminal Q1 can be obtained. It is possible to stop the output and prevent an unintended detection state.

In the configuration example of FIG. 3, when it is detected that the detection terminal D5 is not connected, an H level detection signal is generated from the comparator 44, and an L level reset signal is sent to the latch circuit 42 via the inverter 45. Output. As a result, by fixing the signal output terminal Q1 to the L level undetected state, it is possible to prevent an unintended detection state.

Next, among the means for equalizing the current consumption in the overvoltage detection circuits 31 to 34 in the protection IC 30A according to the first embodiment, an example of the means for correcting the non-uniformity will be described.

In FIG. 3, the current detection circuits A1 to A4 detect each current value DA1 to DA4 flowing through the detection terminals D1 to D4 and output the current values to the processor 40, respectively. The processor 40 controls the current values DA1 to DA4 so as to be substantially the same as each other by adjusting the resistance values of the variable resistors 51 to 54 based on the detected current values DA1 to DA4. ..

Instead of controlling each current value DA1 to DA4 using the processor 40, an ammeter measures each current value DA1 to DA4 flowing through the detection terminals D1 to D4 by a tester device during the test of the manufacturing process of the protection IC 30A. Measure with. Then, the tester device may adjust the resistance values of the variable resistors 51 to 54 so that the current values DA1 to DA4 are substantially the same as each other. At this time, each variable resistor 51 to 54 is a variable resistor formed by connecting, for example, a plurality of resistors in series and a fuse capable of cutting in parallel to each resistor, and constitutes a variable resistor capable of trimming. , The resistance value may be a fixed value after manufacturing.

Further, among the means for equalizing the current consumption in the protection IC 30A of FIG. 3, an example of a means for eliminating non-uniformity will be described.

In the protection IC 30A, the overvoltage detection circuits 31 to 34 exist, and the detection signal from the overvoltage detection circuits 31 to 34 is a binary signal having an H level or an L level, and is referred to the reference potential of the semiconductor substrate of the protection IC 30A. Not. Therefore, the present embodiment is characterized in that the level shift circuits 36 to 38 are used to convert the detection signal from the overvoltage detection circuits 31 to 33 into the reference potential of the semiconductor substrate. Here, even if the current consumption of the overvoltage detection circuits 31 to 34 is uniform, the presence of a steady current path with respect to the reference potential of the protection IC 30A in the level shift circuits 36 to 38 causes the uniformity to be lost. .. Therefore, in the present embodiment, the level shift circuits 36 to 38 configured by using the cross-coupled MOS transistors 61 to 64 shown in FIG. 4 are used, and a configuration without a steady current path with respect to the reference potential is adopted. .. As a result, the current consumption between the detection terminals D1-D2, D2-D3, D3-D4, and D4-D5 of the overvoltage detection circuits 31 to 34 can be made uniform.

As described above, the present embodiment has the following unique effects.
(1) By using the comparator 44, it is possible to prevent the above-mentioned erroneous detection of overvoltage when the secondary battery D4 is not connected to the detection terminal D5 in the open state (floating state). In the configuration example of FIG. 3, by resetting the latch circuit 42 that latches the detection signal, the signal output terminal Q1 is fixed to the undetected state of the L level, and an unintended detection state can be prevented.
(2) By using the current detection circuits A1 to A4, the variable resistors 51 to 54, and the processor 40, the current between the adjacent detection terminals D1 to D5 can be substantially made uniform.
(3) According to the above (1) and (2), the secondary batteries B1 to B4 can be freely connected even if the connection order is not a predetermined limited order. As a result, the assembly work of the semiconductor device can be facilitated as compared with the conventional technique.

Embodiment 2.
FIG. 5 is a circuit diagram showing a configuration example of the protection IC 30B according to the second embodiment of the present invention. In FIG. 5, the protection IC 30B according to the second embodiment differs from the protection IC 30A in FIG. 3 in the following points. Other configurations are the same as those in the first embodiment.
(1) The power supply terminal of the logic circuit 41 is connected to the power supply voltage VCS via the switch SW1.
(2) The power supply terminal of the latch circuit 42 is connected to the power supply voltage VCS via the switch SW2.
(3) When it is determined that the detection terminal D5 is in the open state without the inverter 45, the switches SW1 and SW2 are switched from on to off based on the H level reset signal from the comparator 44. That is, when the comparator 44 detects the open state of the detection terminal D5, the power supply to the logic circuit 41 and the latch circuit 42 is cut off, and the detection signals from the logic circuit 41 and the latch circuit 42 are not detected. It is fixed to a certain L level detection signal.

According to the protection IC 30B according to the second embodiment configured as described above, when the open state of the detection terminal D5 is detected, the power supply to the logic circuit 41 and the latch circuit 42 is cut off. As a result, the output signals from the logic circuit 41 and the latch circuit 42 are fixed to the L level detection signals that are in the undetected state. As a result, even if the detection terminal D5 is in the floating state, the erroneous detection state can be prevented. Other effects are the same as in the first embodiment.

Embodiment 3.
FIG. 6 is a circuit diagram showing a configuration example of the protection IC 30C according to the third embodiment of the present invention. In FIG. 6, the protection IC 30C according to the third embodiment differs from the protection IC 30A in FIG. 3 in the following points. Other configurations are the same as those in the first embodiment.
(1) The latch circuit 42 is not provided, and the and gate 46 is further provided. Here, the output signal from the logic circuit 41 is input to the first input terminal of the and gate 46. Further, the output signal from the comparator 44 is input to the second input terminal of the and gate 46 via the inverter 45. Here, the and gate 46 calculates the logical product of the two input signals, and outputs the calculation result signal from the signal output terminal Q1.
The above differences will be described in detail below.

In FIG. 6, when the open state of the detection terminal D5 is not detected, an H level output signal is input to the and gate 46. Therefore, when the open state of the detection terminal D5 is not detected and the H level detection signal from the logic circuit 41 is output, the detection signal indicating overvoltage detection can be output from the output terminal Q1. Therefore, when the open state of the detection terminal D5 is not detected, it is possible to prevent the output terminal Q1 from outputting the detection signal indicating the overvoltage detection.

According to the protection IC 30C according to the third embodiment configured as described above, when the open state of the detection terminal D5 is not detected, it is possible to prevent the detection signal indicating overvoltage detection from being output from the output terminal Q1. Other effects are the same as in the first embodiment.

Embodiment 4.
FIG. 7 is a circuit diagram showing a configuration example of the protection IC 30D according to the fourth embodiment of the present invention. In FIG. 7, the protection IC 30D according to the fourth embodiment differs from the protection IC 30A in FIG. 3 in the following points. Other configurations are the same as those in the first embodiment.
(1) Instead of the inverter 45, an internal voltage source control circuit 47 and an internal voltage source 48 are further provided.
(2) The logic circuit 41 and the latch circuit 42 operate based on a predetermined internal power supply voltage Vint from the internal voltage source 48.
The above differences will be described in detail below.

In FIG. 7, the internal voltage source control circuit 47 operates the internal voltage source 48 based on the L level detection signal from the comparator 44 to generate the internal power supply voltage Vint, and causes the logic circuit 41 and the latch circuit 42 to generate the internal power supply voltage Vint. Supply. On the other hand, the internal voltage source control circuit 47 does not operate the internal voltage source 48 based on the H level detection signal from the comparator 44, and does not generate the internal power supply voltage Vint. At this time, the logic circuit 41 and the latch circuit 42 do not operate.

According to the protection IC 30D according to the fourth embodiment configured as described above, when the open state of the detection terminal D5 is detected, the power supply to the logic circuit 41 and the latch circuit 42 is cut off. As a result, the detection signals from the logic circuit 41 and the latch circuit 42 are fixed to the L-level detection signals that are in the undetected state. As a result, even if the detection terminal D5 is in the floating state, the erroneous detection state can be prevented. Other effects are the same as in the first embodiment.

Modification example.
In each of the above embodiments, four secondary batteries B1 to B4 are used, but the present invention is not limited to this, and the number of secondary batteries may be two or more.

In each of the above embodiments, the secondary batteries B1 to B4 are used, but the present invention is not limited to this, and can be applied to an IC that protects other types of batteries such as a primary battery.

Although the diode 43 is used in each of the above embodiments, the present invention is not limited to this, and any rectifying element that allows a current to flow in one direction may be used.

Although the protection ICs 30A to 30D are disclosed in each of the above embodiments, the present invention is not limited to this, and may be configured as a control method for controlling the protection ICs 30A to 30D.

Differences between the present embodiment and Patent Document 1 Patent Document 1 discloses a configuration in which a clamp circuit is inserted for the purpose of preventing breakage at the time of disconnection. Certainly, it is similar in that it prevents a specific matter when the terminal is open (disconnection), but the problems that false detection occurs in the protection IC and the connection order is limited have not been solved.

In the present embodiment, even if all the detection terminals D1 to D4 are not connected, the current consumption of the detection terminals D1 to D4 can be equalized between the adjacent terminals in the protection ICs 30A to 30D. Make sure that the pressure state does not collapse. Further, it detects that the detection terminal D5 is not connected and fixes it in the undetected state. This prevents erroneous detection of the protection ICs 30A to 30D. Conventionally, the customer has been requested to connect the secondary batteries B1 to B4 from the connection terminals T15, but the connection terminals T11 to T15 can be connected substantially at the same time. Further, even if the connection order of the connection terminals T11 to T15 is random, it is possible to prevent the protection ICs 30A to 30D from erroneously detecting. Further, since the fuses F1 and F2 are not blown by not erroneously detecting, the yield of the substrate on which the protection ICs 30A to 30D is mounted does not decrease as compared with the prior art.

10-14 ... Resistance,
15 ... Fuse circuit,
16 ... resistance,
17 ... MOS transistor,
20-24 ... Capacitors,
30, 30A, 30B, 30C ... Protective IC,
31-34 ... Overvoltage detection circuit,
35 ... Orgate,
36-38 ... Level shift circuit,
39 ... Orgate,
40 ... Processor (control circuit),
41 ... Logic circuit,
42 ... Latch circuit,
43 ... diode,
44 ... Comparator,
45 ... Inverter,
46 ... And Gate,
47 ... Internal voltage source control circuit,
48 ... Internal voltage source,
51-54 ... Variable resistor,
60 ... Inverter,
61-64 ... MOS transistor,
71, 72 ... Resistance,
73 ... Reference voltage generation circuit,
74 ... Comparator,
A1 to A4 ... Current detection circuit,
B1 to B4 ... Secondary battery,
D1 to D5, D12 ... Detection terminal,
F1, F2 ... Fuse,
Q1, Q11, Q12 ... Signal output terminal,
SW1, SW2 ... Switch,
T1, T2 ... Power output terminal,
T11 to T15 ... Connection terminal,
VCS1, VCC2 ... Power supply terminal,
GND1, GND2 ... Ground terminal.

JP-A-2007-218688

Claims (10)

A semiconductor device that protects a plurality of batteries connected in series with each other, and is one of a positive electrode detection terminal, at least one intermediate detection terminal, and a negative electrode detection terminal when the plurality of batteries are connected. A semiconductor device that outputs a first detection signal when any of the voltages between detection terminals adjacent to each other or each corresponding voltage corresponding to each voltage exceeds a predetermined threshold voltage. There,
A control circuit that detects each current flowing through the detection terminal of the positive electrode and the at least one intermediate detection terminal and controls the currents so that they are substantially the same as each other.
A rectifying element connected so that a current flows from the detection terminal of the negative electrode toward an intermediate detection terminal adjacent to the detection terminal of the negative electrode.
The voltage of the intermediate detection terminal having a ground terminal connected to the reference potential of the semiconductor substrate and adjacent to the detection terminal of the negative electrode is compared with the voltage of the detection terminal of the negative electrode, and the detection terminal of the negative electrode is described as described above. A comparison circuit that outputs a second detection signal when it detects that the battery is not connected,
A semiconductor device including an output circuit for stopping the output of the first detection signal based on the second detection signal. The output circuit includes a latch circuit that latches the first detection signal, and resets the latch circuit based on the second detection signal to stop outputting the first detection signal. The semiconductor device according to claim 1. The claim is characterized in that the output circuit stops outputting the first detection signal by cutting off the power supply voltage supplied to the output circuit based on the second detection signal. 1. The semiconductor device according to 1. It further comprises an internal voltage source that generates an internal supply voltage for the output circuit when it does not detect the second detection signal.
1. The first aspect of the present invention is characterized in that the internal voltage source stops outputting the first detection signal by not generating an internal power supply voltage for the output circuit based on the second detection signal. The semiconductor device described. It is characterized by further including an arithmetic element that calculates the logical product of the first detection signal and the inverted signal of the second detection signal and outputs the calculation result signal as the first detection signal. The semiconductor device according to claim 1. A semiconductor device that protects a plurality of batteries connected in series with each other, and is one of a positive electrode detection terminal, at least one intermediate detection terminal, and a negative electrode detection terminal when the plurality of batteries are connected. A semiconductor device that outputs a first detection signal when either the voltage between the detection terminals adjacent to each other or the corresponding voltage corresponding to each voltage exceeds a predetermined threshold voltage. It ’s a control method,
The semiconductor device includes a rectifying element connected so that a current flows from the detection terminal of the negative electrode toward an intermediate detection terminal adjacent to the detection terminal of the negative electrode.
The control method is
A step of detecting each current flowing through the detection terminal of the positive electrode and the at least one intermediate detection terminal and controlling the currents so as to be substantially the same as each other.
The voltage of the intermediate detection terminal having a ground terminal connected to the reference potential of the semiconductor substrate and adjacent to the detection terminal of the negative electrode is compared with the voltage of the detection terminal of the negative electrode, and the detection terminal of the negative electrode has the said A step to output a second detection signal when it is detected that the battery is not connected,
A method for controlling a semiconductor device, wherein the output circuit includes a step of stopping the output of the first detection signal based on the second detection signal. The output circuit includes a latch circuit that latches the first detection signal.
The control method is
The control method for a semiconductor device according to claim 6, further comprising a step of stopping the output of the first detection signal by resetting the latch circuit based on the second detection signal. .. The output circuit further includes a step of stopping the output of the first detection signal by cutting off the power supply voltage supplied to the output circuit based on the second detection signal. 6. The method for controlling a semiconductor device according to claim 6. It further comprises an internal voltage source that generates an internal supply voltage for the output circuit when it does not detect the second detection signal.
Based on the second detection signal, the internal voltage source further comprises a step of stopping the output of the first detection signal by not generating an internal power supply voltage for the output circuit. 6. The method for controlling a semiconductor device according to claim 6. The claim further includes a step of calculating the logical product of the first detection signal and the inverted signal of the second detection signal and outputting the calculation result signal as the first detection signal. Item 6. The method for controlling a semiconductor device according to item 6.

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