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CN115616276A - Current-limiting differential pressure detection circuit of power tube - Google Patents

Current-limiting differential pressure detection circuit of power tube Download PDF

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Publication number
CN115616276A
CN115616276A CN202110788886.0A CN202110788886A CN115616276A CN 115616276 A CN115616276 A CN 115616276A CN 202110788886 A CN202110788886 A CN 202110788886A CN 115616276 A CN115616276 A CN 115616276A
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China
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pmos
current
node
fixed offset
offset comparator
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CN202110788886.0A
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Chinese (zh)
Inventor
晋海钦
罗旭程
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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Priority to CN202110788886.0A priority Critical patent/CN115616276A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/10—Measuring sum, difference or ratio
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/04—Voltage dividers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Measuring Fluid Pressure (AREA)

Abstract

The invention discloses a current-limiting differential pressure detection circuit of a power tube, which comprises: a current limiting loop having a first input, a second input, a first output, and a second output; the first input end is connected with the signal output end and is used for accessing detection current; the second input end is used for inputting a reference current; the first output end is connected with a grid electrode of the power tube; a voltage division module that outputs a divided voltage signal based on an input voltage and an output voltage; a differential pressure detection module comprising a stuck out-of-order comparator; the pressure difference detection module is used for outputting a current limiting protection signal based on the voltage division signal and the control signal provided by the second output end. By applying the technical scheme provided by the invention, the current-limiting protection can be realized, and the problems that the power tube has overhigh power and the like due to the change of the voltage difference of the power tube along with the input voltage after the power tube enters the current-limiting state are solved.

Description

Current-limiting differential pressure detection circuit of power tube
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a current-limiting differential pressure detection circuit of a power tube.
Background
With the development of power electronic technology, power tubes are widely used in power circuit structures such as switching power supplies and inverters. In the prior art, the function of bidirectional current limiting is realized by independently designing two current limiters in the forward direction and the reverse direction of the circuit, which undoubtedly increases the cost of the circuit design.
The current limiter in the existing general circuit adopts a power tube, but the overload bearing capacity of the power tube is weaker, if the current limiting is not adjusted in time, when the current limiter works at a large load current, the voltage difference of the source and the drain of the power tube is overlarge, and the power tube is easy to burn out.
Disclosure of Invention
In view of this, the present invention provides a current-limiting differential pressure detection circuit for a power tube, which can implement current-limiting protection and eliminate the problem that the power tube differential pressure varies with the input voltage and has too high power after the power tube enters the current-limiting state.
In order to achieve the above purpose, the invention provides the following technical scheme:
a current-limiting differential pressure detection circuit of a power tube is characterized in that a drain electrode of the power tube is connected with a signal input end, the signal input end is used for being connected with input voltage, a source electrode of the power tube is used for being connected with a signal output end, and the signal output end is used for providing output voltage;
the current-limiting differential pressure detection circuit includes:
a current limiting loop having a first input, a second input, a first output, and a second output; the first input end is connected with the signal output end and is used for accessing detection current; the second input end is used for inputting a reference current; the first output end is connected with the grid electrode of the power tube;
a voltage division module that outputs a divided voltage signal based on the input voltage and the output voltage;
a differential pressure detection module comprising a stuck-at offset comparator; the pressure difference detection module is used for outputting a current limiting protection signal based on the voltage division signal and the control signal provided by the second output end.
Preferably, in the above current-limiting differential pressure detection circuit, the voltage division signal includes: a first divided voltage signal output by a first node and a second divided voltage signal output by a second node;
the voltage division module includes: two first resistors, one of said first resistors being connected between said signal output terminal and said first node, the other of said first resistors being connected between said signal input terminal and said second node; and two second resistors, one of which is connected between the first node and a ground terminal, and the other of which is connected between the second node and the ground terminal.
Preferably, in the above current-limiting differential pressure detection circuit, the differential pressure detection module includes: one said stuck offset comparator;
the negative phase input end of the fixed offset comparator is connected with the first node, the positive phase input end of the fixed offset comparator is connected with the second node, the output end of the fixed offset comparator is used for outputting the current-limiting protection signal, and the enable end of the fixed offset comparator is connected with the second output end; the fixed offset comparator has an offset voltage.
Preferably, in the above current-limiting differential pressure detection circuit, the fixed offset comparator includes: first to sixth PMOS and first to third NMOS;
the source electrodes of the first PMOS to the fourth PMOS are all connected with power supply voltage; the grid electrode of the first PMOS is connected with the enabling end of the fixed offset comparator; the drain electrode of the first PMOS is connected with the input end of the bias current; the grid electrode of the second PMOS to the grid electrode of the fourth PMOS and the drain electrode of the second PMOS are connected with the input end of the bias current; the drain electrode of the fourth PMOS is connected with the output end of the fixed offset comparator; the grid electrode of the fifth PMOS is connected with the negative phase input end of the fixed offset comparator, and the source electrode of the fifth PMOS is connected with the drain electrode of the third PMOS; the grid electrode of the sixth PMOS is connected with the positive phase input end of the fixed offset comparator, and the source electrode of the sixth PMOS is connected with the drain electrode of the third PMOS;
the grid electrode of the first NMOS is connected with the drain electrode of the first PMOS, and is connected with the drain electrode of the fifth PMOS and the grid electrode of the second NMOS; the drain electrode of the second NMOS is connected with the drain electrode of the sixth PMOS and is connected with the grid electrode of the third NMOS; the drain electrode of the third NMOS is connected with the output end of the fixed offset comparator; the sources of the first NMOS to the third NMOS are all grounded.
Preferably, in the current-limiting differential pressure detection circuit, the fifth PMOS and the sixth PMOS have different sizes;
the first NMOS and the second NMOS have the same size.
Preferably, in the above current-limiting differential pressure detection circuit, the voltage division signal includes: a first divided voltage signal output by the first node; a second voltage division signal output by a second node; a third voltage division signal output by the third node; a fourth voltage division signal output by the fourth node;
the voltage division module includes: two first resistors, one of said first resistors being connected between said signal output terminal and said first node, the other of said first resistors being connected between said signal input terminal and said second node; two second resistors, one of said second resistors being connected between said first node and said third node and the other of said second resistors being connected between said second node and said fourth node; and one of the third resistors is connected between the third node and a ground terminal, and the other third resistor is connected between the fourth node and the ground terminal.
Preferably, in the above current-limiting differential pressure detection circuit, the differential pressure detection module includes: the first fixed offset comparator, the second fixed offset comparator, the first two-input AND gate and the second two-input AND gate;
the negative phase input end of the first fixed offset comparator is connected with the first node, the positive phase input end of the first fixed offset comparator is connected with the second node, and the output end and the second output end of the first fixed offset comparator are respectively connected with the two input ends of the first two-input AND gate;
the negative phase input end of the second fixed offset comparator is connected with the third node, the positive phase input end of the second fixed offset comparator is connected with the fourth node, and the output end and the second output end of the second fixed offset comparator are respectively connected with the two input ends of the second input AND gate;
the output end of the first two-input AND gate outputs a first current-limiting protection signal, and the output end of the second two-input AND gate outputs a second current-limiting protection signal.
Preferably, in the current-limiting differential pressure detection circuit, the first fixed offset comparator and the second fixed offset comparator are the same.
Preferably, in the above current-limiting differential pressure detection circuit, the first fixed offset comparator includes: first to sixth PMOS and first to third NMOS;
the source electrodes of the first PMOS to the fourth PMOS are all connected with power supply voltage; the grid electrode of the first PMOS is connected with the enabling end of the first fixed offset comparator; the drain electrode of the first PMOS is connected with the input end of the bias current; the grid electrode of the second PMOS to the grid electrode of the fourth PMOS and the drain electrode of the second PMOS are connected with the input end of the bias current; the drain electrode of the fourth PMOS is connected with the output end of the first fixed offset comparator; the grid electrode of the fifth PMOS is connected with the negative phase input end of the first fixed offset comparator, and the source electrode of the fifth PMOS is connected with the drain electrode of the third PMOS; the grid electrode of the sixth PMOS is connected with the positive phase input end of the first fixed offset comparator, and the source electrode of the sixth PMOS is connected with the drain electrode of the third PMOS; the enabling end of the first fixed offset comparator inputs a fixed enabling signal;
the grid electrode of the first NMOS is connected with the drain electrode of the first PMOS, and is connected with the drain electrode of the fifth PMOS and the grid electrode of the second NMOS; the drain electrode of the second NMOS is connected with the drain electrode of the sixth PMOS and is connected with the grid electrode of the third NMOS; the drain electrode of the third NMOS is connected with the output end of the first fixed offset comparator; the sources of the first NMOS to the third NMOS are all grounded.
Preferably, in the above current-limiting differential pressure detection circuit, the current-limiting circuit includes:
an operational amplifier, wherein a positive phase input end of the operational amplifier is the first input end, and a negative phase input end of the operational amplifier is the second input end;
the grid electrodes of the first switch tube and the second switch tube are both connected with the output end of the operational amplifier, and the source electrodes of the first switch tube and the second switch tube are both connected with a grounding end; the drain electrode of the first switching tube is the first output end, and the first output end is connected with the driver; the drain electrode of the second switch tube is connected with the power supply voltage through a current source, the drain electrode of the second switch tube is connected with the input end of the phase inverter, and the output end of the phase inverter is the second output end.
Preferably, in the current-limiting differential pressure detection circuit, the first switch tube and the second switch tube are both NMOS.
As can be seen from the above description, in the current-limiting differential voltage detection circuit of a power tube according to the technical solution of the present invention, the differential voltage detection module has a fixed offset comparator, the fixed offset comparator has an offset voltage, and the current-limiting differential voltage threshold of the power tube can be determined jointly by the offset voltage and the resistor ratio. The voltage division module is used for outputting a voltage division signal based on input voltage and output voltage provided by the power tube, and the voltage difference detection module outputs a current-limiting protection signal based on the voltage division signal and a control signal provided by the current-limiting loop. In the scheme of the invention, the current flowing through the power tube can be regulated through the reference current in the current limiting loop, the current limiting threshold value is reduced, or the power tube is closed through the current limiting loop, so that the current limiting protection is realized, the problems of overhigh power and the like caused by the voltage difference detection of the power tube along with the change of the input voltage after the power tube enters the current limiting process are solved, and the function of protecting the power tube is effectively realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a current-limiting protection differential pressure detection circuit of a power transistor;
fig. 2 is a schematic diagram of a current-limiting differential pressure detection circuit of a power transistor according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a fixed offset comparator according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a current-limiting differential pressure detection circuit of another power transistor according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of a current limiting loop according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The existing power tube voltage difference detection mainly divides an input voltage and an output voltage according to different resistance proportions and then compares the divided voltages, and the detected power tube voltage difference is increased along with the increase of the input voltage by the detection circuit. Therefore, when the input voltage is high, the voltage difference detected after the current limiting is performed is also high, so that the power tube has the risks of overhigh power, burning slices and the like. Therefore, when the power tube enters the current-limiting state, a module or a circuit for detecting the fixed differential pressure is needed to detect and judge to send out a current-limiting protection signal.
Referring to fig. 1, fig. 1 is a schematic diagram of a current-limiting protection differential pressure detection circuit of a power tube, as shown IN fig. 1, IN and OUT are a signal input terminal and a signal output terminal of a power tube M1, OC _ LOOP is a current-limiting LOOP of the power tube M1, and a resistor R 1 And R 2 A voltage-dividing resistor and a resistor R for the signal input terminal IN 3 And R 4 The divider resistor is a divider resistor of the signal output terminal OUT, and CMP1 is a zero offset comparator. The offset voltage of the zero offset comparator is 0V, and specifically, when the voltage VP of two input terminals of the zero offset comparator is equal to>And when VN is used, a high level is output, VP is the input voltage of the positive phase input end, and VN is the voltage of the negative phase input end. OCP is the current-limiting protection signal, DIV _ OUT is the voltage-divided signal output from node a, and DIV _ IN is the voltage-divided signal output from node b.
The current limit protection signal OCP is generally a logic signal for protecting the power transistor M1 after the power transistor M1 enters the current limit, and the logic signal may be used to reduce the current limit threshold or perform a power transistor shutdown, etc. If the current-limiting protection signal OCP is not valid, the power tube M1 has already entered the current-limiting state and the voltage difference VDS across the power tube M1 is too large but does not reach the voltage difference detection threshold, and at this time, the power tube M1 may cause chip overheating and other chip burning risks due to too large power.
In the mode shown in FIG. 1, R is a group 2 /(R 1 +R 2 ) And R 3 /(R 3 +R 4 ) DIV _ IN = VIN × R after the divider resistor ratio is determined 2 /(R 1 +R 2 )，DIV_OUT＝VOUT*R 3 /(R 3 +R 4 ) As the input voltage at the signal input terminal IN increases, the voltage difference between the two terminals of the power transistor M1 increases after the current limiting. Under the condition of high input voltage, the power tube M1 cannot send OUT a current-limiting protection signal OCP after entering the current-limiting state but does not reach a differential pressure detection point (namely DIV _ IN and DIV _ OUT positions), and the power tube M1 continuously works and risks of overhigh power/overheating, burning slices and the like exist.
Therefore, in order to solve the above problems, the present invention provides a current-limiting differential voltage detection circuit for a power tube, wherein a drain of the power tube is connected to a signal input terminal, the signal input terminal is used for receiving an input voltage, a source of the power tube is used for connecting to a signal output terminal, and the signal output terminal is used for providing an output voltage;
the current-limiting differential pressure detection circuit includes:
a current limiting loop having a first input, a second input, a first output, and a second output; the first input end is connected with the signal output end and is used for accessing detection current; the second input end is used for inputting a reference current; the first output end is connected with the grid electrode of the power tube;
a voltage division module that outputs a divided voltage signal based on the input voltage and the output voltage;
a differential pressure detection module comprising a stuck-at offset comparator; the voltage difference detection module is used for outputting a current-limiting protection signal based on the voltage division signal and the control signal provided by the second output end.
As can be seen from the above description, in the current-limiting differential pressure detection circuit of a power tube according to the technical solution of the present invention, the differential pressure detection module has a fixed offset comparator, the fixed offset comparator has an offset voltage, and the current-limiting differential pressure threshold of the power tube can be determined jointly by the offset voltage and the resistance ratio. The voltage division module is used for outputting a voltage division signal based on input voltage and output voltage provided by the power tube, and the voltage difference detection module outputs a current-limiting protection signal based on the voltage division signal and a control signal provided by the current-limiting loop. In the scheme of the invention, the current flowing through the power tube can be adjusted through the reference current in the current limiting loop, the current limiting threshold value is reduced, or the power tube is closed through the current limiting loop, so that the current limiting protection is realized, the problems of overhigh power and the like caused by the voltage difference detection of the power tube along with the change of the input voltage after the power tube enters the current limiting state are solved, and the function of protecting the power tube is effectively realized.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 2, fig. 2 is a schematic diagram of a current-limiting differential pressure detection circuit of a power tube according to an embodiment of the present invention. As shown IN fig. 2, the drain of the power transistor M1 is connected to a signal input terminal IN, the signal input terminal IN is used for receiving an input voltage, the source of the power transistor M1 is used for connecting to a signal output terminal OUT, and the signal output terminal OUT is used for providing an output voltage; the substrate of the power tube M1 is connected with the source electrode;
the current-limiting differential pressure detection circuit includes:
a current limit LOOP OC _ LOOP having a first input, a second input, a first output, and a second output; the first input end is connected with the signal output end OUT and is used for accessing a detection current I SENSE (ii) a The second input end is used for inputting a reference current I REF (ii) a The first output end is connected with the grid electrode of the power tube M1;
a voltage dividing module 10, wherein the voltage dividing module 10 outputs a voltage dividing signal based on the input voltage and the output voltage;
a differential pressure detection module 20, the differential pressure detection module 20 comprising a fixed offset comparator CMP; the voltage difference detection module 20 is configured to output a current limiting protection signal OCP based on the voltage division signal and the control signal provided by the second output terminal.
The fixed offset comparator CMP has an offset voltage Vos greater than 0, and outputs a high level when the voltage at the positive phase input terminal of the fixed offset comparator CMP is greater than the sum of the voltage at the negative phase input terminal and the offset voltage Vos, and otherwise outputs a low level.
As shown in fig. 2, the voltage division signal includes: a first divided voltage signal DIV _ OUT output from a first node a and a second divided voltage signal DIV _ IN output from a second node B;
wherein, the voltage division module 10 includes: two first resistors R 1 One said first resistor R 1 Another one of the first resistors R connected between the signal output terminal OUT and the first node A 1 Connected between the signal input terminal IN and the second node B; two second resistors R 2 One said second resistor R 2 Another one of the second resistors R connected between the first node A and ground 2 Is connected between the second node B and the ground terminal. In addition, R is 1 /R 2 Is not equal to R 3 /R 4 ，R 1 And R 2 Sum and R 3 And R 4 The sum may be several hundred K omega.
Wherein the differential pressure detecting module 20 includes: a fixed offset comparator CMP; the negative phase input end of the fixed offset comparator CMP is connected to the first node a, the positive phase input end thereof is connected to the second node B, the output end thereof is used for outputting the current limiting protection signal OCP, and the enable end EN thereof is connected to the second output end.
As shown in fig. 3, fig. 3 is a schematic circuit diagram of a fixed offset comparator according to an embodiment of the present invention, where the fixed offset comparator CMP includes: first to sixth PMOS MP1 to MP6 and first to third NMOS MN1 to MN3.
The sources of the first PMOS MP1 to the fourth PMOS MP4 are all connected with a power supply voltage VDD; the grid electrode of the first PMOS MP1 is connected with an enabling end EN of the fixed offset comparator CMP; the drain electrode of the first PMOS MP1 is connected with the input end of the bias current IBN; the grid electrode of the second PMOS MP2 to the grid electrode of the fourth PMOS MP4 and the drain electrode of the second PMOS MP2 are connected with the input end of the bias current IBN; the drain of the fourth PMOS MP4 is connected to the output OUT of the fixed offset comparator CMP; the grid electrode of the fifth PMOS MP5 is connected with the negative phase input end VN of the fixed offset comparator CMP, and the source electrode of the fifth PMOS MP5 is connected with the drain electrode of the third PMOS MP 3; the gate of the sixth PMOS MP6 is connected to the non-inverting input VP of the fixed offset comparator CMP, and the source thereof is connected to the drain of the third PMOS MP 3.
The grid electrode of the first NMOS MN1 is connected with the drain electrode, and is connected with the drain electrode of the fifth PMOS MP5 and the grid electrode of the second NMOS MN 2; the drain electrode of the second NMOS MN2 is connected with the drain electrode of the sixth PMOS MP6 and is connected with the gate electrode of the third NMOS MN 3; the drain of the third NMOS MN3 is connected to the output OUT of the fixed offset comparator CMP; the sources of the first NMOS MN1 to the third NMOS MN3 are all grounded.
The fifth PMOS MP5 and the sixth PMOS MP6 have different sizes, and the ratio may be 1:2 or other dimension proportion, wherein the dimension is the channel width-length ratio; the first NMOS MN1 and the second NMOS MN2 have the same size, with a ratio of 1:1.
IN the embodiment of the invention, the proportion of the voltage dividing resistance of the signal input end IN and the signal output end OUT is consistent, the offset comparator adopts a fixed offset comparator CMP (the offset voltage Vos of the comparator is a fixed voltage), and the current-limiting differential pressure threshold of the power tube M1 can be jointly determined by the offset voltage Vos of the fixed offset comparator CMP and the proportion of the resistance. DIV _ IN = VIN ═ R 2 /(R 1 +R 2 )，DIV_OUT＝VOUT*R 2 /(R 1 +R 2 ). When the power tube M1 enters the current limiting state, the fixed offset comparator CMP starts to work, and when the voltage difference VDS = VIN-VOUT at the two ends of the power tube M1 is larger than Vos (R) 1 +R 2 )/R 2 The fixed offset comparator CMP sends out a current-limiting protection signal OCP and reduces a current-limiting threshold value or directly closes the power tube M1, so that the problems of overhigh power, overheating and the like of the power tube M1 are avoided, and the effect of protecting the power tube M1 is effectively achieved. VIN is an input voltage of the signal input terminal IN, and VOUT is an output voltage of the signal output terminal OUT.
Referring to fig. 4, fig. 4 is a schematic diagram of a current-limiting differential pressure detection circuit of another power transistor according to an embodiment of the present invention, and as shown in fig. 4, the voltage division signal includes: a first divided voltage signal DIV _ OUT output from the first node a; a second voltage division signal DIV _ IN output from the second node B; a third voltage division signal DIV _ OUT1 output by the third node C; the fourth voltage division signal DIV _ IN1 output from the fourth node D.
Wherein, the voltage dividing module 30 includes: two first resistors R 1 One said first resistor R 1 Another one of the first resistors R connected between the output terminal OUT and the first node A 1 Connected between the input IN and the second node B; two second resistors R 2 One said second resistor R 2 Another one of the second resistors R is connected between the first node A and the third node C 2 Connected between the second node B and the fourth node D; two third resistors R 3 One said third resistor R 3 Another third resistor R connected between the third node C and ground 3 Is connected between the fourth node D and ground.
Wherein the differential pressure detecting module 40 includes: a first fixed offset comparator CMP1, a second fixed offset comparator CMP2, a first two-input and gate 31, and a second two-input and gate 32.
The negative phase input terminal of the first fixed offset comparator CMP1 is connected to the first node a, the positive phase input terminal thereof is connected to the second node B, and the output terminal thereof and the second output terminal thereof are respectively connected to the two input terminals of the first diode and gate 31.
The negative phase input end of the second fixed offset comparator CMP2 is connected to the third node C, the positive phase input end thereof is connected to the fourth node D, and the output end thereof and the second output end thereof are respectively connected to the two input ends of the second input and gate 32; the output end of the first two-input and gate 31 outputs a first current-limiting protection signal OCP1, and the output end of the second two-input and gate 32 outputs a second current-limiting protection signal OCP2.
The first fixed offset comparator CMP1 and the second fixed offset comparator CMP2 are the same, and both structures can be as shown in fig. 3, and both have offset voltage Vos.
As shown in fig. 3, the first fixed offset comparator CMP1 includes: first to sixth PMOS MP1 to MP6 and first to third NMOS MN1 to MN3.
The sources of the first PMOS MP1 to the fourth PMOS MP4 are all connected with a power supply voltage VDD; the grid electrode of the first PMOS MP1 is connected with the enabling end EN of the first fixed offset comparator CMP 1; the drain electrode of the first PMOS MP1 is connected with the input end of the bias current IBN; the grid of the second PMOS MP2 to the grid of the fourth PMOS MP4 and the drain of the second PMOS MP2 are both connected with the input end of the bias current IBN; the drain of the fourth PMOS MP4 is connected to the output OUT of the first fixed offset comparator CMP 1; the grid electrode of the fifth PMOS MP5 is connected with the negative phase input end VN of the first fixed offset comparator CMP1, and the source electrode of the fifth PMOS MP5 is connected with the drain electrode of the third PMOS MP 3; the gate of the sixth PMOS MP6 is connected to the positive phase input VP of the first fixed offset comparator CMP1, and the source thereof is connected to the drain of the third PMOS MP 3; the enable terminal EN of the first fixed offset comparator CMP1 inputs a fixed enable signal.
The grid electrode of the first NMOS MN1 is connected with the drain electrode, and is connected with the drain electrode of the fifth PMOS MP5 and the grid electrode of the second NMOS MN 2; the drain electrode of the second NMOS MN2 is connected with the drain electrode of the sixth PMOS MP6 and is connected with the gate electrode of the third NMOS MN 3; the drain electrode of the third NMOS MN3 is connected with the output end of the first fixed offset comparator CMP 1; the sources of the first NMOS MN1 to the third NMOS MN3 are all grounded.
The sizes of the fifth PMOS MP5 and the sixth PMOS MP6 are different, and the ratio may be 1:2 or other dimensions; the first NMOS MN1 and the second NMOS MN2 have the same size, with a ratio of 1:1.
fig. 4 is an optimized scheme of fig. 2, in which the differential pressure detection module 40 is independent from the current limiting circuit OC _ LOOP, and whether the current limiting protection signal OCP is issued is detected and determined by a two-stage differential pressure detection circuit. Wherein, the threshold voltage of the primary voltage difference detection circuit is Vos (R) 1 +R 2 +R 3 )/(R 2 +R 3 ) The threshold voltage of the two-stage differential pressure detection circuit is Vos (R) 1 +R 2 +R 3 )/R 3 . When the power tube M1 works normally, the pressure difference between two ends of the power tube M1 is detected to be larger than Vos (R) 1 +R 2 +R 3 )/(R 2 +R 3 ) And at this time, in the current limiting state, the first fixed offset comparator CMP1 outputs the first current limiting protection signal OCP1, and reduces the current limiting threshold. When the voltage difference between the two ends of the power tube M1 is detected to be more than Vos (R) 1 +R 2 +R 3 )/R 3 And at this moment, in a current-limiting state, the second fixed offset comparator CMP2 outputs a second current-limiting protection signal OCP2, directly turns off the power tube M1, and effectively plays a role in protecting the power tube M1.
It should be noted that the reference current I can be adjusted REF Adjusting the current between the source and the drain of the power tube M1, and making the current passing through the power tube M1 equal to the reference current I through the current limiting LOOP OC _ LOOP REF . The power tube M1 can be turned off by closing the DRIVER in the current limiting LOOP OC _ LOOP.
Referring to fig. 5, fig. 5 is a schematic circuit diagram of a current limiting LOOP according to an embodiment of the present invention, and as shown in fig. 5, the current limiting LOOP OC _ LOOP includes: an operational amplifier OP, the positive phase input end of which is the first input end and is used for accessing a detection current I SENSE The negative phase input end of the current transformer is the second input end and is used for inputting a reference current I REF (ii) a The grid electrodes of the first switch tube N1 and the second switch tube N2 are both connected with the output end of the operational amplifier OP, and the source electrodes of the first switch tube N1 and the second switch tube N2 are both connected with the grounding end; the drain electrode of the first switching tube N1 is the first output end, and the first output end is connected to the DRIVER; the drain electrode of the second switch tube N2 is connected to a power supply voltage VDD through a current source I, the drain electrode of the second switch tube N2 is connected to the input end of the phase inverter 41, and the output end of the phase inverter 41 is the second output end.
The first switch tube N1 and the second switch tube N2 are both NMOS.
It should be noted that the output terminal of the offset comparator CMP is connected to the current limiting LOOP OC _ LOOP through a logic circuit to connect the DRIVER, so that the DRIVER controls the conducting state of the power transistor M1 based on the output of the offset comparator CMP.
In the embodiment of the invention, when the power tube M1 enters the current-limiting state, the offset comparator CMP starts to work, and when the voltage difference VDS = VIN-VOUT at the two ends of the power tube M1 is greater than Vos (R) 1 +R 2 )/R 2 The maladjustment comparator CMP sends out a current-limiting protection signal OCP and reduces a current-limiting threshold value or directly closes the power tube M1, so that the problems of overhigh power, overheating and the like of the power tube M1 are avoided, and the effect of protecting the power tube M1 is effectively achieved.
The scheme of the invention mainly corresponds to a power tube current-limiting differential pressure detection circuit, and ensures the fixed power tube differential pressure detection threshold value after the power tube enters the current-limiting state on the circuit principle. The chip burning risks such as chip overheating caused by overlarge power of the power tube due to overlarge differential pressure detection threshold under the condition of high input voltage are guaranteed.
As can be seen from the above description, in the current-limiting differential pressure detection circuit of a power tube according to the technical solution of the present invention, the differential pressure detection module has a fixed offset comparator, the fixed offset comparator has an offset voltage, and the current-limiting differential pressure threshold of the power tube can be determined jointly by the offset voltage and the resistance ratio. The voltage division module is used for outputting a voltage division signal based on input voltage and output voltage provided by the power tube, and the voltage difference detection module outputs a current-limiting protection signal based on the voltage division signal and a control signal provided by the current-limiting loop. In the scheme of the invention, the current flowing through the power tube can be regulated through the reference current in the current limiting loop, the current limiting threshold value is reduced, or the power tube is closed through the current limiting loop, so that the current limiting protection is realized, the problems of overhigh power and the like caused by the voltage difference detection of the power tube along with the change of the input voltage after the power tube enters the current limiting process are solved, and the function of protecting the power tube is effectively realized.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one of 8230, and" comprising 8230does not exclude the presence of additional like elements in an article or device comprising the same element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (11)

1. The current-limiting differential pressure detection circuit of the power tube is characterized in that a drain electrode of the power tube is connected with a signal input end, the signal input end is used for being connected with input voltage, a source electrode of the power tube is used for being connected with a signal output end, and the signal output end is used for providing output voltage;
the current-limiting differential pressure detection circuit includes:
a current limiting loop having a first input, a second input, a first output, and a second output; the first input end is connected with the signal output end and is used for accessing detection current; the second input end is used for inputting a reference current; the first output end is connected with the grid electrode of the power tube;
a voltage division module that outputs a divided voltage signal based on the input voltage and the output voltage;
a differential pressure detection module comprising a stuck out-of-order comparator; the pressure difference detection module is used for outputting a current limiting protection signal based on the voltage division signal and the control signal provided by the second output end.
2. The current-limiting differential pressure detection circuit of claim 1, wherein the divided voltage signal comprises: a first divided voltage signal output by a first node and a second divided voltage signal output by a second node;
the voltage division module includes: two first resistors, one of said first resistors being connected between said signal output terminal and said first node, the other of said first resistors being connected between said signal input terminal and said second node; and two second resistors, one of which is connected between the first node and a ground terminal, and the other of which is connected between the second node and the ground terminal.
3. The current-limiting differential pressure detection circuit of claim 2, wherein the differential pressure detection module comprises: one said stuck offset comparator;
the negative phase input end of the fixed offset comparator is connected with the first node, the positive phase input end of the fixed offset comparator is connected with the second node, the output end of the fixed offset comparator is used for outputting the current-limiting protection signal, and the enable end of the fixed offset comparator is connected with the second output end; the fixed offset comparator has an offset voltage.
4. The current-limiting differential pressure detection circuit of claim 3, wherein the fixed offset comparator comprises: first to sixth PMOS and first to third NMOS;
the source electrodes of the first PMOS to the fourth PMOS are all connected with power supply voltage; the grid electrode of the first PMOS is connected with the enabling end of the fixed offset comparator; the drain electrode of the first PMOS is connected with the input end of the bias current; the grid electrode of the second PMOS to the grid electrode of the fourth PMOS and the drain electrode of the second PMOS are connected with the input end of the bias current; the drain electrode of the fourth PMOS is connected with the output end of the fixed offset comparator; the grid electrode of the fifth PMOS is connected with the negative phase input end of the fixed offset comparator, and the source electrode of the fifth PMOS is connected with the drain electrode of the third PMOS; the grid electrode of the sixth PMOS is connected with the positive phase input end of the fixed offset comparator, and the source electrode of the sixth PMOS is connected with the drain electrode of the third PMOS;
the grid electrode of the first NMOS is connected with the drain electrode of the first PMOS, and is connected with the drain electrode of the fifth PMOS and the grid electrode of the second NMOS; the drain electrode of the second NMOS is connected with the drain electrode of the sixth PMOS and is connected with the grid electrode of the third NMOS; the drain electrode of the third NMOS is connected with the output end of the fixed offset comparator; the sources of the first NMOS to the third NMOS are all grounded.
5. The current-limiting differential pressure detection circuit of claim 4, wherein the fifth PMOS and the sixth PMOS are of different sizes;
the first NMOS and the second NMOS have the same size.
6. The current-limiting differential pressure detection circuit of claim 1, wherein the divided voltage signal comprises: a first divided voltage signal output by the first node; a second divided voltage signal output by the second node; a third voltage division signal output by the third node; a fourth voltage division signal output by the fourth node;
the voltage division module includes: two first resistors, one of said first resistors being connected between said signal output terminal and said first node, the other of said first resistors being connected between said signal input terminal and said second node; two second resistors, one of said second resistors being connected between said first node and said third node and the other of said second resistors being connected between said second node and said fourth node; and one of the third resistors is connected between the third node and a ground terminal, and the other third resistor is connected between the fourth node and the ground terminal.
7. The current-limiting differential pressure detection circuit of claim 6, wherein the differential pressure detection module comprises: the first fixed offset comparator, the second fixed offset comparator, the first two-input AND gate and the second two-input AND gate;
the negative phase input end of the first fixed offset comparator is connected with the first node, the positive phase input end of the first fixed offset comparator is connected with the second node, and the output end and the second output end of the first fixed offset comparator are respectively connected with the two input ends of the first two-input AND gate;
the negative phase input end of the second fixed offset comparator is connected with the third node, the positive phase input end of the second fixed offset comparator is connected with the fourth node, and the output end and the second output end of the second fixed offset comparator are respectively connected with the two input ends of the second input AND gate;
the output end of the first two-input AND gate outputs a first current-limiting protection signal, and the output end of the second two-input AND gate outputs a second current-limiting protection signal.
8. The current-limiting differential pressure detection circuit of claim 7, wherein the first fixed offset comparator is the same as the second fixed offset comparator.
9. The current-limiting differential pressure detection circuit of claim 8, wherein the first fixed offset comparator comprises: first to sixth PMOS and first to third NMOS;
the source electrodes of the first PMOS to the fourth PMOS are all connected with power supply voltage; the grid electrode of the first PMOS is connected with the enabling end of the first fixed offset comparator; the drain electrode of the first PMOS is connected with the input end of the bias current; the grid electrode of the second PMOS to the grid electrode of the fourth PMOS and the drain electrode of the second PMOS are connected with the input end of the bias current; the drain electrode of the fourth PMOS is connected with the output end of the first fixed offset comparator; the grid electrode of the fifth PMOS is connected with the negative phase input end of the first fixed offset comparator, and the source electrode of the fifth PMOS is connected with the drain electrode of the third PMOS; the grid electrode of the sixth PMOS is connected with the positive phase input end of the first fixed offset comparator, and the source electrode of the sixth PMOS is connected with the drain electrode of the third PMOS; the enabling end of the first fixed offset comparator inputs a fixed enabling signal;
the grid electrode of the first NMOS is connected with the drain electrode of the first PMOS, and is connected with the drain electrode of the fifth PMOS and the grid electrode of the second NMOS; the drain electrode of the second NMOS is connected with the drain electrode of the sixth PMOS and is connected with the grid electrode of the third NMOS; the drain electrode of the third NMOS is connected with the output end of the first fixed offset comparator; the sources of the first NMOS to the third NMOS are all grounded.
10. The current-limiting differential pressure detection circuit of claim 1, wherein the current-limiting loop comprises:
an operational amplifier, wherein a positive phase input end of the operational amplifier is the first input end, and a negative phase input end of the operational amplifier is the second input end;
the grid electrodes of the first switch tube and the second switch tube are both connected with the output end of the operational amplifier, and the source electrodes of the first switch tube and the second switch tube are both connected with a grounding end; the drain electrode of the first switching tube is the first output end, and the first output end is connected with the driver; the drain electrode of the second switch tube is connected with the power supply voltage through a current source, the drain electrode of the second switch tube is connected with the input end of the phase inverter, and the output end of the phase inverter is the second output end.
11. The current-limiting differential pressure detection circuit of claim 10, wherein the first and second switching transistors are NMOS.
CN202110788886.0A 2021-07-13 2021-07-13 Current-limiting differential pressure detection circuit of power tube Pending CN115616276A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12132307B2 (en) * 2021-07-20 2024-10-29 Tcl China Star Optoelectronics Technology Co., Ltd. Current limiting circuits capable of adjusting current limiting value

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12132307B2 (en) * 2021-07-20 2024-10-29 Tcl China Star Optoelectronics Technology Co., Ltd. Current limiting circuits capable of adjusting current limiting value

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