JP5262981B2 - Latch device and latch method - Google Patents

Description

  The present invention relates to a latch device and a latch method for latching data when a sudden fluctuation of a power supply voltage occurs.

  When power supply wiring is affected by an external load (for example, electrical interference, sudden change in load, switching of other circuits, etc.), the power supply voltage supplied by the power supply wiring may suddenly fluctuate. is there. The power supply voltage that has fluctuated rapidly in this manner may be lowered to a reset voltage at which the circuit is reset, a ground potential, or even lower than the minimum rated potential of the circuit. As a result, critical system data (eg, register values) may be destroyed.

  In order to prevent destruction of data on the IC necessary for the operation of the integrated circuit (hereinafter referred to as “IC”), a backup circuit against a sudden change in power supply voltage may be provided. By providing a backup circuit, data can be automatically restored. For example, a backup power supply battery is used as an off-chip solution, and a comparator and a backup power supply capacitor that detect a drop in power supply voltage are used as an on-chip solution.

  Further, when the supply of power is interrupted, data stored on the first latch circuit is saved to the second latch circuit via the transfer circuit, so that destruction of data on the IC can be prevented (for example, patents) Reference 1).

JP 2008-78754 A

  However, in the above-described conventional technology, when the data latch timing in the IC and the timing of the rapid fluctuation of the power supply voltage coincide, even if there is a backup circuit, there is a possibility that the data cannot be correctly latched. Therefore, the latch result becomes unstable.

  Accordingly, an object of the present invention is to provide a latch device and a latch method that prevent the latch result from becoming unstable even when a sudden change in the latch and the power supply voltage occurs simultaneously.

In order to achieve the above object, a latch device according to the present invention comprises:
A rectifying element connected to the power supply wiring;
A capacitor connected to the forward side of the rectifying element;
A first latch circuit that operates with a capacitor voltage of the capacitor and latches input data in accordance with a first latch signal;
A filter circuit for outputting a third latch signal generated by passing a second latch signal delayed from the first latch signal through a low-pass filter;
An invalidation circuit for invalidating the second latch signal by detecting a drop in the power supply voltage of the power supply wiring;
A second latch circuit that operates with the capacitor voltage and latches output data of the first latch circuit in accordance with the third latch signal.

In order to achieve the above object, the latch method according to the present invention includes:
A first step of latching input data by inputting a first latch signal to a first latch circuit that operates with a capacitor voltage of a capacitor connected to the forward side of a rectifying element connected to a power supply wiring. When,
A second step of generating a third latch signal by passing a second latch signal delayed from the first latch signal through a low-pass filter;
A third step of invalidating the second latch signal by detecting a decrease in power supply voltage of the power supply wiring;
And a fourth step of latching output data of the first latch circuit by inputting the third latch signal to the second latch circuit operating with the capacitor voltage.

  According to the present invention, it is possible to prevent the latch result from becoming unstable even if sudden changes in the latch and the power supply voltage occur simultaneously.

1 is a configuration diagram of a power supply voltage fluctuation countermeasure circuit 100 which is an embodiment of a latch device according to the present invention. FIG. It is a time chart about DIN, WR1, WR2, DOUT. It is a specific example of the filter circuit F1. It is a block diagram of a data holding register that can be preset to 1 or 0. It is an Example of this invention. 4 is a timing chart showing a latch method in a normal state of the power supply voltage fluctuation countermeasure circuit 100. 6 is a timing chart showing a latch method when a sudden fluctuation of the power supply voltage occurs at the rising edge of the latch signal WR1 in the power supply voltage fluctuation countermeasure circuit 100. 5 is a timing chart showing a latch method in the power supply voltage fluctuation countermeasure circuit 100 when a sudden fluctuation of the power supply voltage occurs during a period from the rising edge of the latch signal WR1 to the rising edge of the latch signal WR2. 6 is a timing chart showing a latch method in the power supply voltage variation countermeasure circuit 100 when a sudden variation in power supply voltage occurs during a period from the rising edge of the latch signal WR2 to the rising edge of the latch signal WR1. FIG. 6 is a timing chart showing a latch method when the power supply voltage drops before the rise timing of the latch signal WR2 when the power supply voltage suddenly fluctuates at the rising edge of the latch signal WR2 in the power supply voltage fluctuation countermeasure circuit 100. FIG. is there. FIG. 6 is a timing chart showing a latching method when the power supply voltage drops after the rising timing of the latch signal WR2 when the power supply voltage suddenly fluctuates at the rising edge of the latch signal WR2 in the power supply voltage fluctuation countermeasure circuit 100. FIG. is there. 2 is a backup power supply circuit when the transistor QD of FIG. 1 is replaced with an N-channel transistor. 2 is a backup power supply circuit when the transistor QD of FIG. 1 is replaced with a diode. This is a backup power supply circuit when the resistance element R1 of FIG. 1 is replaced with a P-channel transistor. This is a backup power supply circuit when the resistance element R1 of FIG. 1 is replaced with an N-channel transistor.

  Hereinafter, the configuration and function of a power supply voltage fluctuation countermeasure circuit which is an embodiment of the latch device according to the present invention will be described. The power supply voltage fluctuation countermeasure circuit is a circuit for protecting data held in the circuit from sudden fluctuations in the power supply voltage, and is formed on the IC chip. The power supply voltage fluctuation countermeasure circuit is configured so that a sudden fluctuation of the power supply voltage (for example, fluctuation time: several μs to several tens of μs, voltage drop amount: less than the circuit reset voltage or less than the ground voltage) occurs at the latch timing. Protect data held in the circuit.

  FIG. 1 is a configuration diagram of a power supply voltage fluctuation countermeasure circuit 100 which is an embodiment of a latch device according to the present invention. The power supply voltage fluctuation countermeasure circuit 100 includes a transistor QD, a capacitor C1, a latch circuit D1, a filter circuit F1, an AND circuit N1, and a latch circuit D2 as main components. The power supply voltage fluctuation countermeasure circuit 100 may include a resistance element R1.

  The circuit constituted by Q1, C1, and R1 generates a backup power supply voltage VDD2 for the entire power supply voltage fluctuation countermeasure circuit. D1 and D2 are a first latch circuit and a second latch circuit, respectively. WR1 is a first latch signal for the latch circuit D1, and WR2 is a second latch signal for the latch circuit D2. DIN is input data, and DOUT is output data. N1 is an AND circuit that detects a drop in the power supply voltage VDD. F1 is a low-pass filter that removes the influence of the noise of the latch signal WR2E and the sudden fluctuation of the power supply voltage with respect to the latch circuit D2.

  Each configuration of the power supply voltage fluctuation countermeasure circuit 100 will be described in more detail.

  The transistor QD is a rectifying element connected to a power supply wiring for supplying the power supply voltage VDD. The transistor QD shown in FIG. 1 is a P-channel type. A specific example is a P-channel MOSFET. The gate and drain of the transistor QD are connected to the power supply voltage VDD, and the source of the transistor QD is connected to the capacitor C1. Thus, the transistor QD provided between the power supply wiring and the capacitor functions as a rectifying element whose forward direction is from the power supply voltage VDD side to the capacitor C1 side. When the power supply voltage VDD is higher than the capacitor voltage VDD2 of the capacitor C1 (that is, the backup power supply voltage VDD2), the capacitor C1 is charged by the current flowing in the forward direction. Conversely, when the power supply voltage VDD is lower than the capacitor voltage VDD2, the transistor QD blocks current from flowing in the direction from the capacitor C1 side to the power supply voltage VDD side. In other words, the transistor QD normally supplies a voltage to the capacitor C1, and isolates the capacitor C1 from a decrease in power supply voltage when the power supply voltage decreases.

  As shown in FIG. 12, the transistor QD shown in FIG. 1 may be replaced with an N-channel transistor, or may be replaced with a diode as shown in FIG. By connecting as shown, any element functions as a rectifying element.

  The capacitor C1 is an on-chip capacitor connected to the forward direction side of the transistor QD, and is used as a power source for the power supply voltage fluctuation countermeasure circuit 100. The capacitance of the capacitor C1 is preferably several tens of pF.

  The latch circuit D1 holds the input data DIN from the digital unit according to the periodic latch signal WR1. The latch circuit D2 holds the output data D1OUT output from the latch circuit D1 in accordance with the latch signal WRE2 generated based on the latch signal WR2 delayed in phase with respect to the latch signal WR1. The latch signals WR1 and WR2 are pulse signals having periodic pulses. The output data D2OUT output from the latch circuit D2 is output as the output value DOUT of the power supply voltage fluctuation countermeasure circuit 100.

  FIG. 2 is a time chart for DIN, WR1, WR2, and DOUT. The latch signal WR2 has a phase delay Td with respect to the latch signal WR1.

  In FIG. 1, an AND circuit N1 functions as a detection circuit that detects a decrease in the power supply voltage VDD, and also functions as an invalidation circuit that invalidates the latch signal WR2. The AND circuit N1 invalidates the latch signal WR2 while detecting a decrease in the power supply voltage VDD. That is, the AND circuit N1 invalidates the latch signal WR2 during a period when the power supply voltage VDD is equal to or lower than a predetermined value. The level signal WR2D output from the AND circuit N1 is fixed at the L level regardless of the input of the latch signal WR2 during the period when the latch signal WR2 is invalidated. When the decrease in the power supply voltage VDD is not detected (when the latch signal WR2 is not invalidated), the AND circuit N1 passes through the latch signal WR2 as it is (that is, the level signal WR2D is the latch signal WR2). be equivalent to).

  The filter circuit F1 outputs a latch signal WR2E (third latch signal) generated by processing the latch signal WR2 via the AND circuit N1 with a low-pass filter. This low-pass filter is used in order to avoid the influence of noise on the latch signal WR2 and the rapid fluctuation of the power supply voltage VDD.

  FIG. 3 is a specific example of the filter circuit F1. The filter circuit F1 includes a CR filter as a low-pass filter (a circuit constituted by the resistor element R2 and the on-chip capacitor C2), an inversion circuit I1 that inverts the output of the CR filter, and an inversion circuit that inverts the output of the inversion circuit I1. I2. The filter circuit F1 outputs the output of the inverting circuit I2 as the latch signal WR2E.

  In FIG. 1, a resistance element R1 is a discharge element for determining the operable time of the power supply voltage fluctuation countermeasure circuit 100 that operates according to the power supply voltage of the capacitor C1 in order to decrease the power supply voltage VDD. The resistance element R1 connected to the forward side of the transistor QD is connected in parallel to the capacitor C1. The electric charge of the capacitor C1 is discharged by the resistance element R1. By increasing at least one of the resistance value of the resistance element R1 and the capacitance of the capacitor C1, the operable time of the power supply voltage fluctuation countermeasure circuit 100 can be extended. For example, when it is desired to retain data as long as possible after power-down of the normal power supply voltage VDD, the resistance value of the resistance element R1 and the capacitance of the capacitor C1 may be determined according to the time for which data is desired to be retained. For example, a decrease in power supply voltage during a period of several microseconds to several tens of microseconds can be regarded as a rapid fluctuation, and a decrease in power supply voltage of several hundred microseconds or more can be regarded as a decrease due to power-down of a normal power supply voltage. That's fine.

  As shown in FIG. 14, the resistance element R1 shown in FIG. 1 may be replaced with a P-channel transistor, or may be replaced with an N-channel transistor as shown in FIG. By connecting as shown in the figure, each element functions as a discharge element using a diode between the source and the drain. Further, when the transistor is used as a discharge element, the layout area can be reduced as compared with the case of a resistance element.

  FIG. 6 is a timing chart showing a latch method in the normal state of the power supply voltage fluctuation countermeasure circuit 100. In the normal operation state (that is, the power supply voltage VDD is normal), the backup power supply voltage VDD2 is equal to the voltage obtained by subtracting the loss due to Q1 from the power supply voltage VDD. The latch circuit D1 receives the periodic latch signal WR1, and outputs output data D1OUT to the latch circuit D2. The latch circuit D2 receives a periodic latch signal WR2E based on the latch signal WR2, and outputs data D1OUT latched at the latch timing of the latch signal WR2E as output data D2OUT (DOUT). In the normal operation state, since a decrease in the power supply voltage VDD is not detected, the AND circuit N1 outputs the latch signal WR2 as it is as the output data WR2D. The pulse width of the latch signal WR2E is longer than the pulse width of the latch signal WR1 because it passes through the filter circuit F1.

  When a sudden fluctuation of the power supply voltage occurs, the power supply voltage VDD may drop to 0 V or a reset voltage with reference to the ground potential. In this case, the transistor QD is cut off and the backup power supply VDD2 is separated from the power supply voltage VDD. As a result, the charge of the capacitor C1 does not leak to the power supply voltage VDD side. The capacitor C1 separated from the power supply voltage VDD operates as a power supply for the power supply voltage fluctuation countermeasure circuit 100.

  The generation timing of the rapid fluctuation of the power supply voltage can be classified into four types with respect to the state of the latch signal.

(1) Abrupt fluctuations in the power supply voltage VDD occur simultaneously with the rising edge of the latch signal WR1 of the latch circuit D1 (see FIG. 7).
(2) Abrupt fluctuation of the power supply voltage VDD occurs during the period from the rise of the latch signal WR1 of the latch circuit D1 to the rise of the latch signal WR2 of the latch circuit D2 (see FIG. 8).
(3) Abrupt fluctuation of the power supply voltage VDD occurs simultaneously with the rising edge of the latch signal WR2 of the latch circuit D2 (see FIGS. 10 and 11).
(4) Abrupt fluctuation of the power supply voltage VDD occurs during the period from the rise of the latch signal WR2 of the latch circuit D2 to the rise of the latch signal WR1 of the latch circuit D1 (see FIG. 9).
Hereinafter, the operation of the power supply voltage fluctuation countermeasure circuit 100 when the power supply voltage VDD fluctuates at the respective timings (1) to (4) will be described.

  In the case of (1) (in the case of FIG. 7), the data of the latch circuit D1 cannot be determined because the input data DIN changes simultaneously. Therefore, the data of the latch circuit D1 is not guaranteed. However, in this case, the latch signal WR2 (WR2E) of the latch circuit D2 is not generated after the sudden fluctuation of the power supply voltage VDD by being invalidated by the AND circuit N1. Therefore, the data immediately before the sudden fluctuation timing of the power supply voltage VDD is stably held in the latch circuit D2.

  In the case of (2) (in the case of FIG. 8), the latch signal WR2 (WRE2) of the latch circuit D2 is not generated after the sudden fluctuation of the power supply voltage VDD by being invalidated by the AND circuit N1. Therefore, the latch circuit D2 stably holds the data latched by the previously received latch signal WRE2.

  In the case of (3) (in the case of FIGS. 10 and 11), the data in the latch circuit D1 is normal.

  As shown in FIG. 10, if the power supply voltage VDD decreases before the rising timing of the latch signal WR2 due to the delay in the chip, the latch signal WR2 is invalidated by the AND circuit N1. Therefore, the latch signal WR2E is not generated. Therefore, the latch circuit D2 stably holds the data latched by the previously received latch signal WRE2.

  On the other hand, as shown in FIG. 11, if the power supply voltage VDD decreases with a delay from the rising timing of the latch signal WR2, the AND circuit N1 outputs the latch signal WR2 until the decrease of the power supply voltage VDD is detected. It will pass as it is. The filter circuit F1 normally suppresses or eliminates short pulses of several hundred nanoseconds or less.

  Therefore, if the pulse width of the latch signal WR2 that has passed through the AND circuit N1 is long enough to be removed by the filter circuit F1, the latch signal WR2E is not generated. Therefore, the latch circuit D2 stably holds the data latched by the previously received latch signal WRE2. On the other hand, if the pulse width of the latch signal WR2 that has passed through the AND circuit N1 is a length that cannot be removed by the filter circuit F1, the latch signal WR2 is regarded as a valid signal and is received by the latch circuit D2 as the latch signal WR2E. Is done. As a result, the output data D1OUT output from the latch circuit D1 is transmitted to the latch circuit D2. That is, the latch circuit D2 can stably latch the output data D1OUT at the edge of the latch signal WR2E regarded as a valid signal. Normal data (that is, output data D1OUT) is transmitted to the latch circuit D2 because it is not affected by the sudden fluctuation of the power supply voltage VDD.

  Note that the pulse width of the latch signal WR2 that can be removed by the filter circuit F1 can be determined, for example, by adjusting the constants of the CR circuit shown in FIG.

  In the case of (4) (in the case of FIG. 9), the latch circuit D2 has already acquired normal data. The latch circuit D2 does not receive the latch signal again until the power supply voltage VDD returns to the normal value. Therefore, the latch circuit D2 stably holds the data latched by the previously received latch signal WRE2.

  After the rapid fluctuation of the power supply voltage VDD occurs, the power supply voltage VDD gradually increases to the normal value. During a period when the latest value of the input data DIN is not prepared, the output data DOUT is output from the power supply voltage fluctuation countermeasure circuit 100 with a very short delay. The data output during this period is data held during a sudden change in the power supply voltage VDD, and is data immediately before the sudden change in the power supply voltage VDD occurs.

  When the supply of the original power supply voltage VDD is not stopped suddenly (for example, the main power supply is turned off), the power supply voltage fluctuation countermeasure circuit 100 does not supply the power supply voltage VDD. From the first period, data is retained. However, since the electric charge of the capacitor C1 is discharged through the resistance element R1, the data held by the power supply voltage fluctuation countermeasure circuit 100 is eventually lost. In this way, by providing a configuration capable of discharging by a discharge element such as the resistance element R1, when the power is turned on again after the supply of the original power supply voltage is stopped, the final value before the supply of the power supply voltage is stopped. Output (that is, erroneous output) can be prevented.

  Therefore, as described above, even when the data latch timing (the timing at which the latch signal rises) coincides with the timing at which the power supply voltage changes rapidly, the second timing is greater than the latch signal input to the first latch circuit. Since the phase of the latch signal input to the latch circuit is delayed, it is possible to avoid the loss of data held in the latch circuit.

  That is, when a sudden change in the power supply voltage occurs at the latch timing of the latch circuit D1, since the latch signal of the latch circuit D2 is not generated, the data in the latch circuit D2 remains unchanged.

  Further, when a sudden change in the power supply voltage occurs at the latch timing of the latch circuit D2, the latch signal for the latch circuit D2 is all filtered by the filter circuit if the pulse width of the latch signal is short. If the pulse width of the latch signal is long, it is maintained without being lost by the filter circuit, so that normal data in the latch circuit D1 is transferred to the latch circuit D2 in accordance with the latch signal that has passed through the filter circuit.

  The delay width between the two latch signals may be set longer than the maximum value assumed as the time when the power supply voltage changes rapidly.

  Incidentally, the initial values of the registers in the latch circuits D1 and D2 are set by adjusting the size of the core part of the back-to-back inverter. By setting the ratio of the gate width and gate length of a plurality of transistors constituting two back-to-back inverters to be unbalanced rather than being balanced among the plurality of transistors, an IC power-on register is set. Can always be set to a predetermined value (1 or 0).

  FIG. 4 is a configuration diagram of the core portion of the register of the latch circuit. As shown below, the initial value of each register can be preset. The transistors Q1, Q2, Q3, and Q4 form two back-to-back inverters that perform positive feedback for data retention. Generally, in order to form a balanced structure, the sizes of Q1 and Q3 and the sizes of Q2 and Q4 are designed to be equal. In the case of this balanced structure, the values at points A and B, which are input / output values of the two back-to-back inverters, take random initial values.

On the other hand, in the present invention, the gate sizes of the transistors Q1, Q2, Q3, and Q4 are set unbalanced among the transistors. For example, when it is desired to preset the initial value of the output terminal QO to 1, the initial value of the output terminal QO can be preset to 1 by any one of the following four setting methods.
[Setting method 1]
The ratio of the gate width and the gate length of the transistor Q4 is set larger than the ratio of Q2, and the sizes of the transistors Q1 and Q3 are set equal. Thereby, the transistor Q4 can be easily turned on.
[Setting method 2]
The ratio of the gate width and the gate length of the transistor Q3 is set smaller than the ratio of Q1, and the sizes of the transistors Q2 and Q4 are set equal. Thereby, the transistor Q1 can be easily turned on.
[Setting method 3]
The ratio of the gate width and the gate length of the transistor Q4 is set larger than the ratio of Q2, and the ratio of the transistor Q3 is set smaller than the ratio of Q1. Thereby, the transistors Q1 and Q4 can be easily turned on.

  By any one of these setting methods, the balance of the transistor sizes is lost, and the point A is inclined lower than the point B. Since the value of the point B converges to 0 and the value of the point A converges to 1 by the positive feedback operation, the initial value of the output terminal QO can be preset to 1. In the same way, the initial value of the output terminal QO can be preset to 0 by reversing the magnitude relationship of the ratios shown in the above setting method.

  FIG. 5 is a specific example of a chip to which the present invention is applied. A low-speed sampling AD converter (ADC) is controlled by a digital control unit, which is digital logic, and periodically generates data DIN for a power supply voltage fluctuation countermeasure circuit. The latch signals WR1 and WR2 are generated by digital logic according to a timing sequence. When the ADC outputs data DIN at a rate of 1 sample / ms, 1 ms is required to restore the final value to the output DOUT without the power supply voltage fluctuation countermeasure circuit. However, according to the present invention, the final value can be restored to the output DOUT in several tens of μs.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

  For example, the components in FIGS. 1 and 12 to 15 may be replaced with each other.

QD, Q1 to Q6 Transistor D1 Latch circuit C1 Capacitor R1, R2 Resistance element N1 AND circuit F1 Filter circuit I1, I2 Inversion circuit

Claims (12)

A rectifying element connected to the power supply wiring;
A capacitor connected to the forward side of the rectifying element;
A first latch circuit that operates with a capacitor voltage of the capacitor and latches input data in accordance with a first latch signal;
A filter circuit for outputting a third latch signal generated by passing a second latch signal delayed from the first latch signal through a low-pass filter;
An invalidation circuit for invalidating the second latch signal by detecting a drop in the power supply voltage of the power supply wiring;
And a second latch circuit that operates with the capacitor voltage and latches output data of the first latch circuit in accordance with the third latch signal. The filter circuit includes a CR filter as the low-pass filter, a first inverting circuit for inverting the output of the CR filter, and a second inverting circuit for inverting the output of the first inverting circuit,
The latch device according to claim 1, wherein the third latch signal is output based on an output of the second inverting circuit.   The latch device according to claim 1, further comprising: a discharge element that discharges the electric charge of the capacitor on a forward side of the rectifying element.   The latch device according to claim 3, wherein the discharge element is connected in parallel to the capacitor.   The latch device according to claim 4, wherein the discharge element is a resistance element.   The latch device according to claim 4, wherein the discharge element is an N-channel transistor or a P-channel transistor.   When the power supply voltage is higher than the capacitor voltage, the capacitor is charged by a current flowing in the forward direction of the rectifier element, and when the power supply voltage is lower than the capacitor voltage, the current flowing through the rectifier element is cut off. The latch device according to claim 1 or 2.   The latch device according to claim 7, wherein the rectifying element is an N-channel transistor or a P-channel transistor.   The latch device according to claim 7, wherein the rectifying element is a diode. The first latch circuit and the second latch circuit include a back-to-back inverter composed of a plurality of transistors,
The latch device according to claim 1, wherein gate dimensions of the plurality of transistors are set to be unbalanced.   The latch device according to claim 1 or 2, further comprising a latch signal output circuit that outputs the first latch signal and the second latch signal. A first step of latching input data by inputting a first latch signal to a first latch circuit that operates with a capacitor voltage of a capacitor connected to the forward side of a rectifying element connected to a power supply wiring. When,
A second step of generating a third latch signal by passing a second latch signal delayed from the first latch signal through a low-pass filter;
A third step of invalidating the second latch signal by detecting a decrease in power supply voltage of the power supply wiring;
And a fourth step of latching output data of the first latch circuit by inputting the third latch signal to the second latch circuit operating with the capacitor voltage.