CN101859595B - Latch device and latch method thereof - Google Patents

Abstract

The invention relates to a latch device and a latch method thereof. The latch device comprises a rectifying element, a capacitor, a first latch circuit, a filter circuit, an invalidation circuit and a second latch circuit, wherein, the rectifying element is connected with power wiring; the capacitor is connected with the forward side of the rectifying element; the first latch circuit operates under the capacitor voltage and latches input data according to a first latch signal; the filter circuit outputs a third latch signal and drives a second latch signal which is more delayed than the first latch signal to generate a third latch signal through a low-pass filter; the invalidation circuit invalidates the second latch signal by means of detecting reduced power supply voltage of power wiring; and the second latch circuit operates under the capacitor voltage and latches the output data of the first latch circuit according to the third latch signal.

Description

Latch device and latch method

technical field

The invention relates to a latch device and a latch method for latching data when a power supply voltage fluctuates sharply.

Background technique

When the power supply wiring is affected by an external load (for example, electrical noise, sudden change of load, switching of other circuits, etc.), the power supply voltage supplied by the power supply wiring may fluctuate rapidly. Such sudden fluctuations in the power supply voltage may drop below the reset voltage at which reset occurs in the circuit, the ground potential, or even the lowest rated potential of the circuit. As a result, important system data (such as register values, etc.) are often destroyed.

In order to prevent data on the IC necessary for the operation of an integrated circuit (hereinafter referred to as "IC") from being destroyed, a backup circuit against sudden fluctuations in power supply voltage is often provided. By setting up a backup circuit, data can be automatically restored. For example, a backup power supply battery is used as an off-chip solution, and a comparator for detecting a drop in power supply voltage and a backup power supply capacitor are used as an on-chip solution.

In addition, when the power supply is cut off, the data stored in the first latch circuit is held in the second latch circuit through the transfer circuit, thereby preventing data on the IC from being destroyed (for example, refer to Patent Document 1).

Patent Document 1: Japanese Patent Laid-Open No. 2008-78754

However, in the prior art described above, when the timing of data latching in the IC coincides with the timing of a sudden change in power supply voltage, data may not be latched accurately even if there is a backup circuit. Therefore, the latch result will be unstable.

Contents of the invention

Therefore, an object of the present invention is to provide a latch device and a latch method capable of stabilizing a latch result even if a latch and a power supply voltage fluctuate rapidly at the same time.

In order to achieve the above object, the latch device related to the present invention includes:

Rectifier elements connected to power wiring;

a capacitor connected to the positive side of the rectifying element;

a first latch circuit operating at a capacitor voltage of the capacitor and latching input data according to a first latch signal;

a filter circuit that outputs a third latch signal, which passes a second latch signal delayed from the first latch signal through a low-pass filter to generate the third latch signal;

an invalidation circuit that invalidates the second latch signal by detecting a drop in a power supply voltage of the power supply wiring; and

a second latch circuit that operates at the capacitor voltage and latches the output data of the first latch circuit according to the third latch signal.

In addition, in order to achieve the above object, the latching method related to the present invention includes:

In a first step, input data is latched by inputting a first latch signal to a first latch circuit operating at a voltage of a capacitor connected to a rectifying element connected to a power supply wiring positive side of

In a second step, passing a second latch signal delayed from the first latch signal through a low-pass filter to generate a third latch signal;

a third step of deactivating the second latch signal by detecting a drop in a power supply voltage of the power supply wiring; and

The fourth step is to input the third latch signal to the second latch circuit operating at the capacitor voltage to latch the output data of the first latch circuit.

Invention effect

According to the present invention, even if latching and a sudden fluctuation of the power supply voltage occur at the same time, it is possible to prevent the latching result from being unstable.

Description of drawings

FIG. 1 is a configuration diagram of a power supply voltage fluctuation countermeasure circuit 100 as an embodiment of a latch device according to the present invention.

Figure 2 is a timing diagram about DIN, WR1, WR2, and DOUT.

FIG. 3 is a specific example of the filter circuit F1.

Figure 4 is a structural diagram of a data holding register that can be preset to 1 or 0.

Fig. 5 is an embodiment of the present invention.

FIG. 6 is a timing chart showing a latch method in a normal state of the power supply voltage fluctuation countermeasure circuit 100 .

FIG. 7 is a timing chart showing a latch method of the power supply voltage fluctuation countermeasure circuit 100 when a sudden fluctuation of the power supply voltage occurs at the rising edge of the latch signal WR1 .

FIG. 8 is a timing chart showing a latch method when a sudden change in the power supply voltage occurs between the rising edge of the latch signal WR1 and the rising edge of the latch signal WR2 in the power supply voltage fluctuation countermeasure circuit 100 .

FIG. 9 is a timing chart showing a latch method when a sudden change in the power supply voltage occurs between the rising edge of the latch signal WR2 and the rising edge of the latch signal WR1 in the power supply voltage fluctuation countermeasure circuit 100 .

10 is a timing chart showing a latch method in power supply voltage fluctuation countermeasure circuit 100 when the power supply voltage suddenly fluctuates at the rising edge of latch signal WR2 and the power supply voltage falls before the rising timing of latch signal WR2.

11 is a timing chart showing a latch method when the power supply voltage falls later than the rising timing of the latch signal WR2 when the power supply voltage suddenly fluctuates at the rising edge of the latch signal WR2 in the power supply voltage fluctuation countermeasure circuit 100 .

FIG. 12 is a backup power supply circuit in which the transistor QD in FIG. 1 is replaced with an N-channel transistor.

FIG. 13 is a backup power supply circuit in which the transistor QD in FIG. 1 is replaced with a diode.

FIG. 14 is a backup power supply circuit when the resistor R1 in FIG. 1 is replaced by a P-channel transistor.

FIG. 15 is a backup power supply circuit in which the resistor R1 in FIG. 1 is replaced by an N-channel transistor.

Explanation of symbols in the figure:

QD, Q1～Q6 Transistors

D1 latch circuit

C1 capacitor

R1, R2 Resistive elements

N1 AND circuit

F1 filter circuit

I1, I2 reverse circuit

Detailed ways

Next, the structure and function of the power supply voltage variation countermeasure circuit as an embodiment of the latch device according to the present invention will be described. The power supply voltage fluctuation countermeasure circuit is a circuit for protecting data held in the circuit from sudden fluctuations in the power supply voltage, and is formed on an IC chip. Even if a sudden change in the power supply voltage occurs during the latch timing (e.g., change time: several μseconds to tens of μseconds, amount of voltage drop: below the reset voltage of the circuit or below the ground voltage), the power supply voltage fluctuation countermeasure circuit will protect data held in the circuit.

FIG. 1 is a configuration diagram of a power supply voltage fluctuation countermeasure circuit 100 as an embodiment of a latch device according to the present invention. The power supply voltage variation countermeasure circuit 100 includes, as main components, a transistor QD, a capacitor C1, a latch circuit D1, a filter circuit F1, an AND circuit N1, and a latch circuit D2. In addition, the power supply voltage fluctuation countermeasure circuit 100 further includes a resistance element R1.

A circuit composed of Q1, C1, and R1 generates a backup power supply voltage VDD2 for the entire power supply voltage fluctuation countermeasure circuit. D1 and D2 are a first latch circuit and a second latch circuit, respectively. WR1 is a first latch signal for the latch circuit D1, and WR2 is a second latch signal for the latch circuit D2. DIN is the input data and DOUT is the output data. N1 is an AND circuit that detects a drop in the power supply voltage VDD. F1 is a low-pass filter for removing the influence of the noise of the latch signal WR2E and the sudden fluctuation of the power supply voltage on the latch circuit D2.

Each configuration of the power supply voltage fluctuation countermeasure circuit 100 will be described in more detail.

Transistor QD is a rectifying element connected to a power supply wiring for supplying a power supply voltage VDD. The transistor QD shown in FIG. 1 is a P-channel type transistor. As a specific example, a P-channel MOSFET may be mentioned. The gate and drain of the transistor QD are connected to the power supply voltage VDD, and the source of the transistor QD is connected to the capacitor C1. The transistor QD thus provided between the power supply wiring and the capacitor functions as a rectifying element whose direction is forward from the power supply voltage VDD side to the capacitor C1 side. In the case where the power supply voltage VDD is higher than the capacitor voltage VDD2 of the capacitor C1 (ie, the backup power supply voltage VDD2 ), the capacitor C1 is charged due to the forward flow of current. Conversely, when the power supply voltage VDD is lower than the capacitor voltage VDD2 , the transistor QD blocks the flow of current from the capacitor C1 side to the power supply voltage VDD side. That is, transistor QD normally supplies a voltage to capacitor C1 , decoupling capacitor C1 from a drop in supply voltage in the event of a drop in supply voltage.

Furthermore, as shown in FIG. 12 , the transistor QD shown in FIG. 1 may be replaced by an N-channel transistor, or may be replaced by a diode as shown in FIG. 13 . According to the connection shown in the figure, any element can function as a rectifying element.

The capacitor C1 is an on-chip capacitor connected to the positive side of the transistor QD, and is used as a power supply of the power supply voltage fluctuation countermeasure circuit 100 . Capacitor C1 can have a capacity of tens of pF.

The latch circuit D1 holds the input data DIN from the digital unit according to the periodic latch signal WR1. The latch circuit D2 holds the output data D1OUT output from the latch circuit D1 according to a latch signal WRE2 generated based on a latch signal WR2 whose phase is delayed with respect to the latch signal WR1. The latch signals WR1 and WR2 are pulse signals having periodic pulses. Furthermore, the output data D2OUT output from the latch circuit D2 is output as the output value DOUT of the power supply voltage fluctuation countermeasure circuit 100 .

Fig. 2 is the sequence chart about DIN, WR1, WR2, DOUT. The latch signal WR2 has a phase delay Td with respect to the latch signal WR1.

In FIG. 1 , AND circuit N1 functions as a detection circuit for detecting a drop in power supply voltage VDD, and also functions as an invalidation circuit for invalidating latch signal WR2 . The AND circuit N1 disables the latch signal WR2 while detecting a drop in the power supply voltage VDD. That is, AND circuit N1 disables latch signal WR2 while power supply voltage VDD is equal to or less than a predetermined value. The level signal WR2D output from the AND circuit N1 is fixed at the L level while the latch signal WR2 is inactive regardless of the input of the latch signal WR2 . When the AND circuit N1 does not detect a drop in the power supply voltage VDD (when the latch signal WR2 is not invalidated), it directly outputs the latch signal WR2 unchanged (that is, the level signal WR2D is equal to the latch signal WR2) .

The filter circuit F1 processes the latch signal WR2 passed through the AND circuit N1 with a low-pass filter, and outputs the generated latch signal WR2E (third latch signal). This low-pass filter is used to avoid the influence of noise and sudden fluctuations in the power supply voltage VDD on the latch signal WR2.

FIG. 3 is a specific example of the filter circuit F1. The filter circuit F1 includes: a CR filter (a circuit composed of a resistive element R2 and an on-chip capacitor C2) as a low-pass filter, an inverting circuit I1 for inverting the output of the CR filter, and an inverting circuit I1 for inverting the output of the inverting circuit I1. The inverting circuit I2 that outputs the reverse. The filter circuit F1 outputs the output of the inverting circuit I2 as a latch signal WR2E.

In FIG. 1 , the resistance element R1 is a discharge element for determining the operable time of the power supply voltage variation countermeasure circuit 100 that operates according to the power supply voltage of the capacitor C1 due to the drop of the power supply voltage VDD. The resistance element R1 connected to the positive side of the transistor QD is connected in parallel with the capacitor C1. The charge of the capacitor C1 is discharged through the resistive element R1. By increasing at least one of the resistance value of the resistance element R1 and the capacity of the capacitor C1, the operable time of the power supply voltage fluctuation countermeasure circuit 100 can be extended. For example, when it is desired to hold data for as long as possible after the normal power supply voltage VDD drops, the resistance value of the resistive element R1 and the capacity of the capacitor C1 can be determined according to the time to hold data. For example, a drop in the power supply voltage for a period of several microseconds to several tens of microseconds can be regarded as a sudden change, and a drop in the power supply voltage of more than a few hundred microseconds can be regarded as a drop caused by a normal power supply voltage drop.

Furthermore, as shown in FIG. 14, the resistance element R1 shown in FIG. 1 may be replaced with a P-channel transistor, or as shown in FIG. 15, it may be replaced with an N-channel transistor. With the connection shown in the figure, any element functions as a discharge element using the diode between the source and the drain. In addition, the layout area can be reduced in the case of using a transistor as a discharge element compared with the case of a resistance element.

FIG. 6 is a timing chart showing a latch method in a normal state of the power supply voltage fluctuation countermeasure circuit 100 . In a normal working state (that is, a normal state of the power supply voltage VDD), the backup power supply voltage VDD2 is equal to the voltage obtained by subtracting the loss caused by Q1 from the power supply voltage VDD. The latch circuit D1 receives the periodic latch signal WR1, and outputs the output data D1OUT to the latch circuit D2. The latch circuit D2 receives the latch signal WR2E based on the period of the latch signal WR2, and outputs the latched data D1OUT as output data D2OUT (DOUT) at the timing of latching the latch signal WR2E. In the normal working state, since the drop of the power supply voltage VDD is not detected, the AND circuit N1 still outputs the latch signal WR2 as the output data WR2D. In addition, the pulse width of the latch signal WR2E is longer than the pulse width of the latch signal WR1 because it passes through the filter circuit F1.

When a sudden change in the power supply voltage occurs, the power supply voltage VDD often drops to 0 V or a reset voltage with reference to the ground potential. In this case, the transistor QD is turned off, and the backup power supply VDD2 is separated from the power supply voltage VDD. As a result, the charge of the capacitor C1 does not leak to the power supply voltage VDD side. The capacitor C1 separated from the power supply voltage VDD operates as a power supply of the power supply voltage fluctuation countermeasure circuit 100 .

The timing at which a sudden change in the power supply voltage occurs can be classified into four types with respect to the state of the latch signal.

(1) A sudden change in the power supply voltage VDD occurs simultaneously with the rising edge of the latch signal WR1 of the latch circuit D1 (see FIG. 7 )

(2) During the period from the rise of the latch signal WR1 of the latch circuit D1 to the rise of the latch signal WR2 of the latch circuit D2, a sudden change in the power supply voltage VDD occurs (see FIG. 8 ).

(3) A sudden change in the power supply voltage VDD occurs simultaneously with the rising edge of the latch signal WR2 of the latch circuit D2 (see FIGS. 10 and 11 )

(4) During the period from the rise of the latch signal WR2 of the latch circuit D2 to the rise of the latch signal WR1 of the latch circuit D1, a sudden change in the power supply voltage VDD occurs (see FIG. 9 ).

Next, the operation of the power supply voltage variation countermeasure circuit 100 when the power supply voltage VDD fluctuates at each of the timings (1) to (4) will be described.

In the case of (1) (the case of FIG. 7 ), the data of the latch circuit D1 cannot be determined because the input data DIN changes simultaneously. Therefore, the data of the latch circuit D1 cannot be guaranteed. However, in this case, since the latch signal WR2 (WR2E) of the latch circuit D2 is negated by the AND circuit N1, it does not regenerate after a sudden change in the power supply voltage VDD. Therefore, the data before the sudden fluctuation of the power supply voltage VDD is held stably in the latch circuit D2.

In the case of (2) (the case of FIG. 8 ), since the latch signal WR2 (WRE2) of the latch circuit D2 is negated by the AND circuit N1, it does not occur after a sudden change in the power supply voltage VDD. Therefore, the data latched by the latch signal WRE2 received last time is held stably in the latch circuit D2.

In the case of (3) (the cases of FIGS. 10 and 11 ), the data of the latch circuit D1 is normal.

As shown in FIG. 10 , if the power supply voltage VDD falls before the rising timing of the latch signal WR2 due to delay in the chip, the AND circuit N1 invalidates the latch signal WR2 . Therefore, the latch signal WR2E is not generated. Therefore, the data latched by the latch signal WRE2 received last time is held stably in the latch circuit D2.

On the other hand, as shown in FIG. 11, if the power supply voltage VDD falls later than the rising timing of the latch signal WR2, the AND circuit N1 directly passes the latch signal WR2 until the power supply voltage VDD fall is detected. The filter circuit F1 typically suppresses or removes short pulses below a few hundred nanoseconds.

Therefore, if the pulse width of the latch signal WR2 passing through the AND circuit N1 is a length that can be eliminated by the filter circuit F1, the latch signal WR2E is not generated. Thus, the data latched by the latch signal WRE2 received last time is stably held in the latch circuit D2. On the other hand, if the pulse width of the latch signal WR2 passing through the AND circuit N1 is a length that cannot be removed by the filter circuit F1, then this latch signal WR2 is regarded as an effective signal, and is output by the latch circuit D2 as the latch signal WR2E. take over. As a result, the output data D1OUT output from the latch circuit D1 is transferred to the latch circuit D2. That is, the latch circuit D2 can stably latch the output data D1OUT at the edge of the latch signal WR2E regarded as an effective signal. Since it is not affected by sudden fluctuations in the power supply voltage VDD, normal data (that is, output data D1OUT) is transferred to the latch circuit D2.

Furthermore, the pulse width of the latch signal WR2 that can be removed by the filter circuit F1 can be determined, for example, by adjusting constants of the CR circuit shown in FIG. 3 .

In the case of (4) (the case of FIG. 9 ), the latch circuit D2 has already acquired normal data. Moreover, the latch circuit D2 will not receive the latch signal again until the power supply voltage VDD returns to a normal value. Therefore, the data latched by the latch signal WRE2 received last time is stably held in the latch circuit D2.

After a sharp fluctuation of the power supply voltage VDD occurs, the power supply voltage VDD gradually rises to a normal value. While the latest value of input data DIN cannot be prepared, output data DOUT is output from power supply voltage fluctuation countermeasure circuit 100 with an extremely short delay. The data output during this period is data held during a sudden change in the power supply voltage VDD, and is data before the sudden change in the power supply voltage VDD occurs.

In addition, when there is no sudden change in the power supply voltage VDD, but the power supply of the original power supply voltage VDD is stopped (for example, the power supply of the main power supply is turned off), the power supply voltage fluctuation countermeasure circuit 100 initially hold data for a period of time. However, since the charge of the capacitor C1 is discharged through the resistance element R1, the data held by the power supply voltage variation countermeasure circuit 100 will eventually disappear. In this way, by providing a discharge element such as the resistance element R1, when the power supply is turned on again after the original power supply voltage is stopped, it is possible to prevent output of the final value of the power supply voltage before the power supply stop (that is, erroneous output).

Therefore, according to the above description, even when the data latch timing (the latch signal rising timing) coincides with the timing of sudden fluctuations in the power supply voltage, since the phase ratio of the latch signal input to the second latch circuit to the second latch circuit is 1 Since the latch signal of the latch circuit is delayed, it is possible to avoid erasure of data held in the latch circuit.

That is, when the power supply voltage suddenly fluctuates at the latch timing of the latch circuit D1, since the latch signal of the latch circuit D2 is not generated, the data in the latch circuit D2 is held without changing.

Also, when a sudden change in the power supply voltage occurs at the latching timing of the latch circuit D2, if the pulse width of the latch signal is shorter than that of the latch signal of the latch circuit D2, all of it is filtered out by the filter circuit. If the pulse width of the latch signal is long, it is maintained without being canceled by the filter circuit, so the normal data of the latch circuit D1 is transmitted to the latch circuit D2 according to the latch signal passed through the filter circuit.

In addition, the delay width between the two latch signals can be set longer than the maximum value of the time when the power supply voltage fluctuates rapidly.

However, the initial values of the registers in the latch circuits D1 and D2 are set by adjusting the size of the chip part of the back-to-back inverter. By making the ratio of gate width and gate length of a plurality of transistors constituting two back-to-back inverters unbalanced among these plurality of transistors, and setting them to be unbalanced, the power supply connection of the IC can be made The initial value of the register when it is turned on must be set to a predetermined value (1 or 0).

4 is a configuration diagram of a chip portion of a register of a latch circuit. The initial value of each register can be preset as shown below. Transistors Q1, Q2, Q3, and Q4 form two back-to-back inverters for positive feedback for data retention. Generally, to form a balanced structure, Q1 and Q3 are equally sized and Q2 and Q4 are sized. In the case of this balanced structure, the values of points A and B, which are the input and output values of the two back-to-back inverters, take random initial values.

On the other hand, in the present invention, the gate sizes of the transistors Q1, Q2, Q3, and Q4 are set to be unbalanced among the transistors. For example, when you want to preset the initial value of the output terminal QO to 1, you can preset the initial value of the output terminal QO to 1 by any one of the four setting methods shown below.

[setting method 1]

The ratio of the gate width to the gate length of transistor Q4 is set to be larger than the ratio of gate width to gate length of Q2, and the dimensions of transistors Q1 and Q3 are set to be equal. This enables transistor Q4 to be easily turned on.

[setting method 2]

The ratio of the gate width to the gate length of transistor Q3 is set to be smaller than the ratio of gate width to gate length of Q1, and the dimensions of transistors Q2 and Q4 are set to be equal. As a result, transistor Q1 can be easily turned on.

[setting method 3]

The ratio of gate width to gate length of transistor Q4 is set to be larger than the ratio of gate width to gate length of Q2, and the ratio of gate width to gate length of transistor Q3 is set to be smaller than that of Q1 Ratio of width to gate length. This makes it easy to turn on the transistors Q1 and Q4.

By any one of these setting methods, the balance of the dimensions of the transistors is broken, and the point A tends to be lower than the point B. Furthermore, since the value at point B converges to 0 and the value at point A converges to 1 by the positive feedback operation, the initial value of the output terminal QO can be preset to 1. In the same way, the initial value of the output terminal QO can be preset to 0 by inverting the magnitude relationship of the ratio shown in the above setting method.

Example

FIG. 5 is a specific example of a chip to which the present invention is applied. The low-speed sampling AD converter (ADC) is controlled by the digital control unit as a digital logic device, and periodically generates data DIN for the power supply voltage fluctuation countermeasure circuit. Latch signals WR1 and WR2 are generated by sequential digital logic. When the ADC outputs data DIN at a rate of 1 sample/ms, if there is no power supply voltage fluctuation countermeasure circuit, it takes 1ms to return the final value to output DOUT. However, according to the present invention, the final value can be restored to the output DOUT in tens of μs.

Although preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments, and various modifications and substitutions can be added to the above embodiments without departing from the scope of the present invention.

For example, each component in FIGS. 1, 12 to 15 can be replaced with each other.

Claims (12)

1. latch means comprises:

The rectifier cell that is connected with power-supply wiring;

The capacitor that is connected with the forward side of said rectifier cell;

First latch cicuit, its capacitor electrode at said capacitor are depressed work and are latched the input data according to first latch signal;

Export the filtering circuit of the 3rd latch signal, it makes second latch signal that postpones than said first latch signal produce the 3rd latch signal through low-pass filter;

The AND circuit, the decline of its supply voltage through detecting said power-supply wiring makes said second latch signal invalid; And

Second latch cicuit, it depresses work at said capacitor electrode, and latchs the output data of said first latch cicuit according to said the 3rd latch signal.

2. latch means according to claim 1 is characterized in that,

Said filtering circuit comprises: as the CR wave filter of said low-pass filter, make the first reverse negater circuit of output of CR wave filter, and the second reverse negater circuit of output that makes first negater circuit,

This latch means is exported said the 3rd latch signal according to the output of said second negater circuit.

3. latch means according to claim 1 and 2 is characterized in that,

In the forward side of said rectifier cell, possesses the arresting element of the charge discharge that makes said capacitor.

4. latch means according to claim 3 is characterized in that,

Said arresting element and said capacitor are connected in parallel.

5. latch means according to claim 4 is characterized in that,

Said arresting element is a resistive element.

6. latch means according to claim 4 is characterized in that,

Said arresting element is N channel transistor or P channel transistor.

7. latch means according to claim 1 and 2 is characterized in that,

When said supply voltage is higher than said condenser voltage, make just always said capacitor being charged of the said rectifier cell of current direction, when said supply voltage forced down than said capacitor electrode, blocking flow to the electric current of said rectifier cell.

8. latch means according to claim 7 is characterized in that,

Said rectifier cell is N channel transistor or P channel transistor.

9. latch means according to claim 7 is characterized in that,

Said rectifier cell is a diode.

10. latch means according to claim 1 and 2 is characterized in that,

Said first latch cicuit and said second latch cicuit comprise the back-to-back reverser that is made up of a plurality of transistors;

Set said a plurality of transistorized grid size lopsidedly.

11. latch means according to claim 1 and 2 is characterized in that,

The latch signal output circuit that also comprises said first latch signal of output and said second latch signal.

12. a latch method comprises:

First step latchs the input data through first latch signal is input to first latch cicuit, and wherein, this first latch cicuit is depressed work at capacitor electrode, and this capacitor is connected to the forward side of the rectifier cell that is connected with power-supply wiring;

Second step makes second latch signal that postpones than said first latch signal produce the 3rd latch signal through low-pass filter;

Third step, the decline of the supply voltage through detecting said power-supply wiring makes said second latch signal invalid; And

The 4th step makes said the 3rd latch signal be input to the output data that second latch cicuit of depressing work at said capacitor electrode latchs said first latch cicuit.

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