JP6740723B2 - Ring mixer - Google Patents

Description

The present invention relates to a ring mixer, for example, a ring mixer having an FET.

The ring mixer is a circuit that mixes an input signal with a local oscillation signal and outputs an output signal. A ring mixer using an FET (Field Effect Transistor) that outputs an output signal is known (Patent Document 1).

Japanese Unexamined Patent Publication No. 8-204458

However, in the ring mixer using the FET, the conversion gain from the input signal to the output signal is low. The present invention has been made in view of the above problems, and an object thereof is to improve conversion gain.

According to an embodiment of the present invention, a pair of distributed constant lines are connected in series, and four lines connected in a ring shape are provided between adjacent lines of the four lines, and are provided at opposing nodes. The reference potential is supplied to the four nodes to which the oscillation signal is input and the output signals are output from the remaining opposing nodes, the drain is connected to the node between the pair of distributed constant lines, and the input signal is input to the gate. Is a ring mixer including four FETs input by the.

According to the present invention, the conversion gain can be improved.

FIG. 1 is a circuit diagram of a ring mixer according to Comparative Example 1. FIG. 2 is a diagram showing the voltage of each signal in Comparative Example 1 and Example 1 with respect to time. FIG. 3 is a diagram showing the conversion gain with respect to the frequency in Comparative Example 1. FIG. 4A to FIG. 4D are equivalent circuit diagrams showing the line 22. FIG. 5 is a circuit diagram of the ring mixer according to the first embodiment. FIG. 6A to FIG. 6D are equivalent circuit diagrams showing the line 22. FIG. 7 is a diagram showing conversion gain with respect to frequency in the first embodiment. FIG. 8 is a diagram showing the conversion gain with respect to the power of the input signal in the first embodiment. FIG. 9 is a diagram showing the conversion phase with respect to the power of the input signal in the first embodiment.

[Description of Embodiments of the Present Invention]
First, the contents of the embodiments of the present invention will be listed and described.
According to the present invention, a pair of distributed constant lines are respectively connected in series and provided between four lines connected in a ring shape and adjacent lines of the four lines, and an oscillation signal is input to a node facing each other. Then, the reference potential is supplied to the four nodes outputting the output signals from the remaining opposing nodes, the source is connected to the nodes between the pair of distributed constant lines, and the input signal is input to the gate. A ring mixer including two FETs. As a result, when the FET is turned on, the distributed constant line viewed from the node between the adjacent lines can be opened. As a result, the line can be cut off. Therefore, the conversion gain from the input signal to the output signal can be improved.

Of the four FETs, one of the balanced input signals that is the input signal is input to the gates of the facing FETs, and the other of the balanced input terminals is input to the gates of the remaining facing FETs, and one of the facing nodes One of the balanced oscillation signals that is the oscillation signal is input to the other of the opposite nodes, and the other of the balanced oscillation signals is input to the other of the opposite nodes, and one of the remaining opposite nodes outputs the balanced output signal that is the output signal. It is preferable that one of them outputs and the other of the balanced output signals outputs from the other of the remaining opposing nodes. As a result, the balanced input signal can be mixed with the balanced oscillation signal and output as a balanced output signal.

It is preferable that each of the pair of distributed constant lines in the four lines has an electrical length of 1/8 or more and 3/8 or less of the wavelength of the oscillation signal. Thereby, when the FET is turned on, the distributed constant line viewed from the node between the adjacent lines can be ideally opened. This allows the line to be blocked more ideally. Therefore, the conversion gain from the input signal to the output signal can be further improved.

[Comparative Example 1]
FIG. 1 is a circuit diagram of a ring mixer according to Comparative Example 1. As shown in FIG. 1, in the ring mixer 102, the lines 22, 24 are respectively provided between the nodes N6 and N8, between the nodes N7 and N9, between the nodes N6 and N9, and between the nodes N7 and N8. , 26 and 28 are connected in series. FETs 32 to 38 are connected in series to the lines 22 to 28, respectively. The oscillation terminal LO1 is connected to the gates of the FETs 32 and 34, and the oscillation terminal LO2 is connected to the gates of the FETs 36 and 38. Input terminals IF1 and IF2 are connected to nodes N8 and N9, respectively. Output terminals RF1 and RF2 are connected to nodes N6 and N7, respectively.

Oscillation signals LO+ and LO- are input to the oscillation terminals LO1 and LO2, respectively. Input signals IF+ and IF− are input to the input terminals IF1 and IF2, respectively. Output signals RF+ and RF- are output from the output terminals RF1 and RF2, respectively. The oscillation signals LO+ and LO-, the input signals IF+ and IF-, and the output signals RF+ and RF- are balanced signals. In FIG. 1, the solid line shows the signal flow when the FETs 32 and 34 are on and the FETs 36 and 38 are off. The dashed line shows the signal flow when FETs 32 and 34 are off and FETs 36 and 38 are on. The thick line shows the flow of the input signal IF+, and the thin line shows the flow of the input signal IF-.

FIG. 2 is a diagram showing the voltage of each signal in Comparative Example 1 and Example 1 with respect to time. The oscillation signal LO+, the input signal IF+, and the output signal RF+ with respect to time are shown. Time is an arbitrary coordinate. As shown in FIGS. 1 and 2, when the oscillation signal LO+ is positive, the FETs 32 and 34 are turned on and the FETs 36 and 38 are turned off. Therefore, almost the input signal IF+ is output as the output signal RF+, and almost the input signal IF− is output as the output signal RF−. When the oscillation signal LO+ is negative, the FETs 32 and 34 turn off and the FETs 36 and 38 turn on. Therefore, almost the input signal IF- is output as the output signal RF+, and almost the input signal IF+ is output as the output signal RF-. As a result, signals obtained by mixing the oscillation signals LO+ and LO- and the input signals IF+ and IF- are output as the output signals RF+ and RF-.

The conversion gain of the ring mixer according to Comparative Example 1 was simulated. The simulation conditions are as follows.
FET: InGaAs channel layer/AlGaAs electron supply layer HEMT (High Electron Mobility Transistor), gate width 80 μm
Oscillation signal: LO (Local Oscillation) signal Frequency 70 GHz to 82 GHz
Input signal: IF (Intermediate Frequency) signal, frequency 3 GHz, power -20 dBm
Output signal: RF (Radio Frequency) signal

FIG. 3 is a diagram showing the conversion gain with respect to the frequency in Comparative Example 1. The frequency is the frequency of the oscillating signal and the conversion gain is the gain of the output signal with respect to the input signal. The solid line is the conversion gain of the output signal RF+ with respect to the input signal IF+, and the broken line is the conversion gain of the output signal RF- with respect to the input signal IF-. The conversion gain is as small as -10.5 dB to -12.2 dB in the frequency range of 70 GHz to 82 GHz.

The reason why the conversion gain is low in Comparative Example 1 will be described. FIG. 4A to FIG. 4D are equivalent circuit diagrams showing the line 22. As shown in FIG. 4A, a FET 32 is provided on the line 22. When the FET 32 is on, a high frequency signal is transmitted between the nodes N6 and N8 via the line 22. As shown in FIG. 4B, when the FET 32 is turned off, the line 22 should be cut off and no high frequency signal should be transmitted to the line 22.

However, as shown in FIG. 4C, in the actual line 22, the distributed constant line L0 is connected as a transmission line between the FET 32 and the nodes N6 and N8. As shown in FIG. 4D, when the FET 32 is turned off, the distributed constant line L0 becomes an open stub. Therefore, the line 22 is not ideally turned off depending on the length of the distributed constant line L0 and the like, and the conversion gain is reduced.

FIG. 5 is a circuit diagram of the ring mixer according to the first embodiment. As shown in FIG. 5, in ring mixer 100, lines 22, 24 are respectively provided between nodes N6 and N8, between nodes N7 and N9, between nodes N6 and N9, and between nodes N7 and N8. , 26 and 28 are connected in series. In this way, the lines 22 to 28 are connected in a ring shape. The lines 22 to 28 are provided with a pair of distributed constant lines L1 to L4, respectively. Nodes between the pair of distributed constant lines L1 to L4 are nodes N1 to N4. The nodes N6 to N9 are connected to the output terminals RF1 and RF2 and the oscillation terminals LO1 and LO2, respectively. The FETs 12 to 18 have their sources connected to the ground and their drains connected to the nodes N1 to N4, respectively. The gates of the FETs 12 and 14 are connected to the input terminal IF1 and the gates of the FETs 16 and 18 are connected to the input terminal IF2.

The oscillation signals LO+ and LO- are balanced oscillation signals and have almost opposite phases. The input signals IF+ and IF- are balanced input signals and are approximately out of phase with each other. The output signals RF+ and RF- are balanced output signals and are approximately in opposite phase to each other. The FETs 12 to 18 are turned on when a voltage (for example, a positive voltage in FIG. 2) higher than the median of the maximum amplitudes of the input signals IF+ and IF− (for example, 0V in FIG. 2) is input to the gates, and a low voltage (for example, in FIG. 2). It turns off when a negative voltage is input. For example, the pinch-off voltage of the FETs 12 to 18 is set to the gate as the median of the maximum amplitudes of the input signals IF+ and IF-.

In FIG. 5, the solid line shows the signal flow when the FETs 12 and 14 are off and the FETs 16 and 18 are on. The broken line shows the signal flow when the FETs 12 and 14 are on and the FETs 16 and 18 are off. The thick line shows the flow of the oscillation signal LO+, and the thin line shows the flow of the oscillation signal LO-. As shown in FIGS. 2 and 5, when the input signal IF+ is negative, the FETs 12 and 14 turn off and the FETs 16 and 18 turn on. Therefore, the oscillation signal LO+ is output as the output signal RF+, and the oscillation signal LO− is output as the output signal RF−. When the input signal IF+ is positive, FETs 12 and 14 turn on and FETs 16 and 18 turn off. Therefore, the oscillation signal LO- is output as the output signal RF+, and the oscillation signal LO+ is output as the output signal RF-. As a result, signals obtained by mixing the oscillation signals LO+ and LO- and the input signals IF+ and IF- are output as the output signals RF+ and RF-.

FIG. 6A to FIG. 6D are equivalent circuit diagrams showing the line 22. As shown in FIG. 6A, the FET 12 is connected between the node N1 in the line 22 and the ground. When the FET 12 is off, a high frequency signal is transmitted between the nodes N6 and N8 via the line 22. As shown in FIG. 6B, when the FET 12 is turned on, the line 22 is grounded. As shown in FIG. 6C, the distributed constant line L1 is connected between the nodes N1 and N6 and between the nodes N1 and N8. The distributed constant line L1 has a length of λ/4, for example. When the FET 12 is off, the distributed constant line L1 functions as a transmission line. Therefore, the high frequency signal is transmitted through the line 22. As shown in FIG. 4D, the node N1 is grounded when the FET 12 is on. The distributed constant line L1 is a short stub having a length of λ/4. Thus, looking at N1 from nodes N6 and N8 appears open. In this way, an ideal open can be established between the nodes N6 and N8. Considering the parasitic capacitance of the FET 12 and the like, the length of the distributed constant line L1 is slightly shorter than λ/4.

The conversion gain of the ring mixer according to the first embodiment was simulated. The simulation conditions are as follows.
FET: InGaAs channel layer/AlGaAs electron supply layer HEMT, gate width 80 μm
Distributed constant line: length 220μm, width 10μm
Oscillation signal: LO signal Frequency 70 GHz to 82 GHz
Input signal: IF signal Frequency 1 GHz
Output signal: RF signal

FIG. 7 is a diagram showing conversion gain with respect to frequency in the first embodiment. The frequency is the frequency of the oscillating signal and the conversion gain is the gain of the output signal with respect to the input signal. The solid line is the conversion gain of the output signal RF+ with respect to the input signal IF+, and the broken line is the conversion gain of the output signal RF- with respect to the input signal IF-. The power of the input signal is -20 dBm. When the frequency is 70 GHz to 82 GHz, the conversion gain is -1.5 dB to -2.2 dB, which is improved by about 10 dB as compared with FIG. 3 of Comparative Example 1.

FIG. 8 is a diagram showing the conversion gain with respect to the power of the input signal in the first embodiment. The frequency of the oscillation signal is 76 GHz. As shown in FIG. 8, the conversion gain increases as the IF power increases. When the IF power is -20 dBm or less, the conversion gain is constant and has good linearity.

FIG. 9 is a diagram showing the conversion phase with respect to the power of the input signal in the first embodiment. The frequency of the oscillation signal is 76 GHz. As shown in FIG. 9, when the IF power is −10 dBm or less, the conversion phase is constant and has good linearity.

According to the first embodiment, each of the four lines 22 to 28 has a pair of distributed constant lines L1 to L4 connected in series and connected in a ring shape. The nodes N6 to N9 are provided between adjacent lines of the four lines 22 to 28. Oscillation signals LO+ and LO- are input to opposing nodes N8 and N9, and output signals RF+ and RF- are output from the remaining opposing nodes N6 and N7. The drains of the FETs 12 to 18 are connected to the nodes N1 to N4 between the pair of distributed constant lines L1 to L4, respectively, the reference potential (eg, ground potential) is supplied to the sources, and the input signals IF+ and IF− are input to the gates.

Thus, when the FETs 12 to 18 are turned on, the distributed constant lines L1 to L4 become short stubs, and the distributed constant lines L1 to L4 can be opened when the nodes N6 to N9 are viewed. Therefore, the lines 22 to 28 can be cut off. Therefore, the conversion gain from the input signals IF+ and IF- to the output signals RF+ and RF- can be improved.

Further, the input signal IF+ (one of the balanced input signals) is input to the gates of the FETs 12 and 14 facing each other, and the input signal IF− (the other of the balanced input terminals) is input to the gates of the remaining FETs 16 and 18 facing the other. Oscillation signal LO+ (one of balanced oscillation signals) is input to one node N8 of opposing nodes N8 and N9, and oscillation signal LO− (the other of balanced oscillation signals) is input to the other node N9. The output signal RF+ (one of the balanced output signals) is output from one node N6 of the remaining opposing nodes N6 and N7, and the output signal RF- (the other of the balanced output signals) is output from the other node N7.

As a result, as shown in FIG. 5, the balanced oscillation signals LO+ and LO- and the balanced input signals IF+ and IF- can be mixed to output the balanced output signals RF+ and RF-. The oscillation signals LO+ and LO−, the input signals IF+ and IF−, and the output signals RF+ and RF− have opposite phases. It suffices that these phase differences have opposite phases within the range of functioning as a ring mixer.

Further, the pair of distributed constant lines L1 to L4 in the lines 22 to 28 have an electrical length of ⅛ or more and 3/8 or less of the wavelengths of the oscillation signals LO+ and LO−. Thereby, when the FETs 12 to 18 are turned on, the distributed constant lines L1 to L4 functioning as short stubs can be ideally opened when viewed from the nodes N6 to N9. Therefore, the lines 22 to 28 can be shut off in a state closer to the ideal. Therefore, the conversion gain from the input signals IF+ and IF− to the output signals RF+ and RF− can be further improved.

It is more preferable that the distributed constant lines L1 to L4 have an electrical length of 3/16 or more and 5/16 or less of the wavelengths of the oscillation signals LO+ and LO-. Furthermore, it is more preferable that the distributed constant lines L1 to L4 have an electrical length of ¼ of the wavelength of the oscillation signals LO+ and LO−. This allows the lines 22 to 28 to be cut off more ideally when the FETs 12 to 18 are turned on.

Although the input signals IF+ and IF− have a frequency lower than that of the output signals RF+ and RF− (that is, an example of up-converting), the input signals IF+ and IF− have a higher frequency than the output signals RF+ and RF− ( That is, even down-covert).

The lines 22 to 28 preferably operate in the same manner. Therefore, it is preferable that the distributed constant lines L1 to L4 have substantially the same electrical length. Further, it is preferable that the FETs 12 to 18 have substantially the same size (eg, gate width). It is preferable that the FETs 12 to 18 have substantially the same characteristics (eg, pinch-off voltage). The term “substantially the same” means that they are the same as long as they function as a ring mixer. For example, it may be the same within a range including a manufacturing error.

In order to shorten the distributed constant line, the frequencies of the oscillation signals LO+ and LO- are preferably 10 GHz or higher, more preferably 30 GHz or higher. The frequencies of the oscillation signals LO+ and LO- are preferably 100 GHz or less.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above meaning but by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

12, 14, 16, 18, 32, 34, 36, 38 FET
22, 24, 26, 28 Line IF1, IF2 Input terminal LO1, LO2 Oscillation terminal RF1, RF2 Output terminal IF+, IF- Input signal LO+, LO- Oscillation signal RF+, RF- Output signal L1, L2, L3, L4 Distributed constant Line N1, N2, N3, N4, N6, N7, N8, N9 nodes

Claims (3)

A first input terminal and a second input terminal for inputting mutually balanced input signals;
A third input terminal and a fourth input terminal to which mutually balanced oscillation signals are input ;
A first output terminal and a second output terminal,
A first distributed constant line having one end connected to the first output terminal and the other end connected to a first node;
A second distributed constant line having one end connected to the third input terminal and the other end connected to the first node;
A third distributed constant line having one end connected to the second output terminal and the other end connected to the second node;
A fourth distributed constant line having one end connected to the fourth input terminal and the other end connected to the second node;
A fifth distributed constant line having one end connected to the first output terminal and the other end connected to a third node;
A sixth distributed constant line having one end connected to the fourth input terminal and the other end connected to the third node;
A seventh distributed constant line having one end connected to the second output terminal and the other end connected to a fourth node;
An eighth distributed constant line having one end connected to the third input terminal and the other end connected to the fourth node;
A first FET having a gate connected to the first input terminal, a drain connected to the first node, and a source grounded ;
A second FET having a gate connected to the first input terminal, a drain connected to the second node, and a source grounded;
A third FET having a gate connected to the second input terminal, a drain connected to the third node, and a source grounded;
A fourth FET having a gate connected to the second input terminal, a drain connected to the fourth node, and a source grounded;
Equipped with,
The first distributed constant line, the second distributed constant line, the third distributed constant line, the fourth distributed constant line, the fifth distributed constant line, the sixth distributed constant line, the 7. The ring mixer according to claim 7, wherein the electrical lengths of the distributed constant line 7 and the eighth distributed constant line are respectively 1/8 or more and 3/8 or less of the wavelength of the oscillation signal . The first distributed constant line, the second distributed constant line, the third distributed constant line, the fourth distributed constant line, the fifth distributed constant line, the sixth distributed constant line, the The ring mixer according to claim 1, wherein the electrical lengths of the distributed constant line 7 and the eighth distributed constant line are respectively 3/16 or more and 5/16 or less of the wavelength of the oscillation signal . 3. The ring mixer according to claim 1, wherein the first output terminal and the second output terminal output mutually balanced output signals obtained by mixing the oscillation signal with the input signal .

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