JP6693885B2 - Semiconductor device - Google Patents

Description

One embodiment of the present invention relates to a semiconductor device, a circuit board, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture or composition (composition of matter). Alternatively, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an imaging device, a driving method thereof, or a manufacturing method thereof.

In a semiconductor device such as an integrated circuit (IC) or a display device, a pull-up (or pull-down) resistor is used to prevent the input / output terminals of the circuit from becoming indefinite. For example, a technique of using gate polysilicon as a pull-up (or pull-down) resistor of a CMOS inverter is disclosed (see Patent Document 1).

JP, 11-274440, A

For example, in a CMOS circuit, the resistance value of the pull-up (or pull-down) resistor may be very large, from several kilo Ω to several mega Ω. As described in the above-mentioned Patent Document 1, when polysilicon is used as a resistor in a gate array semiconductor circuit device, the area occupied by polysilicon becomes large, which causes a problem of increasing the cell size.

Further, in an IC having a pull-up (or pull-down) resistance, a current of about several μA always continues to flow while a signal is being input / output to / from an input / output terminal, which causes a problem of increasing power consumption.

Further, the IC having the pull-up (or pull-down) resistance as described above consumes a large amount of power. Therefore, in order to suppress the power consumption and make the IC lower in power consumption, a switch may be provided to disconnect the pull-up (or pull-down) resistor after the IC starts stable operation. Although the switch can be formed mainly by a transistor, even if the transistor is turned off and the switch is disconnected, an off-leakage current flows, so that power consumption is increased.

Therefore, it is an object of one embodiment of the present invention to provide a novel semiconductor device, a circuit board, or an electronic device. Another object of one embodiment of the present invention is to reduce a layout area or to provide a structure capable of realizing the reduction. Alternatively, it is an object of one embodiment of the present invention to prevent steady generation of current or provide a structure capable of realizing the same. Another object of one embodiment of the present invention is to reduce power consumption or to provide a structure capable of realizing the reduction. Alternatively, it is an object of one embodiment of the present invention to reduce the time during which a shoot-through current occurs or to provide a structure capable of realizing the same.

Note that one embodiment of the present invention does not necessarily need to solve all of the above problems and may be at least one of the above problems. Further, the above description of the problems does not prevent the existence of other problems. Problems other than these are obvious from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. ..

One embodiment of the present invention includes an internal circuit, an input / output terminal, a signal line, a power supply line, a resistor portion, a first transistor, and a control signal generation circuit, and the internal circuit is a signal line. Is electrically connected to the input / output terminal through the first transistor, the first terminal of the first transistor is electrically connected to the power supply line, and the second terminal of the first transistor is connected to the first terminal of the resistor portion. The second terminal of the resistance section is electrically connected to the terminal, the second terminal of the resistance section is electrically connected to the signal line, and the control signal generation circuit is electrically connected to the gate of the first transistor. The transistor is a semiconductor device including an oxide semiconductor.

One embodiment of the present invention includes an internal circuit, an input / output terminal, a signal line, a power supply line, a resistor portion, a first transistor, and a control signal generation circuit, and the internal circuit is a signal line. Electrically connected to the input / output terminal through the first transistor, the first terminal of the first transistor is electrically connected to the second terminal of the resistor portion, and the second terminal of the first transistor is connected to the signal terminal. The control circuit is electrically connected to the line, the first terminal of the resistance section is electrically connected to the power supply line, and the control signal generation circuit is electrically connected to the gate of the first transistor. The transistor is a semiconductor device including an oxide semiconductor.

One embodiment of the present invention includes an internal circuit, an input / output terminal, a signal line, a power supply line, a first transistor, and a control signal generation circuit, and the internal circuit is connected through the signal line. The first terminal of the first transistor is electrically connected to the output terminal, the first terminal of the first transistor is electrically connected to the power line, and the second terminal of the first transistor is electrically connected to the signal line. The signal generation circuit is electrically connected to the gate of the first transistor, and the first transistor is a semiconductor device including an oxide semiconductor.

Further, one embodiment of the present invention includes the semiconductor device described above and a second transistor, and the control signal generation circuit is electrically connected to a first terminal of the second transistor. The second terminal of the transistor is electrically connected to the gate of the first transistor, and the second transistor is a semiconductor device including an oxide semiconductor.

Further, one embodiment of the present invention includes the above-described semiconductor device and a capacitor, and the capacitor is electrically connected to a second terminal of the second transistor and a gate of the first transistor. It is a semiconductor device.

Further, the control signal generation circuit and the gate of the second transistor may be electrically connected. Further, the gate of the second transistor may be connected to another wiring.

Further, one embodiment of the present invention is a circuit board including the semiconductor device described above and a printed board.

Further, one embodiment of the present invention is an electronic device including the semiconductor device described above or the circuit board described above, and a display portion, a microphone, a speaker, or an operation key.

Note that in this specification and the like, the resistor portion is preferably a layer including an oxide semiconductor as a resistor.

One embodiment of the present invention can provide a novel semiconductor device, a circuit board, or an electronic device. Alternatively, according to one embodiment of the present invention, a layout area can be reduced or a structure capable of realizing the same can be provided. Alternatively, one embodiment of the present invention can provide a structure capable of preventing or realizing a steady current flow. Alternatively, according to one embodiment of the present invention, power consumption can be reduced or a structure capable of achieving the power consumption can be provided. Alternatively, one embodiment of the present invention can provide a structure in which the time during which a shoot-through current occurs can be shortened or can be realized.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have to have all of these effects. It should be noted that the effects other than these are naturally apparent from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the description of the specification, drawings, claims, etc. Is.

FIG. 6 illustrates an example of a semiconductor device. FIG. 6 illustrates an example of a semiconductor device. FIG. 6 illustrates an example of a semiconductor device. FIG. 6 illustrates an example of a semiconductor device. Timing chart. FIG. 6 illustrates an example of a semiconductor device. FIG. 6 illustrates an example of a semiconductor device. FIG. 6 illustrates an example of a semiconductor device. FIG. 6 illustrates an example of a semiconductor device. 7A to 7C each illustrate an example of a structure of a transistor. 7A to 7C each illustrate an example of a structure of a transistor. 7A to 7C each illustrate an example of a structure of a transistor. 7A to 7C each illustrate an example of a structure of a transistor. 7A to 7C each illustrate an example of a structure of a transistor. 7A to 7C each illustrate an example of a structure of a transistor. 7A to 7C each illustrate an example of a structure of a transistor. 6A and 6B each illustrate an energy band diagram of a transistor. FIG. 6 illustrates an example of a semiconductor device. The flowchart figure and perspective perspective view which show the manufacturing process of an electronic component. 7A to 7C each illustrate an electronic device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description of the embodiments below, and it is easily understood by those skilled in the art that modes and details thereof can be variously modified without departing from the spirit and scope of the present invention. To be done. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity.

Note that in this specification, the notation “film” and the notation “layer” can be interchanged with each other.

Further, the voltage often indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Therefore, the voltage can be restated as the potential. Generally, the potential (voltage) is relative and is determined by the relative magnitude from the reference potential. Therefore, even if it is described as "ground potential" or the like, the potential is not always 0V. For example, the lowest potential in the circuit may be the “ground potential”. Alternatively, an intermediate potential in the circuit may be the “ground potential”. In that case, a positive potential and a negative potential are defined with reference to the potential.

Further, in this specification and the like, the high power supply potential VDD (hereinafter, also simply referred to as “VDD” or “H potential”) is also referred to as the low power supply potential VSS (hereinafter, simply referred to as “VSS” or “L potential”). ) Is higher than the power supply potential. The low power supply potential VSS indicates a power supply potential lower than the high power supply potential VDD. Further, the ground potential can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is lower than the ground potential, and when VSS is the ground potential, VDD is higher than the ground potential.

Note that the ordinal numbers given as the first and second are used for convenience and do not indicate the order of steps or the order of stacking. Therefore, for example, “first” can be replaced with “second” or “third” as appropriate. In addition, the ordinal numbers described in this specification and the like may be different from the ordinal numbers used to specify one embodiment of the present invention.

Further, one embodiment of the present invention includes, in addition to an integrated circuit, any device including a display device, an RF tag, and an imaging device in its category. In addition, the display device includes a liquid crystal display device, a light emitting device including a light emitting element represented by an organic light emitting element in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), and FED (Field Emission). A display device having an integrated circuit such as a display is included in the category.

In describing the structure of the invention with reference to the drawings, the same reference numerals may be commonly used in different drawings.

Further, in this specification and the like, in a diagram or a text described in one embodiment, part of the diagram or the text can be taken out to form one embodiment of the invention. Therefore, in the case where a diagram or a sentence which describes a certain portion is described, the extracted content of the diagram or the sentence of the part is also disclosed as one embodiment of the invention and may constitute one embodiment of the invention. It shall be possible. And it can be said that one aspect of the invention is clear. Therefore, for example, a drawing or text in which an active element (such as a transistor), a wiring, a passive element (such as a capacitive element), a conductive layer, an insulating layer, a semiconductor layer, a component, a device, an operating method, or a manufacturing method is described in single or plural. In, it is possible to form a part of the invention by taking out a part thereof. For example, from a circuit diagram including N (N is an integer) circuit elements (transistors, capacitive elements, etc.), M (M is an integer, M <N) circuit elements (transistors, capacitive elements) It is possible to form one embodiment of the invention by extracting As another example, some elements are arbitrarily extracted from the sentence that "A has B, C, D, E, or F", and "A has B and E." "," A has E and F, "" A has C, E, and F, "or" A has B, C, D, and E. " It is possible to configure aspects.

Further, in this specification and the like, in the case where at least one specific example is described in a diagram or a text described in one embodiment, it is easy for those skilled in the art to derive a superordinate concept of the specific example. Be understood by Therefore, when at least one specific example is described in a diagram or a text described in one embodiment, a super concept of the specific example is also disclosed as one aspect of the invention. Aspects can be configured. And it can be said that one aspect of the invention is clear.

Further, in this specification and the like, at least the contents illustrated in the drawings (which may be part of the drawings) are disclosed as one embodiment of the invention and can constitute one embodiment of the invention. Is. Therefore, as long as some content is described in the drawings, the content is disclosed as one embodiment of the invention and does not constitute one embodiment of the invention even if the content is not described using text. It is possible. Similarly, a drawing obtained by extracting a part of the drawing is also disclosed as one embodiment of the invention, and one embodiment of the invention can be configured. And it can be said that one aspect of the invention is clear.

Further, it is possible to form an aspect of the invention in which the content not specified in the text or drawings in the specification is excluded. Alternatively, if a numerical range indicated by the upper limit value and the lower limit value, etc. is stated for a certain value, the range can be made narrower by arbitrarily narrowing the range or by excluding one point in the range. One aspect of the excluded invention can be specified. From these, for example, it can be defined that the related art does not fall within the technical scope of one aspect of the present invention.

Further, in this specification and the like, a person skilled in the art would not have to specify the connection destinations of all terminals of active elements (transistors or the like), passive elements (capacitance elements, or the like), and one skilled in the art would appreciate that It may be possible to configure aspects. That is, it can be said that one embodiment of the invention is clear without specifying a connection destination. When the content in which the connection destination is specified is described in this specification or the like, it is possible to determine that one aspect of the invention that does not specify the connection destination is described in this specification or the like There is. In particular, when there are a plurality of candidates for the connection destination of the terminal, it is not necessary to limit the connection destination of the terminal to a specific location. Therefore, in some cases, one embodiment of the invention can be formed by specifying the connection destinations of only some terminals of active elements (such as transistors) and passive elements (such as capacitors).

Further, in this specification and the like, it may be possible for those skilled in the art to specify the invention by specifying at least the connection destination of a certain circuit. Alternatively, it may be possible for those skilled in the art to specify the invention by specifying at least the function of a certain circuit. That is, it can be said that one aspect of the invention is clear when the function is specified. In some cases, it may be possible to determine that one aspect of the invention in which the function is specified is described in this specification and the like. Therefore, even if the function of a certain circuit is not specified, if the connection destination is specified, the circuit is disclosed as one embodiment of the invention, and one embodiment of the invention can be configured. Alternatively, if a function of a circuit is specified without specifying a connection destination, the circuit is disclosed as one embodiment of the invention, and one embodiment of the invention can be formed.

Further, in this specification and the like, when it is explicitly described that X and Y are connected, a case where X and Y are electrically connected and a case where X and Y function The case where they are electrically connected and the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relation, for example, the connection relation shown in the drawing or the text, and other than the connection relation shown in the drawing or the text is also described in the drawing or the text.

Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is given. Elements (light emitting elements, loads, etc.) are not connected between X and Y, and elements (eg, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y , Resistor element, diode, display element, light emitting element, load, etc.) and X and Y are connected.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display, etc.) that enables the X and Y to be electrically connected. Element, light emitting element, load, etc.) can be connected between X and Y one or more. The switch has a function of controlling on / off. That is, the switch is in a conducting state (on state) or a non-conducting state (off state) and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

Examples of the case where X and Y are functionally connected include a circuit (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.)) that enables functional connection between X and Y, and signal conversion. Circuits (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (step-up circuit, step-down circuit, etc.), level shifter circuit for changing signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc. It is possible to connect more than one in between. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. To do. In addition, when X and Y are functionally connected, the case where X and Y are directly connected and the case where X and Y are electrically connected are included.

In addition, when it is explicitly described that X and Y are electrically connected, when X and Y are electrically connected (that is, when X and Y are separately connected, Element or another circuit is sandwiched between them and X and Y are functionally connected (that is, another circuit is sandwiched between X and Y and functionally connected). And a case where X and Y are directly connected (that is, a case where another element or another circuit is connected between X and Y is not provided). It is assumed to be disclosed in a written document. That is, when explicitly described as being electrically connected, the same content as the case where only explicitly described as being connected is disclosed in this specification and the like. It has been done.

Note that, for example, the source (or the first terminal or the like) of the transistor is electrically connected to X through (or not) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Via (or without) electrically connecting to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1 and another part of Z1 Is directly connected to X, the drain (or the second terminal, etc.) of the transistor is directly connected to part of Z2, and another part of Z2 is directly connected to Y. , Can be expressed as follows.

For example, “X and Y, the source (or the first terminal or the like) of the transistor, and the drain (or the second terminal or the like) are electrically connected to each other, and X, the source (or the first terminal) of the transistor, or the like. Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order. ” Or “the source of the transistor (or the first terminal or the like) is electrically connected to X, the drain of the transistor (or the second terminal or the like) is electrically connected to Y, and X, the source of the transistor (or the like). Alternatively, the first terminal or the like), the drain of the transistor (or the second terminal, or the like), and Y are electrically connected in this order ”. Alternatively, “X is electrically connected to Y through a source (or a first terminal or the like) and a drain (or a second terminal or the like) of the transistor, and X, a source (or a first terminal) of the transistor, or the like. Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order ”. The source (or the first terminal or the like) of the transistor and the drain (or the second terminal or the like) are separated from each other by defining the order of connection in the circuit structure using the expression method similar to these examples. Apart from this, the technical scope can be determined.

Alternatively, as another expression method, for example, “the source of the transistor (or the first terminal or the like) is electrically connected to X through at least the first connection path, and the first connection path is The second connection path does not have two connection paths, and the second connection path is between the transistor source (or the first terminal or the like) and the transistor drain (or the second terminal or the like) through the transistor. And a first connection path is a path via Z1, and a drain (or a second terminal or the like) of the transistor is electrically connected to Y via at least a third connection path, The third connection route does not have the second connection route, and the third connection route is a route via Z2. ” Alternatively, "the source (or the first terminal or the like) of the transistor is electrically connected to X via at least the first connection path via Z1, and the first connection path is connected to the second connection path. The second connection path does not have, and the second connection path has a connection path through the transistor, and the drain (or the second terminal or the like) of the transistor has at least the third connection path, through Z2, and Y. And the third connection path does not have the second connection path. ” Or “the source of the transistor (or the first terminal or the like) is electrically connected to X via at least the first electrical path via Z1, and the first electrical path is connected to the second electrical path. The second electrical path is an electrical path from the source (or the first terminal or the like) of the transistor to the drain (or the second terminal or the like) of the transistor, The drain (or the second terminal or the like) is electrically connected to Y through at least a third electrical path via Z2, and the third electrical path has a fourth electrical path. And the fourth electrical path is an electrical path from the drain of the transistor (or the second terminal or the like) to the source of the transistor (or the first terminal or the like). ” .. By defining the connection path in the circuit configuration using the expression method similar to these examples, the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor can be distinguished. , The technical scope can be determined.

Note that these expression methods are examples, and the present invention is not limited to these expression methods. Here, X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

In addition, even when independent components are illustrated as electrically connected to each other on the circuit diagram, when one component also has the functions of a plurality of components. There is also. For example, in the case where part of the wiring also functions as an electrode, one conductive film has both functions of a wiring and a function of an electrode. Therefore, the term “electrically connected” in this specification includes a category in which one conductive film also has a plurality of functions of components.

(Embodiment 1)
In this embodiment, an example of a semiconductor device according to one embodiment of the present invention will be described. A semiconductor device according to one embodiment of the present invention, in a circuit having an internal circuit and an input / output terminal for inputting / outputting a signal to / from the internal circuit, has a pull-out for preventing the input / output terminal of the circuit from entering an undefined state. It is a circuit with up (or pull down) resistance.

<Example of configuration of semiconductor device>
FIG. 1A is a circuit diagram of a semiconductor device 10 according to one embodiment of the present invention. A semiconductor device 10 illustrated in FIG. 1A includes a transistor 11, a resistor portion 12, an input / output terminal 13, an internal circuit 14, a power supply line 15, a signal line 16, and a control signal generation circuit 17. Have.

In the semiconductor device 10, the first terminal of the transistor 11 is connected to the power supply line 15, and the second terminal of the transistor 11 is connected to the first terminal of the resistance section 12. The gate of the transistor 11 is connected to the control signal generation circuit 17. The second terminal of the resistance portion 12 is connected to the signal line 16, and the input / output terminal 13 is connected to the internal circuit 14 via the signal line 16.

The input / output terminal 13 is a terminal for inputting a signal (high level signal, low level signal or analog signal) to the internal circuit 14 or outputting a signal (high level signal, low level signal or analog signal) from the internal circuit 14. is there. The control signal generation circuit 17 is a circuit that sends a signal to the gate of the transistor 11 to control the on / off state of the transistor 11.

The power supply line 15 can be a high potential power supply line VDD that gives a high level (H) potential or a low potential power supply line VSS (VSS <VDD) that gives a low level (L) potential. When the power supply line 15 is VDD, the resistance section 12 in the semiconductor device 10 functions as a pull-up resistance. When the power supply line 15 is VSS, the resistance section 12 in the semiconductor device 10 functions as a pull-down resistance.

Without a pull-up (or pull-down) resistor, when no circuit or load device is connected to the input / output terminal 13 from the outside, or when no signal is input / output to the input / output terminal 13, The input / output terminal 13 is in an undefined state (a state that is neither H nor L., or an unknown state of H or L). If the input / output terminal 13 becomes indefinite, the internal circuit 14 may malfunction.

Therefore, by providing a pull-up (or pull-down) resistor as shown in FIG. 1A, the input / output terminal 13 can be fixed at H or L, and thereby malfunction of the internal circuit can be prevented.

The transistor 11 is on when a signal (high level signal, low level signal or analog signal) is not input to or output from the input / output terminal 13. Therefore, when the power supply line 15 is VDD and the signal is not input to the input / output terminal 13, the input / output terminal is held at the high level. When the power supply line 15 is VSS and the signal is not input / output to / from the input / output terminal 13, the input / output terminal is held at the low level.

The transistor 11 is turned off after a signal (high level signal, low level signal or analog signal) is input to the input / output terminal 13 and the internal circuit 14 is normally activated. Thereby, it is possible to stop the current from flowing between the power supply line 15 and the signal line 16. Therefore, it is possible to prevent the resistor unit 12 from constantly consuming current and reduce the power consumption of the semiconductor device 10.

The transistor 11 and the resistance portion 12 include an oxide semiconductor. The oxide semiconductor is a wide-gap semiconductor, and the effective mass of holes is very large. Further, the carrier concentration of the oxide semiconductor can be reduced by reducing impurities contained in the oxide semiconductor as much as possible and further reducing oxygen vacancies. By using such a highly purified intrinsic oxide semiconductor for a transistor, a transistor with extremely low off-state current can be formed. Thus, by using an oxide semiconductor for the transistor 11, power consumption of the semiconductor device 10 can be reduced. Further, when used as the resistance portion 12, the oxide semiconductor as described above has a very high resistance, and therefore, when used as the resistance portion, the area for achieving the required resistance value becomes small. That is, by using an oxide semiconductor for the resistor portion 12, the layout area of the resistor portion 12 can be reduced.

In addition, a transistor and a resistor portion including an oxide semiconductor can easily have a stacked structure. For example, it can be formed by stacking with a transistor or the like using silicon. Therefore, for example, like the semiconductor device 10 according to one embodiment of the present invention, the transistor 11 and the resistor portion 12 are formed using an oxide semiconductor, and the internal circuit 14 is formed using a transistor including silicon or the like. Since the transistor 11 and the resistor portion 12 and the internal circuit 14 can be formed by being stacked, the layout area can be reduced. Further, the transistor 11 and the resistance portion 12 may be formed by stacking.

Further, a resistance portion including an oxide semiconductor functioning as a resistance layer and a conductive layer in contact with the oxide semiconductor might have a non-linear resistance.

FIG. 1B is a circuit diagram of the semiconductor device 20 according to one embodiment of the present invention. The semiconductor device 20 has a configuration in which the transistor 11 and the resistance portion 12 in the semiconductor device 10 shown in FIG. The semiconductor device 20 includes a transistor 21, a resistance section 22, an input / output terminal 23, an internal circuit 24, a power supply line 25, a signal line 26, and a control signal generation circuit 27.

In the semiconductor device 20, the first terminal of the transistor 21 is connected to the second terminal of the resistor portion 22, and the second terminal of the transistor 21 is connected to the signal line 26. The gate of the transistor 21 is connected to the control signal generation circuit 27. The first terminal of the resistor portion 22 is connected to the power supply line 25, and the input / output terminal 23 is connected to the internal circuit 24 via the signal line 26.

FIG. 1C is a circuit diagram of the semiconductor device 30 according to one embodiment of the present invention. The semiconductor device 30 includes a transistor 31, an input / output terminal 33, an internal circuit 34, a power supply line 35, a signal line 36, and a control signal generation circuit 37.

The semiconductor device 30 has a configuration in which the resistance portion 12 is not provided in the semiconductor device 10 of FIG. That is, the semiconductor device 30 in FIG. 1C has only the transistor 31 between the power supply line 35 and the signal line 36.

In the semiconductor device 30, the first terminal of the transistor 31 is connected to the power supply line 35, and the second terminal of the transistor 31 is connected to the signal line 36. The gate of the transistor 31 is connected to the control signal generation circuit 37. The input / output terminal 33 is connected to the internal circuit 34 via the signal line 36.

Although the semiconductor device 30 has a configuration in which there is no resistance portion between the power supply line 35 and the signal line 36, the on-state channel resistance of the transistor 31 can be used as a substitute for the resistance portion and pull-up ( Or pull down) also functions as a resistor. In particular, it is preferable to use an oxide semiconductor for the transistor 31 because a high channel resistance can be easily formed and off-state current is extremely small.

FIG. 1D is a circuit diagram of the semiconductor device 40 according to one embodiment of the present invention. The semiconductor device 40 includes a resistance section 42, an input / output terminal 43, an internal circuit 44, a power supply line 45, and a signal line 46.

The semiconductor device 40 has a configuration in which the transistor 11 and the control signal generation circuit 17 are not provided in the semiconductor device 10 of FIG. That is, the semiconductor device 40 in FIG. 1D has only the resistance portion 42 between the power supply line 45 and the signal line 46.

In the semiconductor device 40, the first terminal of the resistance section 42 is connected to the power supply line 45, and the second terminal of the resistance section 42 is connected to the signal line 46. The input / output terminal 43 is connected to the internal circuit 44 via the signal line 46.

The semiconductor device 40 has no transistor between the power supply line 45 and the signal line 46. As described above, even if the transistor is not formed between the power supply line 45 and the signal line 46, it is possible to prevent the signal line 46 from entering an indefinite state because of the resistance portion 42. However, in that case, while the semiconductor device 40 is activated, a current constantly flows, so that the power consumption of the semiconductor device 40 increases, but the area for forming the transistor becomes unnecessary, The layout can be small.

Further, in the semiconductor device 10 illustrated in FIG. 1A, a plurality of transistors 11 and a plurality of resistor portions 12 can be used, respectively. For example, as in the semiconductor device 70 shown in FIG. 2A, a configuration using two resistance portions 12 may be used. It should be noted that the configuration may be such that three or more resistor portions 12 are used. Alternatively, as in the semiconductor device 80 illustrated in FIG. 2B, a structure including two transistors 11 may be used. Note that a structure including three or more transistors 11 may be used. Further, the transistor 11 and the resistance portion 12 do not have to be alternately connected, and the same structure may be continuously connected.

As an example of the internal circuit 14 in the semiconductor device 10 shown in FIG. 1A, a gate driver circuit as shown in FIG. 3A and a clock generator or the like as shown in FIG. 3B are used. it can. Further, not limited to these, various circuits can be used.

FIG. 4A is a circuit diagram of the semiconductor device 50 according to one embodiment of the present invention. The semiconductor device 50 has a configuration in which a transistor is further provided between the gate of the transistor 11 and the control signal generation circuit 17 in the configuration of the semiconductor device 10 of FIG.

The semiconductor device 50 includes a transistor 51, a resistor portion 52, an input / output terminal 53, an internal circuit 54, a power supply line 55, a signal line 56, a control signal generation circuit 57, and a transistor 58.

In the semiconductor device 50, the first terminal of the transistor 51 is connected to the power supply line 55, the second terminal of the transistor 51 is connected to the first terminal of the resistor section 52, and the second terminal of the resistor section 52 is connected to the signal line. Connected to line 56. The gate of the transistor 51 is connected to the first terminal of the transistor 58, and the second terminal of the transistor 58 is connected to the control signal generation circuit 57. The gate of the transistor 58 is connected to the control signal generation circuit 57. The input / output terminal 53 is connected to the internal circuit 54 via the signal line 56. Further, a floating node (FN) is formed at a connection portion between the gate of the transistor 51 and the first terminal of the transistor 58.

The transistor 58 has an oxide semiconductor similarly to the transistor 51 and the resistor portion 52. The off-state current of a transistor including an oxide semiconductor is extremely low. Therefore, in the semiconductor device 50, the voltage for operating the transistor 51 can be held in FN by switching the transistor 58 on and off. Therefore, the control signal generation circuit 57 can be stopped while the transistor 51 is kept on or off. With this configuration, the power consumption of the semiconductor device 50 can be reduced.

In the semiconductor device 50 illustrated in FIG. 4A, the gate of the transistor 58 is connected to the control signal generation circuit 57, but the gate of the transistor 58 may not be connected to the control signal generation circuit 57. Good. That is, the gate of the transistor 58 can be connected to another wiring or a circuit.

FIG. 4B is a circuit diagram of the semiconductor device 60 according to one embodiment of the present invention. The semiconductor device 60 has a configuration in which a capacitance element is further connected to a floating node formed at a connection portion between the gate of the transistor 51 and the transistor 58 in the configuration of the semiconductor device 50 of FIG.

The semiconductor device 60 includes a transistor 61, a resistor portion 62, an input / output terminal 63, an internal circuit 64, a power supply line 65, a signal line 66, a control signal generation circuit 67, a transistor 68, and a capacitance element 69. , With.

In the semiconductor device 60, the first terminal of the transistor 61 is connected to the power supply line 65, the second terminal of the transistor 61 is connected to the first terminal of the resistor section 62, and the second terminal of the resistor section 62 is connected to the signal line. It is connected to the line 66. The gate of the transistor 61 is connected to the first terminal of the transistor 68 and the capacitor 69, and the second terminal of the transistor 68 is connected to the control signal generation circuit 67. The gate of the transistor 68 is connected to the control signal generation circuit 67. The input / output terminal 63 is connected to the internal circuit 64 via the signal line 66. Further, a floating node (FN) is formed at a connection portion of the gate of the transistor 61, the first terminal of the transistor 68, and the capacitor 69.

Similarly to the semiconductor device 50, the semiconductor device 60 can hold the voltage for operating the transistor 61 in FN by switching the transistor 68 on and off. Further, the semiconductor device 60 has a configuration in which the capacitor 69 is connected to the FN, so that the voltage can be more easily held in the FN. Therefore, it becomes easier to maintain the on state or the off state of the transistor 61 and the control signal generation circuit 67 can be stopped, so that the power consumption of the semiconductor device 60 can be reduced.

Although the gate of the transistor 68 is connected to the control signal generation circuit 67 in the semiconductor device 60 illustrated in FIG. 4B, the gate of the transistor 68 may not be connected to the control signal generation circuit 67. Good. That is, the gate of the transistor 68 can be connected to another wiring or a circuit.

<Operation example of semiconductor device>
Next, operation in the case where the semiconductor device 10 illustrated in FIG. 1A is controlled based on the timing charts illustrated in FIGS. 5A and 5B will be described. However, the semiconductor device 10 illustrated in FIG. 1A can perform various other operations by appropriately controlling the potential of each wiring.

FIG. 5A is a timing chart illustrating the case where the power supply line 15 of the semiconductor device 10 in FIG. 1A functions as the high-potential power supply line VDD. That is, the resistance section 12 functions as a pull-up resistance.

FIG. 5A shows the potential V15 of the power supply line 15, the potential V17 of the control signal generation circuit 17, and the potential V13 of the input / output terminal 13.

In a period T11 illustrated in FIG. 5A, the potentials of the power supply line 15 and the control signal generation circuit 17 are gradually increased and boosted to the threshold voltage (Vth) of the transistor 11. Further, the potential of the input / output terminal 13 becomes indefinite because the transistor 11 is in the off state and is in the floating state.

In the period T12, the potentials of the power supply line 15 and the control signal generation circuit 17 are further increased and boosted to VDD (H). After that, the potentials of the power supply line 15 and the control signal generation circuit 17 are held at VDD (H). Further, the potential of the input / output terminal 13 becomes the same potential (VDD) as the power supply line 15 because the transistor 11 is turned on.

In the period T13, the potentials of the power supply line 15 and the control signal generation circuit 17 are held at VDD (H). A low level (L) signal (VSS) is input to the input / output terminal 13. That is, in the period T13, current flows through the transistor 11 and the resistor portion 12, so that the power consumption of the semiconductor device 10 increases. Therefore, it is preferable that the period T13 is short.

In the period T14, the potential of the power supply line 15 is held at VDD. A low level (L) signal (VSS) is input to the control signal generation circuit 17, and the transistor 11 is turned off. The potential of the input / output terminal 13 is held at VSS (L).

In the period T15, the potential of the power supply line 15 is held at VDD (H). A high level signal (VDD) is input to the control signal generation circuit 17, and the transistor 11 is turned on. The potential of the input / output terminal 13 is held at VSS (L). That is, in the period T15, current flows through the transistor 11 and the resistor portion 12, so that the power consumption of the semiconductor device 10 increases. Therefore, it is preferable that the period T15 is short.

In the period T16, the potentials of the power supply line 15 and the control signal generation circuit 17 are held at VDD. The potential of the input / output terminal 13 becomes VDD (H) because the input of the low level (L) signal is stopped.

FIG. 5B is a timing chart illustrating the case where the power supply line 15 of the semiconductor device 10 in FIG. 1A functions as the low potential power supply line VSS. That is, the resistance section 12 functions as a pull-down resistance.

FIG. 5B shows the potential V15 of the power supply line 15, the potential V17 of the control signal generation circuit 17, and the potential V13 of the input / output terminal 13.

In the period T21 shown in FIG. 5B, the power supply line 15 is held at VSS (L). The potential of the control signal generation circuit 17 gradually increases and is boosted to the threshold voltage (Vth) of the transistor 11. Further, the potential of the input / output terminal 13 is in a floating state because the transistor 11 is in the off state, and is in an undefined state.

In the period T22, the power supply line 15 is held at VSS (L). The potential of the control signal generation circuit 17 further increases and is boosted to VDD (H). After that, the potential of the control signal generation circuit 17 is held at VDD (H). Further, the potential of the input / output terminal 13 becomes the same potential (VSS) as the power supply line 15 because the transistor 11 is turned on.

In the period T23, the power supply line 15 is held at VSS (L). The potential of the control signal generation circuit 17 is held at VDD. A high level signal (VDD) is input to the input / output terminal 13. That is, in the period T23, current flows through the transistor 11 and the resistor portion 12, so that the power consumption of the semiconductor device 10 is increased. Therefore, it is preferable that the period T23 is short.

In the period T24, the power supply line 15 is held at VSS (L). A low level (L) signal (VSS) is input to the control signal generation circuit 17, and the transistor 11 is turned off. The potential of the input / output terminal 13 is held at VDD (H).

In the period T25, the power supply line 15 is held at VSS (L). A high level signal (VDD) is input to the control signal generation circuit 17, and the transistor 11 is turned on. The potential of the input / output terminal 13 is held at VDD (H). That is, in the period T25, current flows through the transistor 11 and the resistor portion 12, so that the power consumption of the semiconductor device 10 increases. Therefore, it is preferable that the period T25 is short.

In the period T26, the potential of the power supply line 15 is held at VSS (L). The potential of the control signal generation circuit 17 is held at VDD. The potential of the input / output terminal 13 becomes VSS (L) because the input of the high level (H) signal is stopped.

As described above, the semiconductor device 10 shown in FIG. 1 can function as a semiconductor device having a pull-up (or pull-down) resistance such as an IC.

Note that one embodiment of the present invention is described in this embodiment. Alternatively, one embodiment of the present invention will be described in another embodiment. However, one embodiment of the present invention is not limited to these. That is, in this embodiment and the other embodiments, various aspects of the invention are described; therefore, one aspect of the present invention is not limited to a particular aspect. For example, although an example in which a pull-up (or pull-down) resistor is applied is shown as one embodiment of the present invention, one embodiment of the present invention is not limited to this. In some cases or circumstances, one embodiment of the invention may be applied to other circuits. Or, for example, in some cases or circumstances, one aspect of the invention may not apply a pull-up (or pull-down) resistor. For example, although an example in which a transistor includes an oxide semiconductor is described as one embodiment of the present invention, one embodiment of the present invention is not limited to this. Optionally or optionally, in one aspect of the invention, the transistor comprises a material such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor. Thus, it may have various semiconductor materials. Alternatively, for example, in some cases or in some circumstances, the transistor may not include an oxide semiconductor in one embodiment of the present invention.

Note that this embodiment can be combined with any of the other embodiments as appropriate. Therefore, the content described in this embodiment (may be part of the content) is different from the content described in the embodiment (may be part of the content), and / or one or more other content. Application, combination, replacement, or the like can be performed with respect to the content (may be part of the content) described in the embodiment. Note that the content described in the embodiments means the content described using various drawings or the content described in the specification in each embodiment. In addition, a diagram (may be a part) described in one embodiment, another part of the diagram, another diagram (may be a part) described in the embodiment, and / or one or more. More drawings can be formed by combining the drawings (which may be a part) described in another embodiment of the above. This also applies to the following embodiments.

(Embodiment 2)
In this embodiment, a configuration example of the transistor 11 and the resistance portion 12 in the semiconductor device 10 described in Embodiment 1 will be described.

<Structure example 1>
FIG. 6 shows a circuit diagram, a top view, and a cross-sectional view of the transistor 100 and the resistor portion 200. Note that the transistor 100 can be used as the transistor 11 in FIG. In addition, the resistance portion 200 can be used as the resistance portion 12 in FIG. In addition, a structure in which the transistor 100 and the resistor portion 200 in this embodiment each include an oxide semiconductor will be described.

FIG. 6A shows a circuit diagram in which the transistor 100 and the resistance portion 200 are connected. A top view showing an example of the structure of the transistor 100 and the resistor portion 200 shown in FIG. 6A is shown in FIG. 6B. 6C is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 6A, FIG. 6D is a cross-sectional view taken along dashed-dotted line A3-A4, and FIG. 6E is a dashed-dotted line A5. -The sectional view in A6 is shown. Here, the direction of the alternate long and short dash line A1-A2 may be referred to as the channel length direction, and the direction of the alternate long and short dash line A3-A4 may be referred to as the channel width direction. Therefore, FIG. 6C is a diagram showing a cross-sectional structure of the transistor 100 in the channel length direction, and FIG. 6D is a diagram showing a cross-sectional structure of the transistor 100 in the channel width direction. Note that some components are omitted in FIG. 6B in order to clarify the device structure.

The transistor 100 illustrated in FIG. 6 includes a conductive layer 141 and a conductive layer 142 which are formed so as to be partly in contact with the insulating layer 112 over the substrate 110, the oxide semiconductor layer 120 over the insulating layer 112, and the oxide semiconductor layer 120. The insulating layer 113 over the oxide semiconductor layer 120, the conductive layer 141, and the conductive layer 142 overlaps with the oxide semiconductor layer 120, and the conductive layer 130 over the insulating layer 113 and the conductive layer 130 and over the insulating layer 113. And an insulating layer 115.

The resistance portion 200 illustrated in FIG. 6 includes an insulating layer 112 over the substrate 110, an oxide semiconductor layer 121 over the insulating layer 112, and a conductive layer 142 and a conductive layer which are formed in partial contact with the oxide semiconductor layer 121. The layer 143, the oxide semiconductor layer 121, the conductive layer 142, the insulating layer 113 over the conductive layer 143, and the insulating layer 115 over the insulating layer 113 are included.

In the transistor 100, the insulating layer 112 can function as a base insulating layer. The oxide semiconductor layer 120 can function as an active layer of the transistor 100. The conductive layers 141 and 142 can function as a source electrode and a drain electrode. The insulating layer 113 has a region functioning as a gate insulating layer. The conductive layer 130 can function as a gate electrode. The insulating layer 115 can function as an interlayer insulating layer.

Further, in the resistance portion 200, the oxide semiconductor layer 121 can function as a resistance layer.

<Structure example 2>
FIG. 7 shows a circuit diagram, a top view, and a cross-sectional view of the transistor and the resistor portion 101. Note that the transistor and resistor portion 101 can be used for the transistor 11 and the resistor portion 12 in FIG. Further, a structure in which the transistor and the resistor portion 101 in this embodiment includes an oxide semiconductor will be described.

The transistor and resistance unit 101 shown in FIG. 7 has a structure in which the transistor 100 and the resistance unit 200 in FIG. 6 are combined into one. In particular, by using the transistor including the oxide semiconductor and the resistor portion 101, the active layer of the transistor with low off-state current and the resistor layer with high resistance can be directly connected to each other. The layout area can be reduced by adopting such a configuration that the transistor and the resistance portion are combined.

FIG. 7A shows a circuit diagram of the transistor and the resistor portion 101. FIG. 7B is a top view showing an example of the structure of the transistor and the resistor portion 101 shown in FIG. 7A. 7C is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 7A, FIG. 7D is a cross-sectional view taken along dashed-dotted line A3-A4, and FIG. 7E is a dashed-dotted line A5. -The sectional view in A6 is shown. Note that some components are omitted in FIG. 7B in order to clarify the device structure.

The transistor and resistor portion 101 illustrated in FIG. 7 includes the insulating layer 112 over the substrate 110, the oxide semiconductor layer 122 over the insulating layer 112, and the conductive layer 141 which is formed in partial contact with the oxide semiconductor layer 122. And the conductive layer 143, the insulating layer 114 over the oxide semiconductor layer 122, the conductive layer 141, and the conductive layer 143, the conductive layer 131 over the insulating layer 114, which partially overlaps with the conductive layer 131, and the conductive layer 131. And an insulating layer 115 over the insulating layer 114.

In the transistor and resistor portion 101, the insulating layer 112 can function as a base insulating layer. A region of the oxide semiconductor layer 122 which overlaps with the conductive layer 131 in the transistor and the resistor portion 101 can function as an active layer of the transistor. The conductive layers 141 and 143 can function as a source electrode and a drain electrode. The insulating layer 114 has a region functioning as a gate insulating layer. The conductive layer 131 can function as a gate electrode. The insulating layer 115 can function as an interlayer insulating layer.

In the transistor and the resistance portion 101, the oxide semiconductor layer 122 can function as a resistance layer of the resistance portion in a region between the conductive layer 131 and the conductive layer 143.

<Structure example 3>
FIG. 8 shows a circuit diagram, a top view, and a cross-sectional view of the transistor 400 and the resistor portion 401. Note that the transistor 400 and the resistor portion 401 can be used for the transistor 11 and the resistor portion 12 in FIG. Further, a structure in which the transistor 400 and the resistor portion 401 in this embodiment include an oxide semiconductor will be described.

The transistor 400 illustrated in FIG. 8 is a bottom-gate transistor instead of the top-gate transistor illustrated in FIGS. 6 and 7.

FIG. 8A shows a circuit diagram of the transistor 400 and the resistor portion 401. 8B is a top view illustrating an example of the structure of the transistor 400 and the resistor portion 401 illustrated in FIG. FIG. 8C is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. Note that some components are omitted in FIG. 8B in order to clarify the device structure.

A transistor 400 illustrated in FIG. 8 includes an insulating layer 112 over the substrate 110, a conductive layer 410 over the insulating layer 112, an insulating layer 412 over the conductive layer 410, an oxide semiconductor layer 414 over the insulating layer 412, and an oxide layer. The conductive layer 418 and the conductive layer 420 which are formed so as to be partly in contact with the object semiconductor layer 414, and the insulating layer 424 over the oxide semiconductor layer 414, the conductive layer 418, and the conductive layer 420.

The resistance portion 401 illustrated in FIG. 8 is in partial contact with the insulating layer 112 over the substrate 110, the insulating layer 412 over the insulating layer 112, the oxide semiconductor layer 416 over the insulating layer 412, and the oxide semiconductor layer 416. The conductive layer 420 and the conductive layer 422 which are formed, and the insulating layer 424 over the oxide semiconductor layer 416, the conductive layer 420, and the conductive layer 422 are formed.

In the transistor 400, the insulating layer 112 can function as a base insulating layer. The oxide semiconductor layer 414 can function as an active layer of the transistor 400. The conductive layers 418 and 420 can function as a source electrode and a drain electrode. The insulating layer 412 has a region functioning as a gate insulating layer. The conductive layer 410 can function as a gate electrode. The insulating layer 424 can function as an interlayer insulating layer.

Further, in the resistance portion 401, the oxide semiconductor layer 416 can function as a resistance layer.

Although the bottom-gate transistor 400 illustrated in FIG. 8 has a channel-etched structure, it may be a channel-protection transistor 402 as illustrated in FIG. 9A.

A transistor 402 illustrated in FIG. 9A includes an insulating layer 112 over the substrate 110, a conductive layer 410 over the insulating layer 112, an insulating layer 412 over the conductive layer 410, and an oxide semiconductor layer 414 over the insulating layer 412. And the insulating layer 428 over the oxide semiconductor layer 414, the conductive layer 430 and the conductive layer 432 which are formed so as to be partly in contact with the oxide semiconductor layer 414 and the insulating layer 428, the oxide semiconductor layer 414, and the insulating layer 428. And an insulating layer 434 over the conductive layer 430 and the conductive layer 432.

In the transistor 402, the insulating layer 112 can function as a base insulating layer. The oxide semiconductor layer 414 can function as an active layer of the transistor 400. The conductive layers 430 and 432 can function as a source electrode and a drain electrode. The insulating layer 412 has a region functioning as a gate insulating layer. The conductive layer 410 can function as a gate electrode. The insulating layer 434 can function as an interlayer insulating layer. The insulating layer 428 can function as a channel protective layer.

A transistor 403 illustrated in FIG. 9B has a structure in which the transistor 400 in FIG. 8 includes a conductive layer 411. In the transistor 403, the conductive layer 411 can function as a back gate electrode.

Further, the resistance portion 401 shown in FIG. 8 may have a structure further including a conductive layer. A resistor portion 404 including a resistor portion 401 and a conductive layer 435 is shown in FIG.

A resistor portion 404 illustrated in FIG. 9C includes an insulating layer 112 over the substrate 110, a conductive layer 435 over the insulating layer 112, an insulating layer 438 over the conductive layer 435, and an oxide semiconductor over the insulating layer 438. A layer 444, a conductive layer 440 and a conductive layer 442 which are formed in partial contact with the oxide semiconductor layer 444, and an insulating layer 446 over the oxide semiconductor layer 444, the conductive layer 440, and the conductive layer 442 are included.

Further, in the resistance portion 404, the oxide semiconductor layer 444 can function as a resistance layer.

The resistor portion 405 illustrated in FIG. 9D has a structure in which the resistor portion 404 in FIG. 9C includes a conductive layer 448.

A resistor portion 406 illustrated in FIG. 9E has a structure in which the resistor portion 401 in FIG. 8 includes an insulating layer 450.

When a film containing a large amount of hydrogen, for example, a film containing silicon nitride is used for the insulating layer 450, the resistance value of the oxide semiconductor layer 416 can be reduced in some cases.

The structure and the method described in this embodiment can be combined with the structures and methods described in other embodiments as appropriate.

(Embodiment 3)
In this embodiment, a structural example of a transistor including an oxide semiconductor (also referred to as an OS transistor) that can be used in one embodiment of the present invention will be described. The OS transistor described in this embodiment can be applied to, for example, the transistor 11 in FIG. 1A, the transistor 58 in FIG. 4A, or the like.

<Structure example 1>
FIG. 10 shows an example of the structure of the OS transistor. FIG. 10A is a top view illustrating an example of the structure of the OS transistor. 10B is a sectional view taken along the line y1-y2, FIG. 10C is a sectional view taken along the line x1-x2, and FIG. 10D is a sectional view taken along the line x3-x4. Here, the direction of the y1-y2 line may be referred to as the channel length direction, and the x1-x2 line direction may be referred to as the channel width direction. Therefore, FIG. 10B is a diagram showing a cross-sectional structure of the OS transistor in the channel length direction, and FIGS. 10C and 10D are diagrams showing a cross-sectional structure of the OS transistor in the channel width direction. Become. Note that in order to clarify the device structure, some components are omitted in FIG.

The OS transistor 501 illustrated in FIG. 10 has a back gate. The OS transistor 501 is formed on the insulating surface. Here, it is formed on the insulating layer 511. The insulating layer 511 is formed on the surface of the substrate 510. The OS transistor 501 is covered with the insulating layers 514 and 515. Note that the insulating layers 514 and 515 can be regarded as components of the OS transistor 501. The OS transistor 501 includes an insulating layer 512, an insulating layer 513, an oxide semiconductor layer 521, an oxide semiconductor layer 522, an oxide semiconductor layer 523, a conductive layer 530, a conductive layer 531, a conductive layer 541, and a conductive layer 542. Here, the oxide semiconductor layer 521, the oxide semiconductor layer 522, and the oxide semiconductor layer 523 are collectively referred to as an oxide semiconductor layer 520. Although a structure having a back gate is shown here, a structure without a back gate may be used.

The insulating layer 513 has a region functioning as a gate insulating layer. The conductive layer 530 functions as a gate electrode (first gate electrode). The conductive layer 531 functions as a back gate electrode (second gate electrode). The conductive layer 541 and the conductive layer 542 each function as a source electrode or a drain electrode. Note that the conductive layer 531 may not be provided (the same applies below).

As illustrated in FIGS. 10B and 10C, the oxide semiconductor layer 520 has a region in which the oxide semiconductor layer 521, the oxide semiconductor layer 522, and the oxide semiconductor layer 523 are sequentially stacked. The insulating layer 513 covers this laminated portion. The conductive layer 531 overlaps with a stacked portion of the oxide semiconductor layer with the insulating layer 513 provided therebetween. The conductive layer 541 and the conductive layer 542 are provided over a stacked film including the oxide semiconductor layer 521 and the oxide semiconductor layer 523, and these are in contact with an upper surface of this stacked film and a side surface in the channel length direction of the stacked film. ing. Further, in the example of FIG. 10, the conductive layers 541 and 542 are also in contact with the insulating layer 512. The oxide semiconductor layer 523 is formed so as to cover the oxide semiconductor layer 521, the oxide semiconductor layer 522, the conductive layers 541, and 542. The lower surface of the oxide semiconductor layer 523 is in contact with the upper surface of the oxide semiconductor layer 522.

In the oxide semiconductor layer 520, the conductive layer 530 is formed so as to surround the stacked portion of the oxide semiconductor layers 521 to 523 in the channel width direction with the insulating layer 513 provided therebetween (see FIG. 10C). Therefore, in addition to the gate electric field from the vertical direction, the gate electric field from the side surface direction is also applied to this laminated portion. In the OS transistor 501, the gate electric field refers to an electric field formed by a voltage applied to the conductive layer 531 (gate electrode layer). Therefore, the gate electric field can electrically surround the entire stacked portion of the oxide semiconductor layers 521 to 523, so that a channel may be formed in the entire oxide semiconductor layer 522 (bulk) in some cases. Therefore, the OS transistor 501 can have high on-current characteristics.

In this specification, the structure of the transistor that can electrically surround the semiconductor by the gate electric field is referred to as a "surrounded channel (s-channel)" structure. The OS transistor 501 has an s-channel structure. In the s-channel structure, a large current can flow between the source and the drain of the transistor, and the drain current (ON current) in the conductive state can be increased.

When the OS transistor 501 has an s-channel structure, the channel formation region can be easily controlled with respect to the side surface of the oxide semiconductor layer 522 by a gate electric field. A structure in which the conductive layer 530 extends below the oxide semiconductor layer 522 and faces the side surface of the oxide semiconductor layer 521 is preferable because the controllability is further excellent. As a result, the sub-threshold swing value (also referred to as S value) of the OS transistor 501 can be reduced and the short channel effect can be suppressed. Therefore, the structure is suitable for miniaturization.

When the OS transistor has a three-dimensional device structure like the OS transistor 501 illustrated in FIG. 10, the channel length can be less than 100 nm. The circuit area can be reduced by miniaturizing the OS transistor. The channel length of the OS transistor is preferably less than 65 nm, more preferably 30 nm or less or 20 nm or less.

The conductor that functions as the gate of the transistor is the gate electrode, the conductor that functions as the source of the transistor is the source electrode, the conductor that functions as the drain of the transistor is the drain electrode, the region that functions as the source of the transistor is the source region, and the drain of the transistor. The region functioning as is called a drain region. In this specification, a gate electrode may be referred to as a gate, a drain electrode or a drain region may be referred to as a drain, and a source electrode or a source region may be referred to as a source.

The channel length is, for example, in a top view of a transistor, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate overlap with each other, or a source in a region where a channel is formed. The distance to the drain. Note that in one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be set to one value. Therefore, in this specification, the channel length is any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

The channel width is, for example, a region where a semiconductor (or a portion of a semiconductor in which a current flows when a transistor is on) and a gate overlap with each other, or a region where a channel is formed, where a source and a drain face each other. The length of a part. Note that in one transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of one transistor may not be set to one value. Therefore, in this specification, the channel width is any one of the values, the maximum value, the minimum value, or the average value in the region where the channel is formed.

Note that depending on the structure of the transistor, a channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and a channel width shown in a top view of the transistor (hereinafter, an apparent channel width). May be different from. For example, in a transistor having a three-dimensional structure, the effective channel width becomes larger than the apparent channel width shown in the top view of the transistor, and the effect thereof may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

In this specification, the term “channel width” may indicate an apparent channel width. Alternatively, in the present specification, the term “channel width” may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, enclosing channel width, etc. can be determined by acquiring a cross-sectional TEM image and analyzing the image. it can.

<Structure example 2>
The OS transistor 502 illustrated in FIG. 11 is a modified example of the OS transistor 501. FIG. 11A is a top view of the OS transistor 502. 11B is a sectional view taken along the line y1-y2, FIG. 11C is a sectional view taken along the line x1-x2, and FIG. 11D is a sectional view taken along the line x3-x4. Note that in order to clarify the device structure, some components are omitted in FIG.

Like the OS transistor 501, the OS transistor 502 illustrated in FIG. 11 also has an s-channel structure. The shapes of the conductive layers 541 and 542 are different from those of the OS transistor 501. The conductive layers 541 and 542 of the OS transistor 502 are formed using a hard mask used to form a stacked film of the oxide semiconductor layer 521 and the oxide semiconductor layer 522. Therefore, the conductive layers 541 and 542 are not in contact with the side surfaces of the oxide semiconductor layer 521 and the oxide semiconductor layer 522 (FIG. 11D).

The oxide semiconductor layers 521 and 522 and the conductive layers 541 and 542 can be manufactured through the following steps. A two-layer oxide semiconductor film which forms the oxide semiconductor layers 521 and 522 is formed. A single-layer or stacked-layer conductive film is formed over the oxide semiconductor film. The conductive film is etched to form a hard mask. By using this hard mask, the two-layer oxide semiconductor film is etched to form a stacked film of the oxide semiconductor layer 521 and the oxide semiconductor layer 522. Next, the hard mask is etched to form the conductive layers 541 and 542.

<Structure examples 3 and 4>
The OS transistor 503 illustrated in FIG. 12 is a modification of the OS transistor 501, and the OS transistor 504 illustrated in FIG. 13 is a modification of the OS transistor 502. In the OS transistor 503 and the OS transistor 504, the oxide semiconductor layer 523 and the insulating layer 513 are etched using the conductive layer 530 as a mask. Therefore, the end portions of the oxide semiconductor layer 532 and the insulating layer 513 are substantially aligned with the end portions of the conductive layer 530.

<Structure examples 5 and 6>
The OS transistor 505 illustrated in FIG. 14 is a modification of the OS transistor 501, and the OS transistor 506 illustrated in FIG. 15 is a modification of the OS transistor 502. The OS transistor 505 and the OS transistor 506 each include a layer 551 between the oxide semiconductor layer 523 and the conductive layer 541 and a layer 552 between the oxide semiconductor layer 523 and the conductive layer 542, respectively.

The layers 551 and 552 can be formed using a layer formed using a transparent conductor, an oxide semiconductor, a nitride semiconductor, or an oxynitride semiconductor, for example. The layers 551 and 552 can be formed using n-type oxide semiconductor layers or can be formed using a conductor layer having higher resistance than the conductive layers 541 and 542. For example, as the layers 551 and 552, a layer containing indium, tin and oxygen, a layer containing indium and zinc, a layer containing indium, tungsten and zinc, a layer containing tin and zinc, a layer containing zinc and gallium, zinc and A layer containing aluminum, a layer containing zinc and fluorine, a layer containing zinc and boron, a layer containing tin and antimony, a layer containing tin and fluorine, a layer containing titanium and niobium, or the like may be used. These illustrated layers may include one or more of hydrogen, carbon, nitrogen, silicon, germanium or argon.

The layers 551 and 552 may have a property of transmitting visible light. Alternatively, the layers 551 and 552 may have a property of not transmitting visible light, ultraviolet light, infrared light, or X-ray by reflecting or absorbing it. With such a property, variation in electric characteristics of the transistor due to stray light can be suppressed in some cases.

For the layers 551 and 552, it is preferable to use a layer which does not form a Schottky barrier with the oxide semiconductor layer 532. Thus, the on characteristics of the OS transistors 505 and 506 can be improved.

The layers 551 and 552 are preferably layers having higher resistance than the conductor 516a and the conductor 516b. In addition, the layers 551 and 552 preferably have lower resistance than the channel resistance of the transistor. For example, the resistivity of the layers 551 and 552 may be 0.1 Ωcm or more and 100 Ωcm or less, 0.5 Ωcm or more and 50 Ωcm or less, or 1 Ωcm or more and 10 Ωcm or less. By setting the resistivity of the layers 551 and 552 within the above range, electric field concentration at the boundary between the channel and the drain can be reduced. Therefore, variation in electric characteristics of the transistor can be reduced. In addition, punch-through current due to the electric field generated from the drain can be reduced. Therefore, the saturation characteristics can be improved even in a transistor having a short channel length. Note that in some circuit configurations in which the source and the drain are not interchanged, it may be preferable to arrange only one of the layers 551 and 552 (for example, the drain side).

<Structure example 7>
10 to 15, the conductive layer 530 functioning as a first gate electrode and the conductive layer 531 functioning as a second gate electrode may be connected to each other. As an example, FIG. 16 illustrates a structure in which the conductive layer 530 and the conductive layer 531 in FIG. 10 are connected.

As illustrated in FIG. 16C, an opening is provided in the insulating layer 512 and the insulating layer 513, and a conductive layer 560 is provided in the opening. The conductive layer 530 is connected to the conductive layer 531 through the conductive layer 560. Accordingly, the first gate electrode and the second gate electrode of the OS transistor 501 can be connected. Note that a structure in which the first gate electrode and the second gate electrode are connected can be similarly applied to FIGS. 11 to 15.

The components of the OS transistors 501 to 506 will be described below.

<Oxide semiconductor layer>
As a semiconductor material of the oxide semiconductor layers 521 to 523, typically, an In—Ga oxide, an In—Zn oxide, and an In—M—Zn oxide (M is Ga, Sn, Y, Zr, La). , Ce, or Nd). Further, the oxide semiconductor layers 521 to 523 are not limited to oxide layers containing indium. The oxide semiconductor layers 521 to 523 can be formed using, for example, a Zn—Sn oxide layer, a Ga—Sn layer, a Zn—Mg oxide, or the like. In addition, the oxide semiconductor layer 522 is preferably formed using an In-M-Zn oxide. The oxide semiconductor layer 521 and the oxide semiconductor layer 523 can each be formed using Ga oxide.

The case where the oxide semiconductor layers 521 to 523 are formed using an In-M-Zn oxide film formed by a sputtering method will be described. The atomic ratio of the metal elements of the target for deposition of the In-M-Zn oxide used for forming the oxide semiconductor layer 522 is In: M: Zn = x ₁ : y ₁ : z ₁ and the oxide semiconductor is The atomic ratio of metal elements in the target used for forming the layer 521 and the oxide semiconductor layer 523 is In: M: Zn = x ₂ : y ₂ : z ₂ .

For forming the oxide semiconductor layer 522, x ₁ / y ₁ is 1/3 or more and 6 or less, further 1 or more and 6 or less, and z ₁ / y ₁ is 1/3 or more and 6 or less, further It is preferable to use an In-M-Zn oxide polycrystalline target of 1 or more and 6 or less. When z ₁ / y ₁ is 1 or more and 6 or less, the CAAC-OS film is easily formed. Typical examples of the atomic ratio of the target metal element are In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 1. .5, In: M: Zn = 2: 1: 2.3, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2. : 4.1 etc. Note that the CAAC-OS is an oxide semiconductor having a c-axis aligned crystal part, which will be described later. It is preferable that the CAAC-OS film do not particularly include a spinel crystal structure. Accordingly, electric characteristics and reliability of the transistor including the CAAC-OS film can be improved.

The target used for forming the oxide semiconductor layers 521 and 523 is x ₂ / y ₂ <x ₁ / y ₁ and z ₂ / y ₂ is 1/3 or more and 6 or less, further 1 or more and 6 or less. Is preferred. The z ₂ / _{y 2} With 1 to 6, tends CAAC-OS film is formed. Typical examples of the atomic ratio of the target metal element are In: M: Zn = 1: 3: 2, In: M: Zn = 1: 3: 4, In: M: Zn = 1: 3: 6, In. : M: Zn = 1: 3: 8, In: M: Zn = 1: 4: 4, In: M: Zn = 1: 4: 5, In: M: Zn = 1: 4: 6, In: M : Zn = 1: 4: 7, In: M: Zn = 1: 4: 8, In: M: Zn = 1: 5: 5, In: M: Zn = 1: 5: 6, In: M: Zn = 1: 5: 7, In: M: Zn = 1: 5: 8, In: M: Zn = 1: 6: 8 and the like.

The atomic number ratio of the In-M-Zn oxide film includes a variation of ± 40% of the above atomic number ratio as an error. For example, the atomic ratio of metal elements contained in an oxide semiconductor film formed using an oxide target of In: M: Zn = 4: 2: 4.1 is approximately In: M: Zn = 4: 2: 3.

[Energy Band] Next, the function and effect of the oxide semiconductor layer 520 formed by stacking the oxide semiconductor layers 521 to 523 will be described with reference to an energy band structure diagram in FIG. FIG. 17A is an enlarged view of the channel region of the OS transistor 502 and is a partially enlarged view of FIG. 11B. FIG. 17B shows an energy band structure of a portion (a channel formation region of the OS transistor 502) indicated by a dotted line z1-z2 in FIG. 17A. The OS transistor 502 will be described below as an example, but the same applies to the OS transistors 501 and 503 to 506.

In FIG. 17B, Ec512, Ec521, Ec522, Ec523, and Ec513 are insulating layers 512, an oxide semiconductor layer 521, an oxide semiconductor layer 522, an oxide semiconductor layer 523, and a conduction band lower end of the insulating layer 513, respectively. Shows energy.

Here, the difference between the vacuum level and the energy at the lower end of the conduction band (also referred to as “electron affinity”) is calculated from the difference between the vacuum level and the energy at the upper end of the valence band (also referred to as ionization potential). It will be the subtracted value. The energy gap can be measured using a spectroscopic ellipsometer (UT-300 manufactured by HORIBA JOBIN YVON). Further, the energy difference between the vacuum level and the upper end of the valence band can be measured by using an ultraviolet photoelectron spectroscopy (UPS) device (VersaProbe, PHI).

An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 3: 2 has an energy gap of about 3.5 eV and an electron affinity of about 4.5 eV. .. An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 3: 4 has an energy gap of about 3.4 eV and an electron affinity of about 4.5 eV. .. An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 3: 6 has an energy gap of about 3.3 eV and an electron affinity of about 4.5 eV. .. An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 6: 2 has an energy gap of approximately 3.9 eV and an electron affinity of approximately 4.3 eV. .. An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 6: 8 has an energy gap of about 3.5 eV and an electron affinity of about 4.4 eV. .. An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 6: 10 has an energy gap of about 3.5 eV and an electron affinity of about 4.5 eV. .. An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 1: 1 has an energy gap of about 3.2 eV and an electron affinity of about 4.7 eV. .. An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 3: 1: 2 has an energy gap of approximately 2.8 eV and an electron affinity of approximately 5.0 eV. ..

Since the insulating layer 512 and the insulating layer 513 are insulators, Ec513 and Ec512 are closer to the vacuum level than Ec521, Ec522, and Ec523 (electron affinity is small).

Further, Ec521 is closer to the vacuum level than Ec522. Specifically, Ec521 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less vacuum level than Ec522. Is preferable.

Further, Ec523 is closer to the vacuum level than Ec522. Specifically, Ec523 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less vacuum level than Ec522. Is preferable.

In addition, since a mixed region is formed in the vicinity of the interface between the oxide semiconductor layer 521 and the oxide semiconductor layer 522 and in the vicinity of the interface between the oxide semiconductor layer 522 and the oxide semiconductor layer 523, energy at the bottom of the conduction band is formed. Changes continuously. That is, there are few or no levels at these interfaces.

Therefore, in the stack structure having the energy band structure, electrons mainly move in the oxide semiconductor layer 522. Therefore, even if a level exists at the interface between the oxide semiconductor layer 521 and the insulating layer 512 or the interface between the oxide semiconductor layer 523 and the insulating layer 513, the level has almost no effect on electron transfer. In addition, since there is no or almost no level at the interface between the oxide semiconductor layer 521 and the oxide semiconductor layer 522 and the interface between the oxide semiconductor layer 523 and the oxide semiconductor layer 522, electron movement occurs in the region. It does not interfere with. Therefore, the OS transistor 502 having the above stacked structure of oxide semiconductors can have high field-effect mobility.

Note that as illustrated in FIG. 17B, trap levels Et502 due to impurities and defects are formed in the interface between the oxide semiconductor layer 521 and the insulating layer 512 and in the vicinity of the interface between the oxide semiconductor layer 523 and the insulating layer 513. However, the oxide semiconductor layer 521 and the oxide semiconductor layer 523 can separate the oxide semiconductor layer 522 from the trap level.

The OS transistor 502 is formed such that the upper surface and the side surface of the oxide semiconductor layer 522 are in contact with the oxide semiconductor layer 523 and the lower surface of the oxide semiconductor layer 522 is in contact with the oxide semiconductor layer 521 in the channel width direction (FIG. 11 (C)). By thus covering the oxide semiconductor layer 522 with the oxide semiconductor layer 521 and the oxide semiconductor layer 523, the influence of the trap level can be further reduced.

However, when the energy difference between Ec521 or Ec523 and Ec522 is small, the electrons of the oxide semiconductor layer 522 may reach the trap level by exceeding the energy difference. The trapped electrons in the trap level generate negative fixed charges at the interface of the insulating film, and the threshold voltage of the transistor shifts in the positive direction.

Therefore, when the energy difference between Ec521 and Ec523 and Ec522 is 0.1 eV or more, preferably 0.15 eV or more, fluctuations in the threshold voltage of the transistor are reduced and the electrical characteristics of the transistor are favorable. It is preferable because it can be

The band gaps of the oxide semiconductor layer 521 and the oxide semiconductor layer 523 are preferably wider than the band gap of the oxide semiconductor layer 522.

For the oxide semiconductor layer 521 and the oxide semiconductor layer 523, for example, a material containing (Ga, Y, Zr, La, Ce, or Nd in an atomic ratio higher than that of the oxide semiconductor layer 522 can be used. Specifically, the atomic ratio is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more Since the above-mentioned elements are strongly bonded to oxygen, oxygen vacancies are generated in the oxide semiconductor. That is, it can be said that the oxide semiconductor layer 521 and the oxide semiconductor layer 523 are less likely to have oxygen vacancies than the oxide semiconductor layer 522.

The In-M- in which the oxide semiconductor layer 521, the oxide semiconductor layer 522, and the oxide semiconductor layer 523 include at least indium, zinc, and M (M is Ga, Sn, Y, Zr, La, Ce, or Nd). In the case of using a Zn oxide, the oxide semiconductor layer 521 is formed of In: M: Zn = x ₁ : y ₁ : z ₁ [atomic ratio], and the oxide semiconductor layer 522 is formed of In: M: Zn = x ₂ : y _2. : Z ₂ [atomic ratio] and the oxide semiconductor layer 523 is In: M: Zn = x ₃ : y ₃ : z ₃ [atomic ratio], y ₁ / x ₁ and y ₃ / x ₃ are y. It is preferably larger than ₂ / x ₂ . y ₁ / x ₁ and y ₃ / x ₃ are 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more than y ₂ / x ₂ . At this time, in the oxide semiconductor layer 522, when y ₂ is greater than or equal to x ₂ , the electrical characteristics of the transistor can be stable. However, when y ₂ is 3 times or more as large as x ₂ , the field-effect mobility of the transistor is lowered, so y ₂ is preferably less than 3 times as large as x ₂ .

The In-M-Zn oxide film satisfying such conditions can be formed by using the In-M-Zn oxide target that satisfies the atomic ratio of the metal elements described above.

The atomic ratio of In and M excluding Zn and O in the oxide semiconductor layer 521 and the oxide semiconductor layer 523 is preferably In less than 50 atomic% and M higher than 50 atomic%, more preferably 25 atomic. %, And M is higher than 75 atomic%. In addition, the atomic ratio of In and M excluding Zn and O in the oxide semiconductor layer 522 is preferably higher than 25 atomic% in In, M less than 75 atomic%, and more preferably higher than 34 atomic% in In. , M is less than 66 atomic%.

In some cases, at least one of the oxide semiconductor layer 521 and the oxide semiconductor layer 523 may not contain indium. For example, the oxide semiconductor layer 521 and / or the oxide semiconductor layer 523 can be formed using a gallium oxide film.

The thickness of the oxide semiconductor layer 521 and the oxide semiconductor layer 523 is 3 nm to 100 nm inclusive, preferably 3 nm to 50 nm inclusive. The thickness of the oxide semiconductor layer 522 is 3 nm to 200 nm inclusive, preferably 3 nm to 100 nm inclusive, more preferably 3 nm to 50 nm inclusive. In addition, the oxide semiconductor layer 523 is preferably thinner than the oxide semiconductor layer 521 and the oxide semiconductor layer 523.

Note that it is effective to reduce the impurity concentration in the oxide semiconductor to make the oxide semiconductor intrinsic or substantially intrinsic in order to impart stable electric characteristics to the OS transistor whose channel is the oxide semiconductor. .. Here, “substantially intrinsic” means that the carrier density of the oxide semiconductor is less than 1 × 10 ¹⁷ / cm ³ , preferably less than 1 × 10 ¹⁵ / cm ³ , and more preferably 1 × 10 7. It is less than ¹³ / cm ³ .

Further, in the oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and a metal element other than the main component become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor. The impurity level serves as a trap and may deteriorate the electrical characteristics of the transistor. Therefore, it is preferable to reduce the concentration of impurities in the oxide semiconductor layer 521, the oxide semiconductor layer 522, and the oxide semiconductor layer 523, and at the interfaces between them.

In order to make an oxide semiconductor intrinsic or substantially intrinsic, in SIMS analysis, for example, at a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor, a silicon concentration of 1 × 10 ¹⁹ atoms / It is less than cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . Further, the hydrogen concentration is, for example, 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less at a certain depth of the oxide semiconductor or in a region having the oxide semiconductor. It is preferably 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 5 × 10 ¹⁸ atoms / cm ³ or less. The nitrogen concentration is, for example, less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less at a certain depth of the oxide semiconductor or in a region having the oxide semiconductor. It is preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In the case where the oxide semiconductor contains crystals, high crystallinity of silicon or carbon might reduce the crystallinity of the oxide semiconductor. In order not to reduce the crystallinity of the oxide semiconductor, for example, at a certain depth of the oxide semiconductor or in a region of the oxide semiconductor, the silicon concentration is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 5 or less. It suffices to have a portion of less than × 10 ¹⁸ atoms / cm ³ , and more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . Further, for example, at a certain depth of the oxide semiconductor or in a region of the oxide semiconductor, the carbon concentration is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and further preferably. Need only have a portion of less than 1 × 10 ¹⁸ atoms / cm ³ .

Further, the off-state current of a transistor including a highly purified oxide semiconductor in a channel formation region as described above is extremely low. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off current standardized by the channel width of the transistor is reduced from several yA / μm to several zA / μm. It becomes possible.

[Off-state current] In this specification, unless otherwise specified, the off-state current refers to a drain current when a transistor is in an off state (also referred to as a non-conduction state or a cutoff state). Unless otherwise specified, the off state is a state in which the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor. Is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor may be a drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

The off-state current of a transistor may depend on Vgs. Therefore, the off-state current of the transistor is less than or equal to I may mean that there is a value of Vgs at which the off-state current of the transistor is less than or equal to I. The off-state current of a transistor may refer to an off-state at a predetermined Vgs, an off-state at Vgs within a predetermined range, an off-state at Vgs at which a sufficiently reduced off-state current is obtained, or the like.

As an example, the threshold voltage Vth is 0.5V, the drain current when Vgs is 0.5V is 1 × 10 ⁻⁹ A, and the drain current when Vgs is 0.1V is 1 × 10 ⁻¹³ A. , And the drain current at Vgs of −0.5 V is 1 × 10 ⁻¹⁹ A, and the drain current at Vgs of −0.8 V is 1 × 10 ⁻²² A. The drain current of the transistor is 1 × 10 ⁻¹⁹ A or lower at Vgs of −0.5 V or in the range of Vgs of −0.5 V to −0.8 V; therefore, the off-state current of the transistor is 1 It may be said that it is not more than × 10 ⁻¹⁹ A. Since there is Vgs at which the drain current of the transistor is 1 × 10 ⁻²² A or lower, the off-state current of the transistor may be 1 × 10 ⁻²² A or lower.

In this specification, the off-state current of a transistor having a channel width W may be represented by a current value flowing around the channel width W. Further, it may be represented by a current value flowing around a predetermined channel width (for example, 1 μm). In the latter case, the unit of off current may be represented by a unit having a dimension of current / length (for example, A / μm).

The off-state current of a transistor may depend on temperature. In the present specification, off-state current may represent off-state current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C., unless otherwise specified. Alternatively, at a temperature at which reliability of a semiconductor device or the like including the transistor is guaranteed, or at a temperature at which the semiconductor device or the like including the transistor is used (for example, any temperature of 5 ° C to 35 ° C). Off current may be expressed. The off-state current of a transistor is less than or equal to I means room temperature, 60 ° C., 85 ° C., 95 ° C., 125 ° C., a temperature at which reliability of a semiconductor device including the transistor is guaranteed, or the transistor is included. It may indicate that there is a value of Vgs at which the off-state current of the transistor is less than or equal to I at the temperature at which the semiconductor device or the like is used (for example, any one temperature of 5 ° C to 35 ° C).

The off-state current of a transistor may depend on the voltage Vds between the drain and the source. In the present specification, the off-state current has Vds of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V unless otherwise specified. , Or off current at 20 V. Alternatively, it may represent Vds at which reliability of a semiconductor device or the like including the transistor is guaranteed or off-state current at Vds used in the semiconductor device or the like including the transistor. The off-state current of a transistor is I or less means that Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V. , Vds that ensures the reliability of the semiconductor device including the transistor, or Vds used in a semiconductor device or the like including the transistor, has a value of Vgs at which the off-state current of the transistor is less than or equal to I. Sometimes referred to.

In the above description of off-state current, the drain may be read as the source. That is, the off-state current may refer to a current flowing through the source when the transistor is off.

In this specification, the term “leakage current” may be used in the same meaning as off current.

In this specification, the off-state current may refer to a current flowing between the source and the drain when the transistor is off, for example.

[Crystal Structure of Oxide Semiconductor Film] The structure of the oxide semiconductor film included in the oxide semiconductor layer 520 is described below. Note that in this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system.

The oxide semiconductor film is roughly classified into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, or the like.

<CAAC-OS Film> The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

Confirming a plurality of crystal parts by observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of the CAAC-OS film with a transmission electron microscope (TEM). You can On the other hand, a clear boundary between crystal parts, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed by a high-resolution TEM image. Therefore, it can be said that in the CAAC-OS film, electron mobility is less likely to be reduced due to the crystal grain boundaries.

When a high-resolution TEM image of a cross section of the CAAC-OS film is observed from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in a layered manner in the crystal part. Each layer of metal atoms has a shape that reflects unevenness of a surface (also referred to as a surface to be formed) or an upper surface of the CAAC-OS film, which is arranged parallel to the surface or the upper surface of the CAAC-OS film. ..

On the other hand, when a high-resolution TEM image of a plane of the CAAC-OS film is observed from a direction substantially perpendicular to the sample surface, it can be confirmed that the metal atoms are arranged in a triangle shape or a hexagon shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

When the structural analysis of the CAAC-OS film is performed using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the CAAC-OS film including a crystal of InGaZnO ₄ by the out-of-plane method, A peak may appear near the diffraction angle (2θ) of 31 °. Since this peak is assigned to the (009) plane of the InGaZnO ₄ crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis faces a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

In the analysis of the CAAC-OS film including the InGaZnO ₄ crystal by the out-of-plane method, a peak may appear at 2θ of around 36 ° in addition to a peak at 2θ of around 31 °. The peak near 2θ of 36 ° indicates that a part of the CAAC-OS film contains a crystal having no c-axis orientation. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

The CAAC-OS film is an oxide semiconductor film having a low impurity concentration. The impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, an element such as silicon which has a stronger bonding force with oxygen than a metal element forming the oxide semiconductor film deprives the oxide semiconductor film of oxygen and thus disturbs the atomic arrangement of the oxide semiconductor film, resulting in crystallinity. Will be a factor to reduce. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have a large atomic radius (or molecular radius); therefore, when contained in the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed and crystallinity is increased. Will be a factor to reduce. Note that the impurities contained in the oxide semiconductor film might serve as carrier traps or carrier generation sources.

The CAAC-OS film is an oxide semiconductor film having a low density of defect states. For example, oxygen vacancies in the oxide semiconductor film might serve as carrier traps or carrier generation sources by trapping hydrogen.

Low impurity concentration and low defect level density (low oxygen deficiency) are called high-purity intrinsic or substantially high-purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film rarely has negative threshold voltage (is rarely normally on). Further, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor including the oxide semiconductor film has high variation in electric characteristics and high reliability. Note that the charge trapped in the carrier traps of the oxide semiconductor film takes a long time to be released, and may behave like fixed charge. Therefore, a transistor including an oxide semiconductor film having a high impurity concentration and a high density of defect states might have unstable electric characteristics.

An OS transistor including a CAAC-OS film has little variation in electric characteristics due to irradiation with visible light or ultraviolet light.

<Microcrystalline Oxide Semiconductor Film> The microcrystalline oxide semiconductor film has a region where crystal parts can be confirmed and a region where clear crystal parts cannot be confirmed in a high-resolution TEM image. The crystal part included in the microcrystalline oxide semiconductor film is often 1 nm to 100 nm inclusive, or 1 nm to 10 nm inclusive. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystals) of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is referred to as an nc-OS (nanocrystalline Oxide Semiconductor) film. Further, in the nc-OS film, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly confirmed in some cases.

The nc-OS film has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In the nc-OS film, no regularity is found in crystal orientation between different crystal parts. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS film may be indistinguishable from the amorphous oxide semiconductor film depending on the analysis method. For example, when a structural analysis is performed on an nc-OS film using an XRD apparatus that uses X-rays having a diameter larger than that of a crystal part, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction (also referred to as selected area electron diffraction) using an electron beam having a probe diameter (eg, 50 nm or more) larger than that of a crystal portion is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. To be done. On the other hand, spots are observed when the nc-OS film is subjected to nanobeam electron diffraction using an electron beam having a probe diameter close to or smaller than that of the crystal part. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed like a circle (in a ring shape). When nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region.

The nc-OS film is an oxide semiconductor film having higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. However, in the nc-OS film, there is no regularity in crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.

<Amorphous Oxide Semiconductor Film> The amorphous oxide semiconductor film is an oxide semiconductor film in which atomic arrangement in the film is irregular and which does not have a crystal part. An example is an oxide semiconductor film having an amorphous state such as quartz.

In the high-resolution TEM image of the amorphous oxide semiconductor film, crystal parts cannot be found. When a structural analysis is performed on the amorphous oxide semiconductor film using an XRD apparatus, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. When electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. When nanobeam electron diffraction is performed on the amorphous oxide semiconductor film, a spot is not observed and a halo pattern is observed.

The oxide semiconductor film may have a structure having physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS: a-like OS: Semiconductor) film.

In the high-resolution TEM image of the a-like OS film, a void may be observed. In addition, in the high-resolution TEM image, there is a region where a crystal part can be clearly confirmed and a region where a crystal part cannot be confirmed. The a-like OS film may be crystallized by the irradiation of a small amount of electrons as observed with a TEM, and growth of a crystal part may be observed. On the other hand, in the case of a good nc-OS film, almost no crystallization due to a small amount of electron irradiation as observed by TEM is observed.

The size of the crystal part of the a-like OS film and the nc-OS film can be measured using a high-resolution TEM image. For example, a crystal of InGaZnO ₄ has a layered structure and includes two Ga—Zn—O layers between In—O layers. The unit cell of the InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers are laminated in total, nine layers in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice distance (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm by crystal structure analysis. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, each lattice fringe corresponds to the ab plane of the InGaZnO ₄ crystal in the place where the lattice fringe spacing is 0.28 nm or more and 0.30 nm or less.

The oxide semiconductor film may have different film density depending on the structure. For example, if the composition of an oxide semiconductor film is known, the structure of the oxide semiconductor film can be estimated by comparison with the film density of a single crystal oxide semiconductor film having the same composition. For example, the film density of the a-like OS film is greater than or equal to 78.6% and less than 92.3% with respect to the film density of the single crystal oxide semiconductor film. In addition, for example, the film density of the nc-OS film and the film density of the CAAC-OS film are 92.3% or more and less than 100% with respect to the film density of the single crystal oxide semiconductor film. Note that it is difficult to form an oxide semiconductor film having a film density of less than 78% with respect to the film density of a single crystal oxide semiconductor film.

The above will be described using a specific example. For example, in an oxide semiconductor film that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the film density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, In: Ga: Zn = 1 : 1: 1 in the oxide semiconductor film which satisfies the atomic ratio of the film density of a-like OS film 5.0 g / cm ³ or more 5.9 g / cm ³ Less than Further, for example, in an oxide semiconductor film satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the film density of the nc-OS film and the film density of the CAAC-OS film are 5.9 g / cm ^3. The above is less than 6.3 g / cm ³ .

Note that a single crystal oxide semiconductor film having the same composition may not exist. In that case, by combining single crystal oxide semiconductor films having different compositions at an arbitrary ratio, the film density corresponding to the single crystal oxide semiconductor film having a desired composition can be calculated. The film density of a single crystal oxide semiconductor film having a desired composition may be calculated using a weighted average with respect to a ratio of combining single crystal oxide semiconductor films having different compositions. However, the film density is preferably calculated by combining as few kinds of single crystal oxide semiconductor films as possible.

Note that the oxide semiconductor film may be a stacked film including two or more kinds of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example. ..

<Substrate>
The substrate 510 is not limited to a simple supporting material, and may be a substrate on which devices such as other transistors are formed. In this case, one of the conductive layer 530, the conductive layer 541, and the conductive layer 542 of the OS transistor 501 may be electrically connected to the above other device.

<Base insulating layer>
The insulating layer 511 has a role of preventing diffusion of impurities from the substrate 510. The insulating layer 512 preferably has a role of supplying oxygen to the oxide semiconductor layer 520. I can carry it. Therefore, the insulating layer 512 is preferably an insulating film containing oxygen, and more preferably an insulating film containing oxygen in a higher proportion than the stoichiometric composition. For example, in TDS (Thermal Desorption Spectroscopy), when the surface temperature of the film is 100 ° C. or higher and 700 ° C. or lower, or the amount of released oxygen molecules is 1.0 × or higher in the range of 100 ° C. or higher and 500 ° C. or lower. The film has a film density of 10 ¹⁸ [molecules / cm ³ ] or more. When the substrate 510 is a substrate on which another device is formed, the insulating layer 511 is preferably subjected to planarization treatment by a CMP (Chemical Mechanical Polishing) method or the like so that the surface is flat.

The insulating layers 511 and 512 are formed using aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or silicon nitride. , An insulating material such as silicon nitride oxide, aluminum nitride oxide, or a mixed material thereof can be used. Note that in this specification, an oxynitride is a material having a higher oxygen content than nitrogen, and a nitride oxide is a material having a higher nitrogen content than oxygen.

<Gate electrode>
The conductive layer 530 includes copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), It is made of a low resistance material such as chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), iridium (Ir), strontium (Sr), platinum (Pt). It is preferable to form a simple substance, an alloy, or a compound containing these as main components.

The conductive layer 530 may have a single-layer structure or a layered structure including two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, and a tungsten film is stacked over a titanium nitride film. A layered structure, a two-layered structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film, a titanium film and a three-layered structure in which an aluminum film is stacked on the titanium film and a titanium film is further formed thereon, Cu -Mn alloy film has a single layer structure, a Cu-Mn alloy film has a two-layer structure in which a Cu film is laminated, a Cu film is laminated on a Cu-Mn alloy film, and a Cu-Mn alloy film is further laminated thereon. There is a three-layer structure. In particular, a Cu—Mn alloy film is preferable because it has low electric resistance and can form manganese oxide at the interface with an insulating film containing oxygen and prevent diffusion of Cu.

The conductive layer 530 includes indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium zinc oxide. Or a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used. Alternatively, a stacked-layer structure of the above light-transmitting conductive material and the above metal element can be used.

Here, when a certain transistor T has a pair of gates which sandwich a semiconductor film therebetween like the OS transistors 501 to 506, one gate receives the signal A and the other gate receives the signal A. The fixed potential Vb may be applied.

The signal A is, for example, a signal for controlling the conducting state or the non-conducting state. The signal A may be a digital signal that takes two types of potentials, the potential V1 or the potential V2 (V1> V2). For example, the potential V1 can be a high power supply potential and the potential V2 can be a low power supply potential. The signal A may be an analog signal.

The fixed potential Vb is, for example, a potential for controlling the threshold voltage VthA of the transistor T. The fixed potential Vb may be the potential V1 or the potential V2. In this case, there is no need to separately provide a potential generating circuit for generating the fixed potential Vb, which is preferable. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. The threshold voltage VthA may be increased by decreasing the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is 0 V may be reduced, and the leak current of the circuit including the transistor T may be reduced in some cases. For example, the fixed potential Vb may be lower than the low power supply potential. The threshold voltage VthA may be lowered by increasing the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is VDD may be improved, and the operation speed of the circuit including the transistor T may be improved in some cases. For example, the fixed potential Vb may be higher than the low power supply potential.

The signal A may be supplied to one gate of the transistor T and the signal B may be supplied to the other gate. The signal B is, for example, a signal for controlling the conductive state or the non-conductive state of the transistor T. The signal B may be a digital signal that takes two types of potentials, the potential V3 or the potential V4 (V3> V4). For example, the potential V3 can be a high power supply potential and the potential V4 can be a low power supply potential. The signal B may be an analog signal.

When both the signal A and the signal B are digital signals, the signal B may be a signal having the same digital value as the signal A. In this case, the on-current of the transistor T can be improved and the operation speed of the circuit including the transistor T can be improved in some cases. At this time, the potential V1 of the signal A may be different from the potential V3 of the signal B. Further, the potential V2 of the signal A may be different from the potential V4 of the signal B. For example, when the gate insulating film corresponding to the gate to which the signal B is input is thicker than the gate insulating film corresponding to the gate to which the signal A is input, the potential amplitude (V3-V4) of the signal B is It may be larger than the potential amplitude (V1-V2). By doing so, in some cases, the influence of the signal A and the influence of the signal B on the conductive state or the non-conductive state of the transistor T can be approximately equal to each other.

When both the signal A and the signal B are digital signals, the signal B may have a digital value different from that of the signal A. In this case, the transistor T can be controlled separately by the signal A and the signal B, and a higher function may be realized in some cases. For example, when the transistor T is an n-channel type, it is conductive only when the signal A has the potential V1 and the signal B has the potential V3, or the signal A has the potential V2 and the signal B. In the case of being in the non-conducting state only when V is the potential V4, one transistor may be able to realize the functions of the NAND circuit, the NOR circuit, and the like. Further, the signal B may be a signal for controlling the threshold voltage VthA. For example, the signal B may be a signal whose potential is different between the period in which the circuit including the transistor T is operating and the period in which the circuit is not operating. The signal B may be a signal having a different potential depending on the operation mode of the circuit. In this case, the potential of the signal B may not switch as frequently as the signal A.

When both the signal A and the signal B are analog signals, the signal B is an analog signal having the same potential as the signal A, an analog signal obtained by multiplying the potential of the signal A by a constant, or a potential obtained by adding or subtracting the potential of the signal A by a constant. It may be an analog signal or the like. In this case, the on-current of the transistor T can be improved and the operation speed of the circuit including the transistor T can be improved in some cases. The signal B may be an analog signal different from the signal A. In this case, the transistor T can be controlled separately by the signal A and the signal B, and a higher function may be realized in some cases.

The signal A may be a digital signal and the signal B may be an analog signal. The signal A may be an analog signal and the signal B may be a digital signal.

The fixed potential Va may be applied to one gate of the transistor T and the fixed potential Vb may be applied to the other gate. When a fixed potential is applied to both gates of the transistor T, the transistor T may be able to function as a resistance element equivalent to the resistance element. For example, when the transistor T is an n-channel type, the effective resistance of the transistor can be reduced (increased) by increasing (decreasing) the fixed potential Va or the fixed potential Vb in some cases. By increasing (decreasing) both the fixed potential Va and the fixed potential Vb, an effective resistance lower (higher) than an effective resistance obtained by a transistor having only one gate may be obtained.

<Gate insulating layer>
The insulating layer 513 is formed of an insulating film having a single layer structure or a stacked structure. The insulating layer 513 includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. An insulating film containing one or more can be used. The insulating layer 513 may be a stack of any of the above materials. Note that the insulating layer 513 may contain lanthanum (La), nitrogen, zirconium (Zr), or the like as an impurity. The insulating layer 511 can be formed similarly to the insulating layer 513. The insulating layer 513 includes, for example, oxygen, nitrogen, silicon, hafnium, or the like. Specifically, it is preferable to contain hafnium oxide and silicon oxide or silicon oxynitride.

Hafnium oxide has a higher relative dielectric constant than silicon oxide or silicon oxynitride. Therefore, the thickness of the insulating layer 513 can be increased as compared with the case where silicon oxide is used, so that leakage current due to a tunnel current can be reduced. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystalline structure has a higher relative dielectric constant than hafnium oxide having an amorphous structure. Therefore, it is preferable to use hafnium oxide having a crystal structure in order to obtain a transistor with low off-state current. Examples of the crystal structure include monoclinic system and cubic system. However, one embodiment of the present invention is not limited to these.

<Source electrode, drain electrode, back gate electrode>
The conductive layer 541, the conductive layer 542, and the conductive layer 531 can be manufactured similarly to the conductive layer 530. The Cu—Mn alloy film has low electric resistance and can form manganese oxide at the interface with the oxide semiconductor layer 520 and prevent Cu from diffusing, and thus can be used for the conductive layers 541 and 542. preferable.

<Protective insulation layer>
The insulating layer 514 preferably has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. By providing such an insulating layer 514, diffusion of oxygen from the oxide semiconductor layer 520 to the outside and entry of hydrogen, water, or the like into the oxide semiconductor layer 520 from the outside can be prevented. As the insulating layer 514, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, and the like. Note that an oxide insulating film having a blocking effect against oxygen, hydrogen, water, or the like may be provided instead of the nitride insulating film having a blocking effect against oxygen, hydrogen, water, an alkali metal, an alkaline earth metal, or the like. Examples of the oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and the like.

The aluminum oxide film is preferable for the insulating layer 514 because it has a high blocking effect of not permeating both oxygen and impurities such as hydrogen and moisture and oxygen. Therefore, the aluminum oxide film prevents impurities, such as hydrogen and moisture, which cause variation in electric characteristics of the transistor, from entering the oxide semiconductor layer 520 during and after the manufacturing process of the transistor, and forms the oxide semiconductor layer 520. It is suitable to be used as a protective film having an effect of preventing release of oxygen which is a main component material from an oxide semiconductor and an unnecessary release of oxygen from the insulating layer 512. Further, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor.

<Interlayer insulation layer>
In addition, an insulating layer 515 is preferably formed over the insulating layer 514. The insulating layer 515 can be formed using an insulating film having a single layer structure or a stacked structure. The insulating film contains one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. An insulating film can be used.

<Film forming method>
A sputtering method and a plasma CVD method are typical methods for forming an insulating film, a conductive film, a semiconductor film, and the like which form a semiconductor device. It can be formed by another method, for example, a thermal CVD method. As the thermal CVD method, for example, a MOCVD (Metal Organic Chemical Vapor Deposition) method can be used. Moreover, you may use ALD (Atomic Layer Deposition) method.

Since the thermal CVD method is a film forming method that does not use plasma, it has an advantage that defects are not generated due to plasma damage. In the thermal CVD method, the inside of the chamber may be at atmospheric pressure or reduced pressure, the source gas and the oxidant may be simultaneously sent into the chamber, and the film may be deposited by reacting in the vicinity of or on the substrate and depositing on the substrate. ..

Further, in the ALD method, the inside of the chamber may be under atmospheric pressure or reduced pressure, raw material gases for the reaction may be sequentially introduced into the chamber, and the order of gas introduction may be repeated to form a film. For example, by switching respective switching valves (also referred to as high-speed valves), two or more kinds of raw material gases are sequentially supplied to the chamber, and at the same time as or after the first raw material gas is mixed so that plural kinds of raw material gases are not mixed. An active gas (argon, nitrogen, etc.) is introduced, and a second source gas is introduced. When the inert gas is introduced at the same time, the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second source gas is introduced. Further, instead of introducing the inert gas, the second raw material gas may be introduced after exhausting the first raw material gas by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first monoatomic layer, and reacts with a second source gas introduced later, so that the second monoatomic layer becomes the first monolayer. A thin film is formed by stacking on the atomic layer. By repeating the gas introduction sequence a plurality of times while controlling the gas introduction sequence, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, it is possible to precisely adjust the film thickness, which is suitable for manufacturing a fine FET.

The conductive films and semiconductor films disclosed in the above-described embodiments can be formed by a film forming method such as MOCVD or ALD. For example, when forming an InGaZnO _X (X> 0) film, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula of trimethylindium is (CH ₃ ) ₃ In. In addition, the chemical formula of trimethylgallium is (CH ₃ ) ₃ Ga. The chemical formula of dimethylzinc is Zn (CH ₃ ) ₂ . Further, without being limited to these combinations, triethylgallium (chemical formula (C ₂ H ₅ ) ₃ Ga) can be used instead of trimethylgallium, and diethyl zinc (chemical formula Zn (C ₂ H ₅ )) can be used instead of dimethylzinc. ₂ ) can also be used.

For example, when forming a tungsten film by a film forming apparatus using ALD, WF ₆ gas and B ₂ H ₆ gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF ₆ gas and H ₂ gas are formed. A tungsten film is formed using gas. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, in the case of forming an oxide semiconductor film, for example, an InGaZnO _X (X> 0) film by a film forming apparatus using ALD, In (CH ₃ ) ₃ gas and O ₃ gas are repeatedly introduced successively to form InO _Two layers are formed, and then Ga (CH ₃ ) ₃ gas and O ₃ gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn (CH ₃ ) ₂ gas and O ₃ gas are successively and repeatedly introduced. A ZnO layer is formed. The order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an InGaO ₂ layer, an InZnO ₂ layer, a GaInO layer, a ZnInO layer, or a GaZnO layer may be formed by mixing these gases. Incidentally, instead of the O ₃ gas may be used the H _{2 O} gas obtained by bubbling with an inert gas such as Ar, but better to use an O ₃ gas containing no H are preferred. Further, In _{(CH 3)} 3 in place of the gas may be used _{In (C 2} H _{5) 3} gas. Further, Ga (C ₂ H ₅ ) ₃ gas may be used instead of Ga (CH ₃ ) ₃ gas. Alternatively, Zn (CH ₃ ) ₂ gas may be used.

Further, although the top gate type transistor structure is shown in this embodiment mode, the present invention is not limited to this. For example, a bottom gate type transistor or a planar type transistor can be applied.

The structure and the method described in this embodiment can be combined with the structures and methods described in other embodiments as appropriate.

(Embodiment 4)
In this embodiment, an example of a cross-sectional structure of a semiconductor device according to one embodiment of the present invention will be described.

<Structure example 1>
18A and 18B are cross-sectional views of the transistor 301, the transistor 302, and the resistor portion 303. Note that the transistor 302 can be used for the transistor 11 in FIG. 1A and the resistor portion 303 can be used for the resistor portion 12 in FIG. The transistor 301 connected to the transistor 302 can be used as a transistor included in the internal circuit 14 in FIG. In FIG. 18, a transistor 301 having a channel formation region in a single crystal semiconductor substrate is located in the first layer, and a transistor 302 which is an OS transistor and a resistor portion 303 are located in the second layer over the first layer. 1 illustrates a cross-sectional structure of a semiconductor device in the case of performing.

The transistor 301 may have a channel formation region in a semiconductor film or a semiconductor substrate of amorphous silicon, germanium, or the like which is amorphous, microcrystalline, polycrystalline, or single crystalline. When the transistor 301 is formed using a silicon thin film, the thin film is formed by a vapor deposition method such as a plasma CVD method or an amorphous silicon manufactured by a sputtering method, or amorphous silicon by a treatment such as laser annealing. It is possible to use crystallized polycrystalline silicon, single crystal silicon obtained by implanting hydrogen ions or the like into a single crystal silicon wafer to peel off the surface layer portion, or the like.

As the semiconductor substrate 310 on which the transistor 301 is formed, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, or the like can be used. FIG. 18 illustrates the case where a single crystal silicon substrate is used as the semiconductor substrate 310.

Further, the transistor 301 is electrically isolated by an element isolation method. As the element isolation method, a selective oxidation method (LOCOS method: Local Oxidation of Silicon method), a trench isolation method (STI method: Shallow Trench Isolation), or the like can be used. FIG. 18 illustrates the case where the transistor 301 is electrically isolated by a trench isolation method. Specifically, in FIG. 18, after the trench is formed in the semiconductor substrate 310 by etching or the like, the transistor 301 is isolated by the element isolation region 311 formed by filling the trench with an insulator containing silicon oxide or the like. The case is illustrated.

The transistor 301 has an impurity region 312a and an impurity region 312b. The impurity regions 312a and 312b function as a source or a drain of the transistor 301.

An insulating film 321 is provided over the transistor 301, and an opening is formed in the insulating film 321. Then, a conductive layer 313a connected to the impurity region 312a and a conductive layer 313b connected to the impurity region 312b are formed in the opening. The conductive layer 313a is connected to the conductive layer 322a formed over the insulating film 321, and the conductive layer 313b is connected to the conductive layer 322b formed over the insulating film 321.

An insulating film 323 is provided over the conductive layers 322a and 322b, and an opening is formed in the insulating film 323. Then, a conductive layer 324 connected to the conductive layer 322a is formed in the opening. The conductive layer 324 is connected to the conductive layer 325 formed over the insulating film 323.

An insulating film 326 is provided over the conductive layer 325.

Then, the transistor 302 which is an OS transistor is provided over the insulating film 326. The transistor 302 includes the oxide semiconductor layer 341 over the insulating film 326, the conductive layers 343a and 343b over the oxide semiconductor layer 341, the oxide semiconductor layer 341, the conductive layer 343a, and the insulating film 344 over the conductive layer 343b. And a conductive layer 345 which is located over the insulating film 344 and has a region overlapping with the oxide semiconductor layer 341. Note that the conductive layers 343a and 343b function as a source electrode or a drain electrode of the transistor 302, the insulating film 344 functions as a gate insulating film of the transistor 302, and the conductive layer 345 functions as a gate of the transistor 302. It has a function as an electrode.

Further, the resistance portion 303 is provided on the insulating film 326. The resistor portion 303 includes the oxide semiconductor layer 342 over the insulating film 326, the conductive layers 343b and 343c over the oxide semiconductor layer 342, the oxide semiconductor layer 342, the conductive layer 343b, and the insulating film 344 over the conductive layer 343c. And have. Note that the oxide semiconductor layer 342 functions as a resistance layer in the resistance portion 303.

An insulating film 346 is provided over the insulating film 344 and the conductive layer 345. Further, a conductive layer 352 and a conductive layer 353 are provided over the insulating film 346. The conductive layer 352 is connected to the conductive layer 325 through the openings provided in the insulating film 326, the insulating film 344, and the insulating film 346, and has the openings provided in the insulating film 344, the insulating film 346, and the insulating film 351. It is connected to the conductive layer 343c through. The conductive layer 353 is connected to the conductive layer 343a through openings provided in the insulating films 344 and 346.

Further, FIG. 18 illustrates the case where the transistor 302 has a single-gate structure including one channel formation region corresponding to one conductive layer 345. However, the transistor 302 may have a multi-gate structure in which the oxide semiconductor layer 341 has a plurality of channel formation regions by having a plurality of gate electrodes connected to each other. Further, a structure having a back gate may be used.

As described above, the area of the semiconductor device can be reduced by stacking the transistor 301, the transistor 302, and the resistor portion 303 to be formed. Alternatively, the transistor 302 and the resistor portion 303 may be stacked and formed.

Note that the transistor 302 and the resistor portion 303 may be formed like the transistor and the resistor portion 101 illustrated in FIG. 7. Alternatively, the transistor 302 may be formed like the transistor illustrated in FIGS.

The structure and the method described in this embodiment can be combined with the structures and methods described in other embodiments as appropriate.

(Embodiment 5)
In this embodiment, an example in which the semiconductor device described in any of the above embodiments is applied to an electronic component and an electronic device including the electronic component is described with reference to FIGS.

In FIG. 19A, an example in which the semiconductor device described in any of the above embodiments is applied to an electronic component will be described. The electronic component is also called a semiconductor package or an IC package. This electronic component has a plurality of standards and names depending on the direction in which the terminal is taken out and the shape of the terminal. Therefore, in this embodiment, an example thereof will be described.

The circuit portion including the transistor as described in the above embodiment is completed by assembling a plurality of detachable components on the printed board through an assembly process (post process).

The post-process can be completed by passing through each process shown in FIG. Specifically, after the element substrate obtained in the previous step is completed (step S1), the back surface of the substrate is ground (step S2). This is because by thinning the substrate at this stage, the warpage of the substrate in the previous process can be reduced and the size of the component can be reduced.

A backside of the substrate is ground to perform a dicing process for separating the substrate into a plurality of chips. Then, a die bonding process is performed in which the separated chips are individually picked up and mounted on the lead frame and bonded (step S3). For the bonding of the chip and the lead frame in this die bonding process, a method suitable for the product is selected, such as resin bonding or tape bonding. In addition, you may mount and bond on an interposer in a die-bonding process.

Next, wire bonding is performed to electrically connect the leads of the lead frame and the electrodes on the chip with a metal thin wire (wire) (step S4). A silver wire or a gold wire can be used as the thin metal wire. In addition, wire bonding may be ball bonding or wedge bonding.

The wire-bonded chip is sealed with epoxy resin or the like and subjected to a molding process (step S5). By performing the molding process, the inside of the electronic component is filled with resin, and it is possible to reduce the damage to the built-in circuit part and wires due to mechanical external force, and reduce the deterioration of the characteristics due to moisture and dust. it can.

Next, the leads of the lead frame are plated. Then, the lead is cut and molded (step S6). By this plating treatment, rust on the leads can be prevented, and soldering can be performed more reliably when the leads are later mounted on the printed circuit board.

Next, a printing process (marking) is performed on the surface of the package (step S7). Then, an electronic component is completed (step S9) through a final inspection step (step S8).

The electronic component described above can be configured to include the semiconductor device described in the above embodiments. Therefore, it is possible to realize an electronic component with reduced power consumption.

In addition, a schematic perspective view of the completed electronic component is shown in FIG. 19C shows an electronic component 1700 on the circuit board 1704 shown in FIG. 19B. FIG. 19B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of the electronic component. An electronic component 1700 illustrated in FIGS. 19B and 19C includes a lead 1701 and a circuit portion 1703. The electronic component 1700 shown in FIG. 19B is mounted on, for example, a printed board 1702. A plurality of such electronic components 1700 are combined and electrically connected to each other on the printed circuit board 1702, whereby the electronic components can be mounted inside the electronic device. The completed circuit board 1704 is provided inside an electronic device or the like.

Further, a semiconductor device or an electronic component according to one embodiment of the present invention is an image reproducing device including a display device, a personal computer, and a recording medium (typically, a recording medium such as a DVD: Digital Versatile Disc or the like is reproduced and an image thereof is displayed. Can be used for a device having a display capable of displaying. In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable information terminal, an electronic book terminal, a video camera, a camera such as a digital still camera, or goggles. Type display (head mount display), navigation system, sound reproduction device (car audio, digital audio player, etc.), copier, facsimile, printer, printer complex machine, automatic teller machine (ATM), vending machine, medical device And so on. Specific examples of these electronic devices are shown in FIGS.

20A shows a portable game machine, which includes a housing 5001, a housing 5002, a display portion 5003, a display portion 5004, a microphone 5005, a speaker 5006, operation keys 5007, a stylus 5008, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a portable game machine. Note that the portable game machine illustrated in FIG. 20A includes two display portions 5003 and 5004, but the number of display portions included in the portable game machine is not limited to this.

FIG. 20B illustrates a personal digital assistant, which includes a first housing 5601, a second housing 5602, a first display portion 5603, a second display portion 5604, a connection portion 5605, operation keys 5606, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a mobile information terminal. The first display portion 5603 is provided in the first housing 5601 and the second display portion 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected to each other by a connecting portion 5605, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connecting portion 5605. is there. The image on the first display portion 5603 may be switched according to the angle between the first housing 5601 and the second housing 5602 in the connection portion 5605. Further, a display device in which a function as a position input device is added to at least one of the first display portion 5603 and the second display portion 5604 may be used. The function as the position input device can be added by providing a touch panel on the display device. Alternatively, the function as the position input device can be added by providing a photoelectric conversion element also called a photosensor in the pixel portion of the display device.

FIG. 20C illustrates a laptop personal computer, which includes a housing 5401, a display portion 5402, a keyboard 5403, a pointing device 5404, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a laptop personal computer.

FIG. 20D illustrates an electric refrigerator-freezer, which includes a housing 5301, a refrigerator compartment door 5302, a freezer compartment door 5303, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of an electric refrigerator-freezer.

FIG. 20E illustrates a video camera, which includes a first housing 5801, a second housing 5802, a display portion 5803, operation keys 5804, a lens 5805, a connection portion 5806, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a video camera. The operation key 5804 and the lens 5805 are provided in the first housing 5801, and the display portion 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connecting portion 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connecting portion 5806. is there. The image on the display portion 5803 may be switched according to the angle between the first housing 5801 and the second housing 5802 in the connection portion 5806.

FIG. 20F illustrates an automobile, which includes a vehicle body 5101, wheels 5102, a dashboard 5103, lights 5104, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits in automobiles.

The structure and the method described in this embodiment can be combined with the structures and methods described in other embodiments as appropriate.

10 semiconductor device 11 transistor 12 resistor section 13 input / output terminal 14 internal circuit 15 power supply line 16 signal line 17 control signal generation circuit 20 semiconductor device 21 transistor 22 resistor section 23 input / output terminal 24 internal circuit 25 power supply line 26 signal line 27 control signal Generation circuit 30 Semiconductor device 31 Transistor 33 Input / output terminal 34 Internal circuit 35 Power supply line 36 Signal line 37 Control signal generation circuit 40 Semiconductor device 42 Resistor section 43 Input / output terminal 44 Internal circuit 45 Power supply line 46 Signal line 50 Semiconductor device 51 Transistor 52 Resistor portion 53 Input / output terminal 54 Internal circuit 55 Power supply line 56 Signal line 57 Control signal generating circuit 58 Transistor 60 Semiconductor device 61 Transistor 62 Resistor portion 63 Input / output terminal 64 Internal circuit 65 Power supply line 66 Signal line 67 Control signal generating circuit 68 Transistor 69 Capacitive element 0 semiconductor device 80 semiconductor device 100 transistor 101 resistance part 110 substrate 112 insulating layer 113 insulating layer 114 insulating layer 115 insulating layer 120 oxide semiconductor layer 121 oxide semiconductor layer 122 oxide semiconductor layer 130 conductive layer 131 conductive layer 141 conductive layer 142 Conductive layer 143 Conductive layer 200 Resistor portion 301 Transistor 302 Transistor 303 Resistor portion 310 Semiconductor substrate 311 Element isolation region 312a Impurity region 312b Impurity region 313a Conductive layer 313b Conductive layer 321 Insulating film 322a Conductive layer 322b Conductive layer 323 Insulating film 324 Conductive layer 325 Conductive layer 326 insulating film 341 oxide semiconductor layer 342 oxide semiconductor layer 343a conductive layer 343b conductive layer 343c conductive layer 344 insulating film 345 conductive layer 346 insulating film 351 insulating film 352 conductive layer 353 conductive layer 00 transistor 401 resistor portion 402 transistor 403 transistor 404 resistor portion 405 resistor portion 406 resistor portion 410 conductive layer 411 conductive layer 412 insulating layer 414 oxide semiconductor layer 416 oxide semiconductor layer 418 conductive layer 420 conductive layer 422 conductive layer 424 insulating layer 428 Insulating layer 430 Conductive layer 432 Conductive layer 434 Insulating layer 435 Conductive layer 438 Insulating layer 440 Conductive layer 442 Conductive layer 444 Oxide semiconductor layer 446 Insulating layer 448 Conductive layer 450 Insulating layer 501 OS transistor 502 OS transistor 503 OS transistor 504 OS transistor 505 OS transistor 506 OS transistor 510 substrate 511 insulating layer 512 insulating layer 513 insulating layer 514 insulating layer 515 insulating layer 516a conductor 516b conductor 520 oxide semiconductor layer 521 oxidation Semiconductor layer 522 Oxide semiconductor layer 523 Oxide semiconductor layer 530 Conductive layer 531 Conductive layer 532 Oxide semiconductor layer 541 Conductive layer 542 Conductive layer 551 Layer 552 Layer 560 Conductive layer 1700 Electronic component 1701 Lead 1702 Printed board 1703 Circuit part 1704 Circuit board 5001 housing 5002 housing 5003 display portion 5004 display portion 5005 microphone 5006 speaker 5007 operation keys 5008 stylus 5101 vehicle body 5102 wheels 5103 dashboard 5104 light 5301 housing 5302 refrigerating room door 5301 housing 5402 housing 5402 display portion 5403 Keyboard 5404 Pointing device 5601 Housing 5602 Housing 5603 Display 5604 Display 5605 Connection 5606 Operation keys 5801 Housing 5802 Housing 803 display unit 5804 operation key 5805 lens 5806 connection section

Claims (2)

Internal circuit,
Input and output terminals,
Signal line,
Power line,
Resistance part,
A first transistor,
A control signal generation circuit,
The internal circuit is electrically connected to the input / output terminal via the signal line,
A first terminal of the first transistor is electrically connected to the power line,
A second terminal of the first transistor is electrically connected to a first terminal of the resistance section,
A second terminal of the resistance portion is electrically connected to the signal line,
It said control signal generating circuit is a gate electrically connected to Ru semiconductor device of the first transistor,
A first conductive layer, a second conductive layer, a third conductive layer, an insulating layer, and an oxide semiconductor layer,
The first conductive layer is provided above the oxide semiconductor layer, has a region overlapping with the oxide semiconductor layer with the insulating layer interposed therebetween, and functions as a gate of the first transistor;
The second conductive layer is arranged above the oxide semiconductor layer, and functions as a first terminal of the first transistor;
The third conductive layer is disposed above the oxide semiconductor layer, and functions as a second terminal of the resistor portion,
The oxide semiconductor layer has a region functioning as a channel formation region of the first transistor and a region functioning as the resistance portion,
The first conductive layer has a region overlapping with the second conductive layer through the insulating layer, and does not overlap with the third conductive layer,
A semiconductor device in which electrical connection between the channel formation region and the resistance portion is performed only through the oxide semiconductor layer. A first conductive layer, a second conductive layer, a third conductive layer, an insulating layer, and an oxide semiconductor layer,
The first conductive layer is provided above the oxide semiconductor layer, has a region overlapping with the oxide semiconductor layer with the insulating layer interposed therebetween, and functions as a gate of a transistor;
The second conductive layer is disposed above the oxide semiconductor layer and functions as one of a source electrode and a drain electrode of the transistor,
The third conductive layer is disposed above the oxide semiconductor layer, and functions as one of a pair of terminals of the resistor portion,
The oxide semiconductor layer has a region functioning as a channel formation region of the transistor and a region functioning as the resistance portion,
The first conductive layer has a region overlapping with the second conductive layer through the insulating layer, and does not overlap with the third conductive layer,
A semiconductor device in which electrical connection between the channel formation region and the resistance portion is performed only through the oxide semiconductor layer.

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