JP6690935B2 - Semiconductor device - Google Patents

Description

One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Alternatively, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an imaging device, a driving method thereof, or a manufacturing method thereof.

Patent Document 1 describes a memory device including a transistor including an oxide semiconductor and a transistor including single crystal silicon. Further, it is described that a transistor including an oxide semiconductor has extremely low off-state current.

JP, 2012-256400, A

One object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of storing multi-valued information. Alternatively, one object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

Note that one embodiment of the present invention does not necessarily need to solve all of the above problems and may be at least one problem. Further, the above description of the problems does not prevent the existence of other problems. Problems other than these are obvious from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. .

A semiconductor device according to one embodiment of the present invention includes a memory cell, and the memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. And a second capacitor, the gate of the first transistor is electrically connected to the first wiring, and one of a source and a drain of the first transistor is a gate of the second transistor. And one of the source and the drain of the first transistor is electrically connected to the second wiring, and one of the source and the drain of the second transistor is electrically connected to the second capacitor. Of the second transistor, the other of the source and the drain of the second transistor is electrically connected to the third wiring, and the gate of the third transistor is electrically connected to the fourth wiring. One of the source and the drain of the third transistor is electrically connected to the second capacitor, and the other of the source and the drain of the third transistor is electrically connected to the second wiring, The gate of the fourth transistor is electrically connected to the fifth wiring, and one of the source and the drain of the fourth transistor is electrically connected to the second wiring, and the source or the drain of the fourth transistor. The other one is a semiconductor device electrically connected to the sixth wiring.

Further, a semiconductor device according to one embodiment of the present invention has a function of supplying a first potential corresponding to a potential held in one of a source and a drain of a first transistor to a sixth wiring, It may have a function of supplying a second potential corresponding to the potential held in one of the source and the drain of the transistor to the sixth wiring.

Further, in the semiconductor device according to one embodiment of the present invention, the second potential is supplied to the sixth wiring by distributing the charge accumulated in the second capacitor to the first capacitor. You may break.

Further, in the semiconductor device according to one embodiment of the present invention, charge may be distributed after the reset potential is supplied from the sixth wiring to one of the source and the drain of the first transistor.

Further, in the semiconductor device according to one embodiment of the present invention, the first transistor and the third transistor may include an oxide semiconductor in a channel formation region.

Further, in the semiconductor device according to one embodiment of the present invention, the first transistor is provided over the second transistor, and the third transistor and the fourth transistor are provided over the first transistor. Good.

A memory device according to one embodiment of the present invention includes the above semiconductor device and a driver circuit.

An electronic device according to one embodiment of the present invention includes the semiconductor device or the memory device, a display portion, a microphone, a speaker, or an operation key.

According to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device capable of storing multi-valued information can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have to have all of these effects. It should be noted that the effects other than these are obvious from the description of the specification, drawings, claims, etc., and the effects other than these can be extracted from the description of the specification, drawings, claims, etc. Is.

7A to 7C each illustrate one embodiment of the present invention. FIG. 9 is a circuit diagram illustrating one embodiment of the present invention. Timing chart. FIG. 6 is a circuit diagram illustrating operation of one embodiment of the present invention. FIG. 6 is a circuit diagram illustrating operation of one embodiment of the present invention. FIG. 6 is a circuit diagram illustrating operation of one embodiment of the present invention. FIG. 9 is a schematic diagram illustrating one embodiment of the present invention. FIG. 9 is a schematic diagram illustrating one embodiment of the present invention. FIG. 9 is a circuit diagram illustrating one embodiment of the present invention. FIG. 9 is a circuit diagram illustrating one embodiment of the present invention. 7A to 7C each illustrate one embodiment of the present invention. 7A to 7C each illustrate one embodiment of the present invention. 7A to 7C each illustrate one embodiment of the present invention. 7A to 7C each illustrate one embodiment of the present invention. 7A to 7C each illustrate one embodiment of the present invention. 7A to 7C each illustrate one embodiment of the present invention. 7A to 7C each illustrate one embodiment of the present invention. 7A to 7C each illustrate one embodiment of the present invention. 7A to 7C each illustrate one embodiment of the present invention. 7A to 7C each illustrate one embodiment of the present invention. 7A to 7C each illustrate one embodiment of the present invention. 7A to 7C each illustrate one embodiment of the present invention. 7A to 7C each illustrate one embodiment of the present invention. 6A and 6B each illustrate an example of a structure of a transistor. 6A and 6B each illustrate an example of a structure of a transistor. 6A and 6B each illustrate an example of a structure of a transistor. 9 is a flowchart illustrating an example of a method for manufacturing an electronic component. 7A to 7C each illustrate an electronic device. 7A to 7C each illustrate characteristics of a transistor. 7A to 7C each illustrate characteristics of a transistor. 7A to 7C each illustrate characteristics of a transistor.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description of the embodiments below, and it is easily understood by those skilled in the art that modes and details thereof can be variously modified without departing from the spirit and scope of the present invention. To be done. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

Further, one embodiment of the present invention includes, in addition to a memory device, any device including an RF (Radio Frequency) tag, a display device, an imaging device, and an integrated circuit in its category. Further, the display device includes a liquid crystal display device, a light emitting device having a light emitting element represented by an organic light emitting element in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission). A display device having an integrated circuit such as a display is included in the category.

In describing the structure of the invention with reference to the drawings, the same reference numerals may be commonly used in different drawings.

Further, in this specification and the like, when it is explicitly described that X and Y are connected, a case where X and Y are electrically connected and a case where X and Y function The case where they are connected to each other and the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relation, for example, a connection relation shown in a figure or a sentence, and other than the connection relation shown in a diagram or a sentence is also described in the diagram or the sentence. Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display) that enables an electrical connection between X and Y is given. Elements, light emitting elements, loads, etc.) are not connected between X and Y, and elements (eg, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y , Resistor element, diode, display element, light emitting element, load, etc.) and X and Y are connected.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display, etc.) that enables the X and Y to be electrically connected is used. Element, light emitting element, load, etc.) may be connected between X and Y. The switch has a function of controlling on / off. That is, the switch is in a conducting state (on state) or a non-conducting state (off state) and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

Examples of the case where X and Y are functionally connected include a circuit (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.)) that enables functional connection between X and Y, and signal conversion. Circuits (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (step-up circuit, step-down circuit, etc.), level shifter circuit for changing signal potential level, etc.), voltage source, current source, switching Circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc. It is possible to connect more than one in between. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. To do. In addition, when X and Y are functionally connected, it includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

In addition, when it is explicitly described that X and Y are electrically connected, when X and Y are electrically connected (that is, when X and Y are separately connected, Element or another circuit is sandwiched and connected) and X and Y are functionally connected (that is, another circuit is sandwiched between X and Y and functionally connected). And a case where X and Y are directly connected (that is, a case where another element or another circuit is connected between X and Y without being sandwiched). It is assumed to be disclosed in a written document. That is, when explicitly described as being electrically connected, the same content as in the case where only explicitly described as being connected is disclosed in this specification and the like. It has been done.

Even in the case where independent components are illustrated as electrically connected to each other in the drawing, even when one component also has the functions of a plurality of components, is there. For example, in the case where part of the wiring also functions as an electrode, one conductive film has a function of both a wiring function and an electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film also has functions of a plurality of components.

(Embodiment 1)
In this embodiment, a structural example of the semiconductor device according to one embodiment of the present invention will be described.

<Example of configuration of semiconductor device>
FIG. 1A illustrates a configuration example of a semiconductor device 10 according to one embodiment of the present invention. The semiconductor device 10 has a plurality of memory cells 20 and can be used as a memory device. Here, a configuration in which the semiconductor device 10 has memory cells 20 (memory cells 20 [1, 1] to [n, m]) of n rows and m columns (n and m are natural numbers) will be described.

The memory cell 20 has a function of storing data. In particular, in one embodiment of the present invention, data (multivalued data) of 2 bits or more can be stored in the memory cell 20. As a result, the area of the semiconductor device 10 per 1 bit can be reduced.

The memory cell 20 is connected to the wiring WL and the wiring BL. The wiring WL has a function of transmitting a signal (hereinafter, also referred to as a selection signal) for selecting the memory cell 20 in a predetermined row. The wiring BL has a function of transmitting a potential (hereinafter also referred to as a write potential) corresponding to data to be written in the selected memory cell 20. Further, the wiring BL has a function of transmitting a potential (hereinafter also referred to as a read potential) corresponding to the data stored in the memory cell 20.

Note that here, a structure in which the writing potential and the reading potential are output to the same wiring BL is shown; however, the writing potential and the reading potential may be output to different wirings.

Here, the memory cell 20 is connected to a plurality of wirings WL. In FIG. 1A, the memory cell 20 is connected to two wirings WL (wirings WLa and WLb). As a result, data of 2 bits or more can be written in each memory cell 20.

Specifically, as shown in FIG. 1B, the memory cell 20 has a plurality of holding portions 21. The holding unit 21 is a circuit having a function of holding a predetermined potential. Here, as an example, a configuration in which the memory cell 20 has two holding portions 21 (holding portions 21a and 21b) is shown. The holding portion 21a is connected to the wiring WLa and the wiring BL, and the holding portion 21b is connected to the wiring WLb and the wiring BL.

When the selection signal is supplied to the wiring WLa, the writing potential is supplied from the wiring BL to the holding portion 21a and is held therein. When the selection signal is supplied to the wiring WLb, the writing potential is supplied from the wiring BL to the holding portion 21b and held therein. By holding the holding portions 21a and 21b at two or more potentials, it is possible to store data of two bits or more in the memory cell 20.

The holding portion 21a can hold a potential of i value (i is a natural number), and the holding portion 21b can hold a potential of j value (j is a natural number). The values of i and j can be set freely. For example, the potentials held in the holding units 21a and 21b may be binary potentials (i = 2, j = 2) of high level and low level, respectively, or arbitrary potentials of three or more values (i Is 3 or more and j is 3 or more). The values of i and j may be the same or different.

Data is read from the memory cell 20 by using a potential corresponding to the potential held in the holding portion 21a (first reading potential) and a potential corresponding to the potential held in the holding portion 21b (second reading potential). , Are output to the wiring BL. Specifically, first, the holding portion 21a outputs the first read potential to the wiring BL. After that, the data held in the holding unit 21b is transferred to the holding unit 21a. Then, the second reading potential is output from the holding portion 21a to the wiring BL. Here, when the potential held in the holding unit 21a is the i value and the potential held in the holding unit 21b is the j value, it is possible to read i × j value data from the memory cell 20. That is, when the holding unit 21a stores a-bit (a is a natural number) data and the holding unit 21b stores b-bit (b is a natural number) data, a + b-bit data can be read.

Here, for the holding portion 21, it is preferable to use a transistor including an oxide semiconductor in a channel formation region (hereinafter also referred to as an OS transistor). An oxide semiconductor has a wider bandgap and a lower carrier density than other semiconductors such as silicon. Therefore, the off-state current of the OS transistor is extremely small. Therefore, by using the OS transistor for the holding portion 21, the potential held in the holding portion 21 can be held for a long time.

An example of the structure of the holding unit 21 is shown in FIG. The holding portion 21 includes a transistor 22 and a capacitor 23. Note that the transistor 22 is an OS transistor. One of a source and a drain of the transistor 22 is connected to the capacitor 23. Here, a node connected to one of the source and the drain of the transistor 22 and the capacitor 23 is referred to as a node FN.

The potential held in the holding portion 21 is supplied to the node FN from the wiring BL or the like through the transistor 22. Then, when the transistor 22 is turned off, the node FN is in a floating state and the potential of the node FN is held. Here, since the off-state current of the transistor 22 which is an OS transistor is extremely small, the potential of the node FN can be held for a long time. Note that the conductive state of the transistor 22 can be controlled by supplying a predetermined potential to a wiring connected to the gate of the transistor 22.

The potential held in the node FN may be a binary (high level and low level) potential, or a ternary or higher potential. In particular, when the potential held in the node FN has three or more values, the interval between the held potentials becomes narrow, so that minute charge leakage can cause data variation. However, since the off-state current of the OS transistor is extremely small, the leakage of charges from the node FN can be suppressed to be extremely small. Therefore, it is particularly preferable to use the transistor 22 as an OS transistor in the case of holding a potential of three or more values in the node FN.

Further, the OS transistor has higher withstand voltage than a transistor including silicon in a channel formation region (hereinafter also referred to as a Si transistor). Therefore, when the transistor 22 is an OS transistor, the range of potential held in the node FN can be widened. Therefore, the number of data held in the holding unit 21 can be increased.

For example, the node FN can hold a 16-value potential. When 16-value potentials are held in the holding units 21a and 21b (i = 16, j = 16), 4-bit data can be stored in the holding units 21a and 21b (a = 4, b). = 4). Then, i × j = 16 × 16 = 256 values, that is, a + b = 4 + 4 = 8-bit data can be read from the memory cell 20. Further, for example, when 4-bit data is stored in the holding unit 21a and 5-bit data is stored in the holding unit 21b, 9-bit data can be read from the memory cell 20.

As described above, by providing the memory cell 20 with the plurality of holding portions 21, it is possible to provide a semiconductor device capable of storing multilevel data. In addition, by using an OS transistor for the holding portion 21, the charge accumulated in the holding portion 21 can be held for a long time and a highly reliable semiconductor device can be provided. Hereinafter, a specific configuration example of the memory cell 20 will be described.

<Example of memory cell configuration>
FIG. 2A shows a specific configuration example of the memory cell 20. The memory cell 20 has a circuit 30, a circuit 40, and a circuit 50. The circuit 30 includes a transistor 31 and a capacitor 32. The circuit 40 includes a transistor 41, a capacitor 42, and a transistor 43. The circuit 50 has a transistor 51. Note that the circuits 30 and 40 correspond to the holding portions 21a and 21b in FIG. 1B, respectively. Further, the circuit 50 has a function of controlling reading of data stored in the memory cell 20.

The gate of the transistor 31 is connected to the wiring WLa, one of the source and the drain is connected to one electrode of the capacitor 32 and the gate of the transistor 51, and the other of the source and the drain is connected to the wiring SBL. The other electrode of the capacitor 32 is connected to the wiring WLCa. Here, a node connected to one of a source and a drain of the transistor 31, one electrode of the capacitor 32, and a gate of the transistor 51 is a node FNa.

A gate of the transistor 41 is connected to the wiring WLb, one of a source and a drain is connected to one electrode of the capacitor 42, and the other of the source and the drain is connected to the wiring SBL. The other electrode of the capacitor 42 is connected to the wiring WLCb. A gate of the transistor 43 is connected to the wiring WLc, one of a source and a drain is connected to the wiring SBL, and the other of the source and the drain is connected to the wiring BL. Here, a node connected to one of a source and a drain of the transistor 41 and one electrode of the capacitor 42 is a node FNb.

The gate of the transistor 51 is connected to the node FNa, one of the source and the drain is connected to the wiring SBL, and the other of the source and the drain is connected to the wiring SL.

The wiring WLCa is a wiring having a function of transmitting a signal for controlling the potential of the node FNa (hereinafter also referred to as a read control signal). The wiring WLCb and the wiring SL are wirings having a function of transmitting a constant potential. Note that the wiring WLCb and the wiring SL may be supplied with the high power supply potential VDD or the low power supply potential VSS (ground potential or the like). Further, the potentials supplied to the wiring WLCb and the wiring SL do not have to be constant. A signal for controlling the potential of the node FNb may be supplied to the wiring WLCb.

Note that the wiring SL may be shared by the adjacent memory cells 20.

Here, the transistors 31 and 41 are preferably OS transistors. Thus, when the transistors 31 and 41 are off, the charge accumulated in the nodes FNa and FNb can be held for a long time. Therefore, it is possible to accurately hold the three or more potentials at the nodes FNa and FNb. Note that the nodes FNa and FNb correspond to the node FN in FIG.

The type of the transistor 43 is not particularly limited. For example, an OS transistor may be used, or a transistor in which a channel formation region is formed in part of a substrate including a single crystal semiconductor (hereinafter also referred to as a single crystal transistor) may be used. As a substrate having a single crystal semiconductor, a single crystal silicon substrate, a single crystal germanium substrate, or the like can be given.

Alternatively, as the transistor 43, a transistor in which a channel formation region is formed in a film containing a semiconductor material other than an oxide semiconductor can be used. For example, a transistor including a non-single crystal semiconductor in a channel formation region can be used. Examples of the non-single-crystal semiconductor include non-single-crystal silicon such as amorphous silicon, microcrystalline silicon, and polycrystalline silicon, and non-single-crystal germanium such as amorphous germanium, microcrystalline germanium, and polycrystalline germanium.

A transistor similar to the transistor 43 can be used for the transistor 51. Alternatively, as the transistors 31 and 41, a single crystal transistor or a transistor in which a channel formation region is formed in a film containing a semiconductor material other than an oxide semiconductor can be used. In particular, when the transistor 51 is a single crystal transistor, data can be read from the memory cell 20 at high speed.

Next, the operation of the memory cell 20 will be described. In particular, the operation of the memory cell 20 shown in FIG. 2A will be described here.

First, the potential of the wiring WLc is set to a potential at which the transistor 43 is turned on, so that the transistor 43 is turned on. Then, the potential of the wiring WLa is set to a potential at which the transistor 31 is turned on, so that the transistor 31 is turned on. Accordingly, the potential of the wiring BL (writing potential) is supplied to the node FNa (writing data). Next, the potential of the wiring WLa is set to a potential at which the transistor 31 is turned off, so that the transistor 31 is turned off. As a result, the node FNa is brought into a floating state and the potential of the node FNa is held (data holding). With such an operation, writing and holding of data is performed in the circuit 30.

During the data retention period, the transistor 51 is preferably turned off regardless of the potential written in the node FNa. Specifically, when the transistor 51 is a p-channel type, the potential of the wiring WLCa is raised to a high level. At this time, the potential of the node FNa also rises due to the capacitive coupling of the capacitive element 32. Thus, the transistor 51 can be turned off regardless of the potential written in the node FNa. The potential of the node FNa may be set such that the magnitude of the gate-source voltage of the transistor 51 is less than or equal to the magnitude of the threshold voltage of the transistor 51. Accordingly, current flowing between the source and the drain of the transistor 51 in the data retention period can be suppressed and power consumption can be reduced.

Next, the potential of the wiring WLb is set to a potential at which the transistor 41 is turned on, so that the transistor 41 is turned on. Accordingly, the potential of the wiring BL (writing potential) is supplied to the node FNb (writing data). Next, the potential of the wiring WLb is set to a potential at which the transistor 41 is turned off, so that the transistor 41 is turned off. Accordingly, the node FNb is brought into a floating state and the potential of the node FNb is held (data holding). By such an operation, writing and holding of data is performed in the circuit 40.

Although an example in which the write operation in the circuit 40 is performed after the write operation in the circuit 30 is described here, data may be written in the circuit 30 after writing data in the circuit 40.

The potentials supplied from the wiring BL to the nodes FNa and FNb may be binary potentials of high level and low level (i = 2, j = 2), or potentials of three values or more (i Is 3 or more and j is 3 or more). The values of i and j may be the same or different.

Here, consider a case where the nodes FNa and FNb hold 1-bit data for 10 years. When the power supply voltage is 2 V or more and 3.5 V or less, the holding capacitance of the nodes FNa and FNb is 21 fF, and the allowable fluctuation amount of the holding potential is less than 0.5 V, the holding potential is less than the allowable fluctuation amount at 85 ° C. for 10 years. Therefore, the leakage current from the nodes FNa and FNb needs to be less than 33 × 10 ⁻²⁴ A. When the leakage from other is smaller and the leak location is almost the OS transistor, the leakage current per unit area of the OS transistor is less than 93 × 10 ⁻²⁴ A / μm when the channel width of the OS transistor is 350 nm. Is preferred. With the configuration of the memory cell 20 described above, the memory cell 20 can hold data at 85 ° C. for 10 years.

Also, consider a case where the nodes FNa and FNb hold 4-bit data for 10 years. When the power supply voltage is 2 V or more and 3.5 V or less, the holding capacity is 0.1 fF, the holding potential distribution width is less than 30 mV, and the allowable fluctuation amount of the holding potential is less than 80 mV, the holding potential is allowed at 85 ° C for 10 years. In order to reduce the fluctuation amount, the leakage current from the nodes FNa and FNb needs to be less than 0.025 × 10 ⁻²⁴ A. When the leakage from other is smaller and the leaked portion is almost the OS transistor, the leakage current per unit area of the OS transistor is less than 0.423 × 10 ⁻²⁴ A / μm when the channel width of the OS transistor is 60 nm. Preferably. With the configuration of the memory cell 20 described above, the memory cell 20 can hold data at 85 ° C. for 10 years.

Also, consider a case where the nodes FNa and FNb hold 8-bit data for 10 years. When the power supply voltage is 2 V or more and 3.5 V or less, the holding capacitance is 0.1 fF, the holding potential distribution width is less than 2 mV, and the allowable fluctuation amount of the holding potential is less than 5 mV, the holding potential is 85 ° C. for 10 years. In order to make it less than the permissible fluctuation amount, it is necessary that the leak current from the nodes FNa and FNb is less than 0.0016 × 10 ⁻²⁴ A. In the case where the leak from other is smaller and the leak is almost the OS transistor, the leak current per unit area of the OS transistor is less than 0.026 × 10 ⁻²⁴ A / μm when the channel width of the OS transistor is 60 nm. Preferably. With the configuration of the memory cell 20 described above, the memory cell 20 can hold data at 85 ° C. for 10 years.

Next, the operation of reading data from the circuit 30 will be described.

First, the transistor 43 is turned on, and the wiring BL and the wiring SBL are precharged to a predetermined potential (here, high level). Further, a predetermined potential (here, low level) is supplied to the wiring SL.

After that, the potential of the wiring WLCa is set at a low level and the potential of the node FNa is lowered. Accordingly, the potential of the node FNa becomes the potential supplied from the wiring BL at the time of writing. Then, the wiring SBL and the wiring BL are supplied with a predetermined potential from the wiring SL in accordance with the potential of the node FNa. Specifically, when the potentials of the wiring BL and the wiring SBL fall from the high level and the magnitude of the voltage between the node FNa and the wiring SBL becomes less than or equal to the threshold voltage of the transistor 51, the transistor 51 is turned off. , The potentials of the wiring BL and the wiring SBL are determined. That is, the potentials of the wiring BL and the wiring SBL have different values depending on the potential of the node FNa. Therefore, the potential of the node FNa can be determined by reading the potential of the wiring BL.

Next, a potential for resetting the node FNa (hereinafter also referred to as a reset potential) is supplied to the wiring BL. Here, a low-level potential is supplied as the reset potential. Then, the potential of the wiring WLa is set to a potential at which the transistor 31 is turned on, so that the transistor 31 is turned on. Accordingly, the potential is supplied from the wiring BL to the node FNa, and the potential of the node FNa is reset to a low level.

Next, the potential of the wiring WLc is set to a potential at which the transistor 43 is turned off, so that the transistor 43 is turned off. After that, the potential of the wiring WLb is set to a potential at which the transistor 41 is turned on, so that the transistor 41 is turned on. Accordingly, the node FNa and the node FNb are brought into conduction through the wiring SBL, and the charge accumulated in the node FNb is distributed to the node FNa. As a result, the data stored in the circuit 40 is transferred to the circuit 30.

Here, when the transistors 31 and 41 are turned on, the capacitances of the capacitors 32 and 42 are added to the wiring SBL. Therefore, the potential supplied from the node FNb to the node FNa through the wiring SBL by the charge distribution is lower than the potential of the node FNb before the charge distribution. Therefore, it is preferable that the capacitance value of the capacitance element 42 be larger than the capacitance value of the capacitance element 32. Alternatively, the potential written in the node FNb is preferably higher than the normal write potential. As a result, it is possible to suppress a decrease in potential due to distribution of electric charges. Note that details of the potential variation due to charge distribution will be described later.

Next, the data transferred from the circuit 40 to the circuit 30 is read. This read can be performed by the same operation as the data read from the circuit 30 described above. That is, this can be performed by changing the potentials of the wiring BL and the wiring SBL in accordance with the potential of the node FNa after the charge distribution.

By the above operation, writing and reading of multi-valued data can be performed in the memory cell 20. Specifically, when the i-valued potential is written to the node FNa and the j-valued potential is written to the node FNb, by reading the i-valued potential and the j-valued potential output to the wiring BL, It is possible to read i × j value data.

Rewriting of data in the circuits 30 and 40 can be performed by the same operation as writing and holding of the above data.

Although FIG. 2A shows an example in which the transistors 31, 41, 43 are n-channel type and the transistor 51 is p-channel type, the transistors 31, 41, 43, 51 are respectively n-channel type. Alternatively, it may be a p-channel type. For example, as shown in FIG. 2B, the transistor 51 can be an n-channel type.

In the memory cell 20 illustrated in FIG. 2B, the potential of the wiring WLCa is set at a low level and the potential of the node FNa is lowered, so that the transistor 51 is turned off regardless of the potential written in the node FNa. be able to. Further, the potential of the wiring SL is set to a high level and the wiring BL is precharged to a low level, whereby data can be read from the memory cell 20. For the other operations, the description of the memory cell 20 in FIG. 2A can be referred to.

<Operation example of memory cell>
Next, an operation example of the memory cell 20 will be described. FIG. 3 is a timing chart for explaining the operation of the memory cell 20 shown in FIG. Note that the periods T11 to T13 are periods in which data is written to the memory cell 20, and the periods T21 to T26 are periods in which data are read from the memory cell 20. In addition, FIG. 4A, FIG. 4B, FIG. 5A, FIG. 5B, FIG. 6A, and FIG. 6B respectively show a period T11, a period T12, a period T22, and a period T22. It is a figure showing operation | movement of the memory cell 20 in T23, period T24, and period T26.

First, in the period T11, the writing potential Vwa is supplied to the wiring BL. Note that the write potential Vwa can be a three-value or higher potential. Here, a case where a 16-value (i = 16) write potential Vwa is supplied to the wiring BL is described. In this case, 4-bit data is written in the circuit 30.

Then, the wiring WLCa is set to a low level. Further, the potentials of the wirings WLa and WLc are set to a high level, so that the transistors 31 and 43 are turned on. Accordingly, as illustrated in FIG. 4A, the potential Vwa of the wiring BL is supplied to the node FNa. That is, data is written in the circuit 30.

Next, in the period T12, the potential of the wiring WLa is set at a low level, so that the transistor 31 is turned off. Accordingly, the node FNa is brought into a floating state and the potential of the node FNa is held even if the potential of the wiring BL is changed. Here, the potential of the wiring WLCa is set at a high level and the potential of the node FNa is increased. Accordingly, the transistor 51 is turned off regardless of the potential supplied from the wiring BL to the node FNa.

Then, the write potential Vwb is supplied to the wiring BL. Note that the write potential Vwb can be a three-value or higher potential. Here, a case where a 16-value (j = 16) write potential Vwb is supplied to the wiring BL is described. In this case, 4-bit data is written in the circuit 40.

Then, the potential of the wiring WLb is set to a high level and the transistor 41 is turned on. Accordingly, the potential Vwb of the wiring BL is supplied to the node FNb as illustrated in FIG. That is, data is written in the circuit 40.

Next, in the period T13, the wiring WLb is set at a low level and the transistor 41 is turned off. Accordingly, the node FNb is in a floating state and the potential of the node FNb is held even if the potential of the wiring BL changes.

By the above operation, data writing to the circuits 30 and 40 is performed. Note that the operation in the period T12 may be performed before the period T11 and the data writing to the circuit 40 may be performed before the data writing to the circuit 30.

Next, in a period T21, the potential of the wiring BL is precharged to a high level and then the wiring BL is brought into a floating state. Here, the wiring WLc is at a high level and the transistor 43 is on, so that the potential of the wiring SBL is also precharged to a high level.

Next, in the period T22, the potential of the wiring WLCa is set at a low level. Accordingly, the potential of the node FNa is lowered to the potential Vwa supplied to the node FNa in the period T11, for example. Further, a low-level potential is supplied to the wiring SL as a power supply potential. Therefore, the potentials of the wiring BL and the wiring SBL which are precharged to a high level fall until the transistor 51 is turned off. Accordingly, as illustrated in FIG. 5A, a 16-value potential corresponding to the potential of the node FNa is output to the wiring BL as the read potential Vra. Therefore, 16-value data can be read from the circuit 30.

Next, in the period T23, the potential of the wiring BL is set at a low level (here, the ground potential V _GND ). In addition, the potential of the wiring WLa is set at a high level and the transistor 31 is turned on. Accordingly, as illustrated in FIG. 5B, a low-level potential is supplied from the wiring BL to the node FNa through the wiring SBL and the potential of the node FNa is reset to a low level.

Next, in the period T24, the wiring WLc is set at a low level and the transistor 43 is turned off. Further, the wiring WLb is set to a high level and the transistor 41 is turned on. Accordingly, as illustrated in FIG. 6A, the node FNa and the node FNb are brought into a conductive state through the wiring SBL, and the charge accumulated in the node FNb is distributed to the node FNa. As a result, the data stored in the circuit 40 is transferred to the circuit 30.

Note that, as described above, the potential of the node FNa rises and the potential of the node FNb falls due to the charge distribution. The potential of the node FNa after the charge held in the node FNb is distributed to the node FNa is represented as Vwb ′.

Next, in the period T25, the potentials of the wirings WLa and WLb are set at a low level and the potential of the wiring WLc is set at a high level, so that the transistors 31 and 41 are turned off and the transistor 43 is turned on. After precharging the potential of the wiring BL to a high level, the wiring BL is brought into a floating state. Here, since the transistor 43 is on, the potential of the wiring SBL is also precharged to a high level. In addition, the potential of the wiring WLCa is set to a high level and the potential of the node FNa is set to a potential which turns off the transistor 51 regardless of the potential Vwb ′.

Next, in the period T26, the potential of the wiring WLCa is set at a low level. As a result, the potential of the node FNa is lowered to, for example, the potential Vwb '. Further, a low-level potential is supplied to the wiring SL as a power supply potential. Therefore, the potentials of the wiring BL and the wiring SBL which are precharged to a high level fall until the transistor 51 is turned off. Thus, as illustrated in FIG. 6B, a 16-value potential corresponding to the potential of the node FNa is output to the wiring BL as the read potential Vrb. Therefore, the 16-valued data transferred from the circuit 40 to the circuit 30 can be read.

By the above operation, the multi-valued data stored in the memory cell 20 can be written and read.

<Distribution of charges>
Details of charge distribution from the node FNb to the node FNa shown in the period T24 of FIG. 3 and FIG. 6A will be described.

FIG. 7A shows the distribution of the write potentials Vwa and Vwb supplied to the wiring BL. Note that FIG. 7A illustrates a case where 4-bit data is stored in each of the nodes FNa and FNb.

The write potentials Vwa and Vwb corresponding to 4-bit data can be represented by 16-value potential levels as shown in FIG. The 16-valued potential level corresponds to 4-bit data “0000” to “1111”.

As described above, the data written in the node FNb is read by distributing the charges to the node FNa. Here, a circuit diagram showing the capacitor 42 (capacitance value C1), the capacitor 32 (capacitance value C2), the transistor 31, and the transistor 41 is illustrated in FIG. The transistors 31 and 41 are shown as switches here. When the transistor 41 is off, the potential V1 = Vwb is held in the node FNb and the potential V2 = V _GND which is a reset potential is held in the node FNa.

After that, when the transistor 41 is turned on, the node FNa and the node FNb are connected as illustrated in FIG. 7C and charge is distributed. Note that FIG. 7C corresponds to the circuit diagram of the memory cell 20 in FIG. 6A. Then, the potential V3 of the nodes FNa and FNb after the charge distribution is V3 = (C1 · V1) / (C1 + C2). The potential V3 corresponds to the potential Vwb ′ in FIG. 6A, and the potential Vwb ′ is a potential lower than the potential Vwb.

Here, by setting the capacitance value C1 to be larger than the capacitance value C2, it is possible to suppress a decrease in potential due to charge distribution. That is, by making the capacitance value of the capacitance element 42 larger than that of the capacitance element 32, it is possible to suppress the fall of the potential from the potential Vwb to the potential Vwb ′ when the charge is distributed from the node FNb to the node FNa. . Therefore, the area of the electrode of the capacitive element 42 is preferably larger than the area of the electrode of the capacitive element 32. Alternatively, the thickness of the dielectric of the capacitor 42 is preferably less than the thickness of the dielectric of the capacitor 32.

In FIG. 7D, the potential Vra (solid line in the drawing) of the wiring BL when the data stored in the circuit 30 is read and the wiring when the data transferred from the circuit 40 to the circuit 30 is read. The potential Vrb of BL (broken line in the figure) is shown. When the write potential Vwa and the write potential Vwb are at the same level, as shown in FIG. 7D, a difference (ΔVr) occurs between the read potential Vra and the read potential Vrb. Further, the higher the potential Vwb, the larger the value of ΔVr. When the capacitance value C1 is larger than the capacitance value C2, it is preferable to design so that the voltage difference ΔV shown in FIG. 7D is small enough to discriminate multi-valued data.

Alternatively, the write potential Vwb may be higher than the write potential Vwa. For example, even if the distribution of the write potential Vwa and the distribution of the read potential Vra are the same (FIG. 8A), the distribution of the write potential Vwb and the distribution of the read potential Vrb are different. Therefore, as shown in FIG. 8B, the write potential Vwb is preferably set higher than the write potential Vwa. As a result, even when the read potential Vrb is lower than the write potential Vwb due to the charge distribution, it is possible to reduce the difference in distribution between the read potential Vra and the read potential Vrb.

The memory cell 20 may be designed by combining the configuration shown in FIG. 7 and the configuration shown in FIG.

Further, by using OS transistors as the transistors 31 and 41, leakage of charges at the nodes FNa and FNb can be suppressed. Therefore, the width of the distribution of the write potential and the read potential shown in FIGS. 7 and 8 can be narrowed and the peak can be sharpened. As a result, the interval between the multivalued data stored in the circuits 30 and 40 can be narrowed, and the number of data stored can be increased. Since the OS transistor has higher withstand voltage than the Si transistor, the range of potential held in the nodes FNa and FNb can be widened. Therefore, the number of data stored in the circuits 30 and 40 can be increased.

When OS transistors are used for the transistors 31, 41, and 43, it is preferable that the channel width W / channel length L of the transistor 43 be larger than the W / L of the transistors 31 and 41. Accordingly, the current supply capacity of the transistor 43 can be improved and high-speed reading can be performed. Further, by setting the W / L of the transistors 31 and 41 smaller than the W / L of the transistor 43, the off-state current of the transistors 31 and 41 can be suppressed small and the potentials of the nodes FNa and FNb can be held for a long time. .

As described above, by providing the memory cell 20 with the plurality of holding portions 21, it is possible to provide a semiconductor device capable of storing multilevel data. Further, by using an OS transistor for the holding portion 21, a charge accumulated in the holding portion 21 can be held for a long time, a semiconductor device with high reliability and low power consumption can be provided.

Note that one embodiment of the present invention is not limited to the above structure. That is, since various aspects of the invention are described in this embodiment, one aspect of the present invention is not limited to a particular aspect. For example, although an example of a semiconductor device in which the memory cell 20 is provided with the plurality of holding portions 21 is described as one embodiment of the present invention, one embodiment of the present invention is a memory device according to circumstances or circumstances. The cell 20 may have a configuration in which one holding unit 21 is provided. In addition, although an example in which multi-valued data is stored in the memory cell 20 is described as one embodiment of the present invention, one embodiment of the present invention is provided in the memory cell 20 depending on the case or circumstances. The value data may be stored. Although an example of application to a memory cell is shown as one embodiment of the present invention, one embodiment of the present invention is not limited to this. For example, depending on the case or circumstances, one embodiment of the present invention may be applied to a circuit having another function. Alternatively, for example, in some cases or circumstances, one embodiment of the present invention may not be applied to a memory cell. In addition, as an embodiment of the present invention, in the transistor or the like in the holding portion 21, an example of the case where a channel formation region, a source drain region, or the like of the transistor includes an oxide semiconductor is shown. It is not limited to this. Depending on the case or conditions, the various transistors, the channel formation region of the transistor, the source / drain region of the transistor, or the like in one embodiment of the present invention may include various semiconductors. Depending on circumstances or conditions, various transistors, channel formation regions of transistors, source / drain regions of transistors, and the like in one embodiment of the present invention include, for example, silicon, germanium, silicon germanium, silicon carbide, gallium. At least one of arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be included. Alternatively, for example, in some cases or in some circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source / drain region of the transistor, or the like do not include an oxide semiconductor. Good.

This embodiment can be combined with any of the other embodiments as appropriate. Therefore, the content described in this embodiment (may be part of the content) is different from the content described in the embodiment (may be part of the content), and / or one or more other content. Application, combination, replacement, or the like can be performed on the content (may be part of the content) described in the embodiment. Note that the content described in the embodiments means the content described using various drawings or the content described in the specification in each embodiment. In addition, a diagram (or part of it) described in one embodiment is another part of the diagram, another diagram (or part) described in the embodiment, and / or one or more. More drawings can be configured by combining the drawings (which may be a part) described in another embodiment of 1. This also applies to the following embodiments.

(Embodiment 2)
In this embodiment, modifications of the memory cell 20 according to one embodiment of the present invention will be described.

<Modification 1 of memory cell>
FIG. 9 shows a modification of the memory cell 20. The memory cell 20 illustrated in FIG. 9A is different from that in FIG. 2A in that one of a source and a drain of the transistor 43 and one of a source and a drain of the transistor 51 are connected to different wirings. . One of a source and a drain of the transistor 43 is connected to the wiring WBL, and one of a source and a drain of the transistor 51 is connected to the wiring RBL. In this case, writing of data to the memory cell 20 and reading of data from the memory cell 20 are performed by different wirings.

The memory cell 20 illustrated in FIG. 9B is different from that in FIG. 2A in that the transistor 52 is provided between the transistor 51 and the wiring SBL. The gate of the transistor 52 is connected to the wiring WLCa, one of the source and the drain is connected to the wiring SBL, and the other of the source and the drain is connected to one of the source and the drain of the transistor 51. In this case, the timing of reading data is controlled by the transistor 52. Note that the transistor 52 may be provided between the transistor 51 and the wiring SL.

The memory cell 20 illustrated in FIG. 9C is different from FIG. 2A in that a plurality of transistors 31, a capacitor 32, a transistor 41, a capacitor 42, and a transistor 51 are provided. In addition, the memory cell 20 illustrated in FIG. 9D is different from FIG. 2A in that a plurality of transistors 41 and a plurality of capacitors 42 are provided.

As shown in FIGS. 9C and 9D, by providing the memory cell 20 with three or more nodes FN, the number of data that can be stored in one memory cell 20 can be increased. Specifically, in FIGS. 9C and 9D, if the potentials stored in the four nodes FN are i-value, j-value, k-value, and l-value (k and l are natural numbers), the memory cell 20 can store data of i × j × k × l values. That is, when a-bit, b-bit, c-bit, and d-bit (c and d are natural numbers) data are stored in the four nodes FN, respectively, a + b + c + d-bit data can be read.

Note that FIG. 9C illustrates a structural example in which the transistor 31, the capacitor 32, the transistor 41, the capacitor 42, and the transistor 51 are provided, but three or more may be provided. Although FIG. 9D illustrates a structural example in which three transistors 41 and three capacitor elements 42 are provided, two transistors may be provided or three or more capacitors may be provided.

<Modification 2 of Memory Cell>
FIG. 10 shows another modification of the memory cell 20. The memory cell 20 illustrated in FIG. 10 is different from FIG. 2A in that the transistors 31, 41, and 43 each have a pair of gates. That is, the transistors 31, 41 and 43 have back gates.

In the memory cell 20 illustrated in FIG. 10A, the back gate of the transistor 31 is connected to the gate of the transistor 31, the back gate of the transistor 41 is connected to the gate of the transistor 41, and the back gate of the transistor 43 is connected to the transistor 43. It is connected to the gate. In the memory cell 20 illustrated in FIG. 10B, the back gates of the transistors 31, 41, and 43 are connected to the wiring BG. Note that a fixed potential is supplied to the wiring BG.

Here, when a certain transistor T has a pair of gates which sandwich a semiconductor film therebetween like the transistors 31, 41, and 43, the signal A is applied to one gate and the signal A is applied to the other gate. May be given a fixed potential Vb.

The signal A is, for example, a signal for controlling the conducting state or the non-conducting state. The signal A may be a digital signal that takes two types of potentials, the potential V1 or the potential V2 (V1> V2). For example, the potential V1 can be a high power supply potential and the potential V2 can be a low power supply potential (ground potential or the like). The signal A may be an analog signal.

The fixed potential Vb is, for example, a potential for controlling one threshold voltage VthA of the transistor T. The fixed potential Vb may be the potential V1 or the potential V2. In this case, there is no need to separately provide a potential generation circuit for generating the fixed potential Vb, which is preferable. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. The threshold voltage VthA may be increased by decreasing the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is 0 V can be reduced, and the leakage current of the circuit including the transistor T can be reduced in some cases. For example, the fixed potential Vb may be lower than the low power supply potential. In some cases, the threshold voltage VthA can be lowered by increasing the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is VDD may be improved, and the operation speed of the circuit including the transistor T may be improved in some cases. For example, the fixed potential Vb may be higher than the low power supply potential.

The signal A may be supplied to one gate of the transistor T and the signal B may be supplied to the other gate. The signal B is, for example, a signal for controlling the conductive state or the non-conductive state of the transistor T. The signal B may be a digital signal that takes two types of potentials, the potential V3 and the potential V4 (V3> V4). For example, the potential V3 can be a high power supply potential and the potential V4 can be a low power supply potential. The signal B may be an analog signal.

When both the signal A and the signal B are digital signals, the signal B may be a signal having the same digital value as the signal A. In this case, the on-current of the transistor T can be improved and the operation speed of the circuit including the transistor T can be improved in some cases. At this time, the potential V1 of the signal A may be different from the potential V3 of the signal B. The potential V2 of the signal A may be different from the potential V4 of the signal B. For example, when the gate insulating layer corresponding to the gate to which the signal B is input is thicker than the gate insulating layer corresponding to the gate to which the signal A is input, the potential amplitude (V3-V4) of the signal B is It may be larger than the potential amplitude (V1-V2). By doing so, in some cases, the effect of the signal A and the effect of the signal B on the conductive state or the non-conductive state of the transistor T can be made approximately the same.

When both the signal A and the signal B are digital signals, the signal B may have a digital value different from that of the signal A. In this case, the transistor T can be controlled separately by the signal A and the signal B, and a higher function may be realized in some cases. For example, when the transistor T is an n-channel type, it is conductive only when the signal A has the potential V1 and the signal B has the potential V3, or the signal A has the potential V2 and the signal B. In the case where the transistor is in the non-conducting state only when V is the potential V4, the function of the NAND circuit, the NOR circuit, or the like may be realized by one transistor. Further, the signal B may be a signal for controlling the threshold voltage VthA. For example, the signal B may be a signal whose potential is different between a period in which a circuit including the transistor T is operating and a period in which the circuit is not operating. The signal B may be a signal having a different potential depending on the operation mode of the circuit. In this case, the potential of the signal B may not switch as frequently as the signal A.

When both the signal A and the signal B are analog signals, the signal B is an analog signal having the same potential as the signal A, an analog signal obtained by multiplying the potential of the signal A by a constant, or the potential of the signal A is added or subtracted by a constant. It may be an analog signal or the like. In this case, the on-current of the transistor T can be improved and the operation speed of the circuit including the transistor T can be improved in some cases. The signal B may be an analog signal different from the signal A. In this case, the transistor T can be controlled separately by the signal A and the signal B, and a higher function may be realized in some cases.

The signal A may be a digital signal and the signal B may be an analog signal. The signal A may be an analog signal and the signal B may be a digital signal.

The fixed potential Va may be applied to one gate of the transistor T and the fixed potential Vb may be applied to the other gate. When a fixed potential is applied to both gates of the transistor T, the transistor T may be able to function as a resistance element and an element equivalent to the resistance element. For example, when the transistor T is an n-channel type, the effective resistance of the transistor can be reduced (increased) by increasing (decreasing) the fixed potential Va or the fixed potential Vb in some cases. By increasing (decreasing) both the fixed potential Va and the fixed potential Vb, an effective resistance lower (higher) than the effective resistance obtained by the transistor having only one gate may be obtained.

Note that the transistor 51 may have a pair of gates. Each transistor in FIGS. 2B and 9 may also have a pair of gates.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 3)
In this embodiment, an example of a stacked structure of a semiconductor device according to one embodiment of the present invention will be described.

In the above embodiment, a layer having an OS transistor and a layer having a transistor other than the OS transistor can be stacked. In addition, a plurality of layers each including an OS transistor can be stacked. Specifically, the circuit 30, the circuit 40, and the circuit 50 can be stacked in the memory cell 20 of FIG. As a result, the area of the memory cell can be reduced.

A structural example of a semiconductor device in which an OS transistor and a Si transistor are stacked will be described below with reference to FIGS.

<Cross section structure>
A transistor included in the semiconductor device of one embodiment of the present invention can be a Si transistor or an OS transistor. Further, the cross-sectional structure of the semiconductor device can have a structure in which a layer having a Si transistor and a layer having an OS transistor are stacked. Each layer has a plurality of transistors each formed of a semiconductor of the same material.

As an example, as shown in FIG. 11A, the semiconductor device in one embodiment of the present invention includes a layer 61 having a Si transistor (indicated as Si-FET Layer in the drawing) and a layer 62 provided with a wiring (see FIG. It can be provided by stacking in the order of the middle layer, denoted by Wire Layer) and the 33 having an OS transistor (denoted by OS-FET Layer in the figure).

In the schematic view of the cross-sectional structure illustrated in FIG. 11A, the layer 61 having a Si transistor has a Si transistor formed over a single crystal silicon substrate. Note that the Si transistor may be a transistor in which a thin film semiconductor such as silicon or germanium which is amorphous, microcrystalline, polycrystalline, or single crystal is used for a semiconductor layer.

In the schematic view of the cross-sectional structure illustrated in FIG. 11A, the layer 63 having an OS transistor has an OS transistor formed over a planarized insulating surface.

The layer 62 in which wiring is provided in the schematic view of the cross-sectional structure illustrated in FIG. 11A is a wiring for electrically connecting transistors included in the layer 61 including a Si transistor and / or the layer 63 including an OS transistor. Alternatively, it has a wiring for applying a voltage to the transistor. Although the layer 62 in which the wiring is provided is illustrated as a single layer in FIG. 11A, a plurality of layers may be stacked.

Note that the layer 63 including an OS transistor is illustrated as a single layer in FIG. 11A, but may be stacked. In the case of stacking, it can be represented by a schematic view of a cross-sectional structure shown in FIG.

FIG. 11B illustrates a two-layer structure including layers 63_1 and 63_2 each including an OS transistor. In the schematic view of the cross-sectional structure illustrated in FIG. 11B, the layers 63_1 and 63_2 each including an OS transistor each include an OS transistor formed over a planarized insulating surface. Although an example in which two layers are stacked is shown in FIG. 11B, the number of stacked layers is not limited and may be three or more. Note that the layer 62 provided with a wiring can be provided between the layers 63_1 and 63_2 each including an OS transistor. With this structure, the OS transistors can be electrically connected to each other.

For example, the transistors 31, 41, 43 in FIG. 2 can be OS transistors and the transistor 51 can be Si transistors. When the structure of FIG. 11A is applied to the memory cell 20 of FIG. 2, a layer 61 having a Si transistor has a transistor 51, and a layer 63 having an OS transistor has a transistor 31, 41, or 43. Can be When the structure in FIG. 11B is applied to the memory cell 20 in FIG. 2, the layer 61 including the Si transistor has the transistor 51, the layer 63_1 including the OS transistor has the transistor 31, and the OS The layer 63_2 including a transistor can have a structure including the transistors 41 and 43. Alternatively, the layer 63_3 including an OS transistor may be provided over the layer 63_2 including an OS transistor, and the transistor 43 may be provided in the layer 63_3 including an OS transistor. Alternatively, the transistor 43 can be a Si transistor and can be provided in the layer 61 including a Si transistor like the transistor 51.

By stacking a layer including an OS transistor with a layer including a Si transistor as illustrated in FIGS. 11A and 11B, the circuit area of a memory cell is reduced, that is, the area of a semiconductor device is reduced and downsizing is achieved. Can be planned.

<Si layer / wiring layer>
FIG. 12 illustrates an example of a cross-sectional structure of the layer 61 including the Si transistor and the layer 62 in which wiring is provided, which are described in FIGS. 11A and 11B. In FIG. 12, a cross-sectional structure of the transistor 71 included in the layer 61 including the Si transistor will be described. The cross-sectional structure of the transistor 71 in FIG. 12 can be applied to, for example, the transistor 51 in FIG.

Note that in FIG. 12, a region shown by a broken line A1-A2 shows a structure in the channel length direction of the transistor 71, and a region shown by a broken line A3-A4 shows a structure in the channel width direction of the transistor 71.

In FIG. 12, as the substrate 100 on which the transistor 71 is formed, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, or the like can be used. FIG. 12 illustrates the case where a single crystal silicon substrate is used as the substrate 100.

Further, the transistor 71 is electrically isolated by an element isolation method. As an element isolation method, a trench isolation method (STI method: Shallow Trench Isolation) or the like can be used. FIG. 12 illustrates the case where the transistor 71 is electrically isolated by using the trench isolation method. Specifically, in FIG. 12, an insulating material containing silicon oxide or the like is embedded in a trench formed in the substrate 100 by etching or the like, and then the insulating material is partially removed by etching or the like. The case where the transistor 71 is isolated by the element isolation region 101 is illustrated.

Further, an impurity region 102 and an impurity region 103 of the transistor 71 and a channel formation region 104 sandwiched between the impurity region 102 and the impurity region 103 are provided in a convex portion of the substrate 100 which exists in a region other than the trench. . Further, the transistor 71 includes an insulating film 105 which covers the channel formation region 104 and a gate electrode 106 which overlaps with the channel formation region 104 with the insulating film 105 provided therebetween.

In the transistor 71, the side portion and the upper portion of the projection in the channel formation region 104 and the gate electrode 106 overlap with each other with the insulating film 105 provided therebetween, so that the transistor 71 has a wide range including the side portion and the top portion of the channel formation region 104. Carrier flows. Therefore, the amount of carrier movement in the transistor 71 can be increased while suppressing the occupied area of the transistor 71 over the substrate to be small. As a result, the transistor 71 has a larger on-current and higher field-effect mobility. In particular, when the length of the convex portion in the channel forming region 104 in the channel width direction (channel width) is W and the film thickness of the convex portion in the channel forming region 104 is T, it corresponds to the ratio of the film thickness T to the channel width W. When the aspect ratio is high, the range in which carriers flow becomes wider, so that the on-state current of the transistor 71 can be increased and the field-effect mobility can be further increased.

Note that in the case of the transistor 71 using a bulk semiconductor substrate, the aspect ratio is preferably 0.5 or more, more preferably 1 or more.

An insulating film 111 is provided over the transistor 71. An opening is formed in the insulating film 111. Then, in the opening, conductive films 112 and 113 which are electrically connected to the impurity regions 102 and 103, respectively, and a conductive film 114 which is electrically connected to the gate electrode 106 are provided. Has been formed.

The conductive film 112 is electrically connected to the conductive film 116 formed over the insulating film 111, and the conductive film 113 is electrically connected to the conductive film 117 formed over the insulating film 111. Therefore, the conductive film 114 is electrically connected to the conductive film 118 formed over the insulating film 111.

Note that in FIG. 12, the layer 62 provided with the wiring illustrated in FIGS. 11A and 11B corresponds to the conductive films 116, 117, and 118. Note that the layer 62 provided with a wiring can be stacked by sequentially forming an insulating film, an opening provided in the insulating film, and a conductive film provided in a region including the opening.

<Layer having OS transistor>
Next, FIGS. 13A and 13B show an example of a cross-sectional structure of the layer 63 including the OS transistor, which is described in FIGS. 11A and 11B. In FIG. 13A, a cross-sectional structure of the transistor 72 included in the layer 63 including an OS transistor will be described. The cross-sectional structure of the transistor 72 in FIG. 13 can be applied to the transistors 31, 41, 43, and the like in FIG. 2, for example.

Note that, in FIGS. 13A and 13B, similarly to FIG. 12, a structure in the channel length direction of the transistor 72 is illustrated in a region indicated by a broken line A1-A2, and a transistor is illustrated in a region indicated by a broken line A3-A4. The structure of 72 in the channel width direction is shown.

An insulating film 121 having a blocking effect which prevents diffusion of oxygen, hydrogen, and water is provided over the insulating film 120 which is provided above the layer 62 in which the wiring described in FIGS. 11A and 11B is provided. ing. The insulating film 121 has a higher blocking effect as the density and density are higher, and as the number of dangling bonds is smaller and the insulating film 121 is chemically stable. As the insulating film 121 which has a blocking effect of preventing diffusion of oxygen, hydrogen, and water, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like is used. be able to. As the insulating film 121 which has a blocking effect of preventing diffusion of hydrogen and water, for example, silicon nitride, silicon nitride oxide, or the like can be used.

The insulating film 122 is provided over the insulating film 121, and the transistor 72 is provided over the insulating film 122.

The transistor 72 includes a semiconductor film 130 including an oxide semiconductor, a conductive film 132 and a conductive film 133 which function as a source electrode or a drain electrode, which are electrically connected to the semiconductor film 130, over the insulating film 122, and a semiconductor film. A gate insulating film 131 which covers 130 and a gate electrode 134 which overlaps with the semiconductor film 130 with the gate insulating film 131 interposed therebetween are provided.

Note that in FIG. 13A, the transistor 72 needs to include at least the gate electrode 134 on one side of the semiconductor film 130; however, a gate electrode which overlaps with the semiconductor film 130 with the insulating film 122 interposed therebetween is further included. You may have.

In the case where the transistor 72 has a pair of gate electrodes, a signal for controlling a conductive state or a non-conductive state is given to one gate electrode and a voltage is given to the other gate electrode from another wiring. It may be in a state of being kept. In this case, a voltage of the same height may be applied to the pair of gate electrodes, or a fixed voltage such as a ground voltage may be applied only to the other gate electrode. By controlling the voltage applied to the other gate electrode, the threshold voltage of the transistor can be controlled.

Further, FIG. 13A illustrates the case where the transistor 72 has a single-gate structure including one channel formation region corresponding to one gate electrode 134. However, the transistor 72 may have a multi-gate structure in which one active layer has a plurality of channel formation regions by having a plurality of gate electrodes electrically connected to each other.

In addition, as illustrated in FIG. 13A, the transistor 72 illustrates the case where the semiconductor film 130 includes the oxide semiconductor films 130 a to 130 c sequentially stacked over the insulating film 122. However, in one embodiment of the present invention, the semiconductor film 130 included in the transistor 72 may be formed using a single metal oxide film.

Note that when the oxide semiconductor film 130b is an In-M-Zn oxide (M is Ga, Y, Zr, La, Ce, or Nd), a metal is used as a target in forming the oxide semiconductor film 130b. Assuming that the atomic ratio of elements is In: M: Zn = x ₁ : y ₁ : z _{1 ,} x ₁ / y ₁ is ⅓ or more and 6 or less, and further 1 or more and 6 or less, and z ₁ / y ₁ is preferably ⅓ or more and 6 or less, and more preferably 1 or more and 6 or less. Note that when z ₁ / y ₁ is 1 or more and 6 or less, a CAAC-OS (CAxis Aligned Crystalline Oxide Semiconductor) film is easily formed as the oxide semiconductor film 130b. In: M: Zn = 1: 1: 1 and In: M: Zn = 3: 1: 2 are typical examples of the atomic ratio of the target metal element. Details of the CAAC-OS film will be described later.

Note that when the oxide semiconductor films 130a and 130c are In-M-Zn oxides (M is Ga, Y, Zr, La, Ce, or Nd), it is used for forming the oxide semiconductor films 130a and 130c. In the target, if the atomic ratio of the metal elements is In: M: Zn = x ₂ : y ₂ : z _{2 , then} x ₂ / y ₂ <x ₁ / y ₁ and z ₂ / y ₂ is 1 It is preferably / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. Note that when z ₂ / y ₂ is 1 to 6 inclusive, CAAC-OS films are easily formed as the oxide semiconductor films 130a and 130c. As typical examples of the atomic ratio of the target metal element, In: M: Zn = 1: 3: 2, In: M: Zn = 1: 3: 4, In: M: Zn = 1: 3: 6, etc. There is.

The insulating film 122 is preferably an insulating film having a function of supplying oxygen to the oxide semiconductor films 130a to 130c by heating. The insulating film 122 preferably has few defects. Typically, the density of spins having g = 2.001 derived from a dangling bond of silicon, which is obtained by ESR (Electron Spin Resonance) measurement, is 1 It is preferably × 10 ¹⁸ spins / cm ³ or less.

The insulating film 122 has a function of supplying oxygen to the oxide semiconductor films 130a to 130c by heating, and thus is preferably an oxide, for example, aluminum oxide, magnesium oxide, silicon oxide, or silicon oxynitride. , Silicon nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like can be used. The insulating film 122 can be formed by a plasma CVD (Chemical Vapor Deposition) method, a sputtering method, or the like.

Note that in this specification, oxynitride refers to a material whose content of oxygen is higher than that of nitrogen as its composition, and nitride oxide refers to a material whose content of nitrogen is higher than that of oxygen as its composition. Point to.

Note that in the transistor 72 illustrated in FIG. 13A, an end portion of the oxide semiconductor film 130b in which a channel region is formed, which does not overlap with the conductive film 132 and the conductive film 133, in other words, the conductive film 132 is included. The gate electrode 134 and the end portion located in a region different from the region where the conductive film 133 is located overlap with each other. When the end portion of the oxide semiconductor film 130b is exposed to plasma by etching for forming the end portion, chlorine radicals, fluorine radicals, and the like generated from an etching gas are separated from metal elements included in the oxide semiconductor. Easy to combine. Therefore, oxygen bound to the metal element is easily released at the edge portion of the oxide semiconductor film, so that oxygen vacancies are formed and n-type is easily formed. However, in the transistor 72 illustrated in FIG. 13A, the edge of the oxide semiconductor film 130b, which does not overlap with the conductive film 132 and the conductive film 133, and the gate electrode 134 overlap with each other; thus, the voltage of the gate electrode 134 is controlled. Thus, the electric field applied to the end can be controlled. Therefore, the current flowing between the conductive film 132 and the conductive film 133 through the end portion of the oxide semiconductor film 130b can be controlled by the voltage applied to the gate electrode 134. Such a structure of the transistor 72 is called a Surrounded Channel (s-channel) structure.

Specifically, in the case of the s-channel structure, when a voltage which turns off the transistor 72 is applied to the gate electrode 134, the off-state current flowing between the conductive film 132 and the conductive film 133 through the end portion is changed. It can be kept small. Therefore, in the transistor 72, the channel length is shortened in order to obtain a large on-state current, and as a result, even if the length between the conductive film 132 and the conductive film 133 at the end portion of the oxide semiconductor film 130b is shortened, the transistor 72 The off current of 72 can be suppressed small. Therefore, by shortening the channel length of the transistor 72, a large on-current can be obtained in the conductive state and an off-current can be suppressed to be small in the non-conductive state.

Further, specifically, in the case of the s-channel structure, when a voltage which makes the transistor 72 conductive is applied to the gate electrode 134, it flows between the conductive film 132 and the conductive film 133 through the end portion. The current can be increased. The current contributes to the increase of the field effect mobility and the on-state current of the transistor 72. Then, since the edge portion of the oxide semiconductor film 130b and the gate electrode 134 overlap with each other, the region where carriers flow in the oxide semiconductor film 130b is not limited to the vicinity of the interface of the oxide semiconductor film 130b which is close to the gate insulating film 131. Since carriers flow in a wide range of the oxide semiconductor film 130b, the amount of carrier movement in the transistor 72 is increased. As a result, the on-state current of the transistor 72 is increased and the field effect mobility is increased, and the field effect mobility is typically 10 cm ² / V · s or more, further 20 cm ² / V · s or more. Note that the field-effect mobility here is not an approximate value of mobility as a physical property value of an oxide semiconductor film but an index of current driving force in a saturation region of a transistor, which is apparent field-effect mobility. .

Note that in the description of FIG. 13A, the semiconductor film 130 included in the transistor 72 is illustrated as a structure including the oxide semiconductor films 130a to 130c which are sequentially stacked. The semiconductor film 130 may have a structure as shown in FIG. 13B as another structure. As illustrated in FIG. 13B, the oxide semiconductor film 130c included in the semiconductor film 130 may be provided between the conductive film 132 and the conductive film 133 and the gate insulating film 131.

<Layered structure>
Next, in FIGS. 14 to 16, a cross-sectional structure of the layer including the Si transistor described in FIG. 12, the layer including the wiring, and the layer including the OS transistor described in FIG. 13A is stacked. An example is shown.

FIG. 14 illustrates an example of a cross-sectional structure of the schematic view illustrated in FIG.

Note that, in FIG. 14, as in FIGS. 12 and 13A, the structure in the channel length direction of the transistors 71 and 72 is shown in a region shown by a broken line A1-A2, and the region shown by a broken line A3-A4 is shown in FIG. The structure in the channel width direction of the transistors 71 and 72 is shown.

Note that in one embodiment of the present invention, as illustrated in FIG. 14, the channel length direction of the transistor 71 and the channel length direction of the transistor 72 do not necessarily match.

Note that in FIG. 14, openings are provided in the insulating films 120 to 122 in order to electrically connect the transistors 71 and 72 to each other. The conductive film 133 provided in the opening is connected to the conductive film 118 in the opening.

In the cross-sectional structure illustrated in FIG. 14, as described in the description of FIG. 11A, the transistor 72 having a channel formation region in the oxide semiconductor film is formed over the transistor 71 having a channel formation region in the single crystal silicon substrate. Form. With the structure in FIG. 14, the channel formation region of the transistor 72 and the channel formation region of the transistor 71 can be provided so as to overlap with each other. Therefore, in the semiconductor device having the memory cell having the above structure, the layout area can be reduced.

Note that in the case where there are a plurality of transistors 72 provided in the layer 63 having an OS transistor, they may be provided in the same layer or different layers.

For example, in the case where the transistor 72 provided in the layer 63 including an OS transistor is provided in the same layer, the structure illustrated in FIG. 15 can be used. In the case where the transistor 72 provided in the layer 63 having an OS transistor is provided in a different layer, the layer 63_1 having an OS transistor and the layer 63_2 are separated and stacked with the layer 62 provided with a wiring provided therebetween, as illustrated in FIG. It can be configured.

With the cross-sectional structure illustrated in FIGS. 15A and 15B, the number of stacked layers can be reduced because one layer 63 including an OS transistor may be provided even if the number of OS transistors increases. For example, in FIG. 15, the transistor 72A and the transistor 72B can be manufactured at one time. Therefore, the number of steps for manufacturing a semiconductor device can be reduced.

Note that FIG. 15 illustrates the structures of the transistors 71, 72A, and 72B in the channel length direction. The structure in the channel width direction is similar to the structure shown in FIG. 14, and the above structure may be referred to.

When the configuration of the cross-sectional structure of FIG. 15 is applied to the memory cell 20 in FIG. 2, for example, the transistors 31 and 41 can be formed in the layer 63 including an OS transistor, like the transistors 72A and 72B. Similarly, the transistor 43 can be formed in the layer 63 including an OS transistor. Therefore, the manufacturing cost of the semiconductor device can be reduced.

Further, with the cross-sectional structure illustrated in FIG. 16, even if the number of OS transistors is increased, the layers 63_1 and 63_2 including the OS transistors may be provided in a plurality of layers, so that the circuit area is increased even if the number of transistors is increased. Can be suppressed. Therefore, the chip area of the semiconductor device can be reduced and the size can be reduced.

Note that FIG. 16 illustrates structures of the transistors 71, 72C, and 72D in the channel length direction. The structure in the channel width direction is similar to the structure shown in FIG. 14, and the above structure may be referred to.

With the cross-sectional structure illustrated in FIG. 16, an OS transistor having different thicknesses, film qualities, and the like can be formed between the layers 63_1 and 63_2 having the OS transistors in different layers. Therefore, transistors having different characteristics can be manufactured separately. For example, a transistor in which the gate insulating film is thinned to have high switching characteristics and a transistor in which the gate insulating film is thick to have high withstand voltage can be stacked. Therefore, high performance of the semiconductor device can be achieved.

When the configuration of the cross-sectional structure of FIG. 16 is applied to the memory cell 20 in FIG. 2, for example, the transistor 31 is formed in the layer 63_1 having an OS transistor like the transistor 72C, and the transistor 41 is formed in the same manner as the transistor 72D. It can be formed in the layer 63_2 having a transistor. Similarly, the transistor 43 can be formed in the layer 63_2 including the OS transistor.

Further, in FIG. 16, a layer 63 having an OS transistor can be further stacked. For example, the layers 63_3 and 63_4 each including an OS transistor can be sequentially stacked over the layer 63_2 including an OS transistor. In that case, the transistor 41_2 in FIG. 9D can be provided in the layer 63_3 including the OS transistor and the transistor 41_3 can be provided in the layer 63_4 including the OS transistor.

<Specific example>
FIG. 17 shows a configuration example of the memory cell 20 when the circuit 30, the circuit 40, and the circuit 50 in FIG. 2 are laminated in order. Note that FIG. 17 illustrates the positions of the wirings WLa, WLb, WLc, the wirings WLCa, WLCb, the transistors 31, 41, 43, 51, and the capacitors 32, 42 in FIG. 2. In addition, FIG. 17 illustrates a structure in which the transistors 31, 41, and 43 have back gates and these back gates are connected to the wiring BG (see FIG. 10B). Note that the transistors 31, 41, and 43 can be OS transistors, and the transistor 51 can be a Si transistor.

In the cross-sectional view of the memory cell 20 illustrated in FIG. 17, the transistor 51, the transistor 31, and the transistors 41 and 43 are provided in different layers and stacked. With such a structure, the circuit area of the memory cell having a plurality of holding portions can be reduced and the semiconductor device can be downsized.

In the cross-sectional view shown in FIG. 17, the conductive layers are arranged in parallel to form the capacitive elements 32 and 42, but another structure may be used. For example, as shown in FIG. 18, a conductive layer may be arranged in a trench shape to form the capacitive elements 32 and 42. With such a configuration, the capacitance values of the capacitive elements 32 and 42 can be improved.

17 and 18 show a configuration in which the circuits 30 and 40 are laminated one layer each on the circuit 50, but the circuits 30 and 40 may each be laminated two or more layers. As a result, it is possible to mount three or more nodes FN in the memory cell 20, as shown in FIGS. 9C and 9D, while suppressing an increase in the area of the memory cell 20. Therefore, the amount of data that can be stored in the memory cell 20 can be increased.

17 and 18 show a configuration in which the circuit 30 and the circuit 40 are formed in different layers, the circuit 30 and the circuit 40 may be formed in the same layer on the circuit 50. That is, the transistors 41 and 43 may be formed in the same layer as the transistor 31, and the capacitor 42 may be formed in the same layer as the capacitor 32.

17 and 18 show the structure in which the transistor 43 is provided in the same layer as the transistor 41, the transistor 43 may be provided in the same layer as the transistor 31 or the transistor 51. They may be provided in the same layer. When the transistor 31 and the transistor 43 are provided in the same layer, the transistor 43 can be an OS transistor like the transistor 31. When the transistor 43 and the transistor 51 are provided in the same layer, the transistor 43 can be a Si transistor like the transistor 51.

As described above, by stacking the transistors included in the memory cell 20, the area of the memory cell 20 can be reduced.

The structure and the method described in this embodiment can be combined with structures and methods described in other embodiments as appropriate.

(Embodiment 4)
In this embodiment, a memory device and a computer each including the semiconductor device according to one embodiment of the present invention will be described.

<Structure example of storage device>
FIG. 19 is a block diagram illustrating a structural example of a memory device including the semiconductor device 10 described in the above embodiment.

A memory device 300 illustrated in FIG. 19 includes a memory cell array 310 including a plurality of memory cells 20 described in the above embodiment, a row selection driver 320, a column selection driver 330, and an A / D converter 340. Note that the memory device 300 includes the memory cells 20 arranged in a matrix of n rows and m columns. In addition, in FIG. 19, as the wirings WLa, WLb, WLc, the wirings WLCa, WLCb, the wiring BL, and the wiring SL, the wirings WLa [1], WLb [1], WLc [1], and the wiring WLCa [1] in the first row are used. , WLCb [1], second row wirings WLa [2], WLb [2], WLc [2], wirings WLCa [2], WLCb [2], first column wiring BL [1], wiring SL [ 1], the wiring BL [2] and the wiring SL [2] in the second column are shown.

In the memory cell array 310 illustrated in FIG. 19, the memory cells 20 described in the above embodiment are provided in matrix. Note that the description of each configuration of the memory cell 20 is the same as that in FIG. 2, and the description in FIG.

The row selection driver 320 has a function of selectively turning on the transistors 31, 41, 43 (see FIG. 2) of the memory cells 20 in each row, and selectively changes the potential of the node FN of the memory cells 20 in each row. It is a drive circuit having a function. Specifically, it is a circuit which gives a selection signal to the wirings WLa, WLb, and WLc and gives a read signal to the wirings WLCa and WLCb. By including the row selection driver 320, the memory device 300 can selectively write and read data to and from the memory cell 20 for each row.

The column selection driver 330 has a function of selectively writing data to the node FN of the memory cell 20 in each column, a function of precharging the potential of the wiring BL, a function of initializing the potential of the wiring BL, and a wiring BL electrically. It is a drive circuit having a function of making a floating state. Specifically, the wiring BL has a function of giving a write potential corresponding to multi-valued data, a precharge voltage V _precharge , an initialization voltage V _{initial, and the} like through a switch. By including the column selection driver 330, the memory device 300 can select and write data to and from the memory cell 20 for each column. Note that the column selection driver 330 does not need to have all of the above functions, and can be appropriately omitted according to the operation of the memory cell 20.

The A / D converter 340 is a circuit having a function of converting an electric potential of the wiring BL which is an analog value into a digital value and outputting the digital value to the outside. Specifically, it is a circuit having a flash type A / D converter. By including the A / D converter 340, the memory device 300 can output the potential of the wiring SL corresponding to the data read from the memory cell 20 to the outside.

The A / D converter 340 is described as a flash type A / D converter, but a successive approximation type, multi-slope type, or delta sigma type A / D converter may be used.

[Example of row selection driver configuration]
FIG. 20 is a block diagram showing a configuration example of the row selection driver 320 described in FIG.

The row selection driver 320 illustrated in FIG. 20 includes a decoder 321 and a control circuit 322. The control circuit 322 is provided for each row of the wirings WLa, WLb, WLc, and the wirings WLCa, WLCb, and the control circuit 322 in each row is connected to the wirings WLa, WLb, WLc, and the wirings WLCa, WLCb. Note that the wiring WLCb does not need to be connected to the control circuit 322 when a constant potential is supplied to the wiring WLCb.

The decoder 321 is a circuit having a function of outputting a signal for selecting the wirings WLa, WLb, and WLc and the wirings WLCa and WLCb in a specific row. Specifically, it is a circuit to which the address signal Address is input and which selects the control circuit 322 in a predetermined row in accordance with the address signal Address. By including the decoder 321, the row selection driver 320 can select any row and write or read data. Note that the decoder 321 may have a function of selecting any one of the plurality of control circuits 322, or may have a function of selecting two or more.

The control circuit 322 is a circuit having a function of selectively outputting a selection signal, a read signal, or the like to the wirings WLa, WLb, and WLc and the wirings WLCa and WLCb in a specific row selected by the decoder 321. Specifically, the control circuit 322 is a circuit to which the write control signal Write_CONT and the read control signal Read_CONT are input and which selectively outputs a selection signal or a read signal in accordance with the signals. By including the control circuit 322, the row selection driver 320 can select and output the selection signal or the read signal in the row selected by the decoder 321.

[Example of column selection driver configuration]
FIG. 21 is a block diagram showing a configuration example of the column selection driver 330 described with reference to FIG.

The column selection driver 330 illustrated in FIG. 21 includes a decoder 331, a latch circuit 332, a D / A converter 333, a switch circuit 334, a transistor 335, and a transistor 336. The latch circuit 332, the D / A converter 333, the switch circuit 334, the transistor 335, and the transistor 336 are provided for each column. The switch circuit 334, the transistor 335, and the transistor 336 in each column are connected to the wiring BL.

The decoder 331 is a circuit having a function of selecting a column provided with the wiring BL and distributing and outputting input data. Specifically, it is a circuit which receives the address signal Address and the data Data and outputs the data Data to the latch circuit 332 in any row in accordance with the address signal Address. By including the decoder 331, the column selection driver 330 can select an arbitrary column and write data.

The data Data input to the decoder 331 is a-bit digital data. The a-bit digital data is a signal represented by binary data of 1 or 0 for each bit. For example, 2-bit digital data is data represented by 00, 01, 10, 11.

The latch circuit 332 is a circuit having a function of temporarily storing the input data Data. Specifically, the flip-flop circuit receives the latch signal W_LAT and outputs the data Data stored according to the latch signal W_LAT to the D / A converter 333. By including the latch circuit 332, the column selection driver 330 can write data at an arbitrary timing.

The D / A converter 333 is a circuit having a function of converting input digital value data Data into analog value data V _data . Specifically, the D / A converter 333 is a circuit that, when the number of bits of the data Data is 4 bits, converts the data into any of 16 potentials of a plurality of potentials V0 to V15 and outputs it to the switch circuit 334. . By including the D / A converter 333, the column selection driver 330 can set the data to be written in the memory cell 20 to the potential corresponding to the multivalued data.

The V _data output from the D / A converter 333 is data represented by different voltage values. For example, in the case of 2-bit data, it becomes 4-valued data of 0.5V, 1.0V, 1.5V, 2.0V, and can be said to be data represented by any voltage value.

The switch circuit 334 is a circuit having a function of giving input data V _data to the wiring BL and a function of electrically setting the wiring BL to a floating state. Specifically, it is a circuit that includes an analog switch and an inverter, supplies data V _data to the wiring BL under the control of a switch control signal Write_SW, and then turns off the analog switch to electrically float the wiring BL. is there. By including the switch circuit 334, the column selection driver 330 can hold the wiring BL in an electrically floating state after _supplying the data V _data to the wiring BL.

The transistor 335 is a circuit having a function of applying the initialization voltage V _initial to the wiring BL and a function of electrically floating the wiring BL. Specifically, the switch is a switch which applies the initialization voltage V _initial to the wiring BL under the control of the initialization control signal Init_EN and then brings the wiring BL into an electrically floating state. By including the transistor 335, the column selection driver 330 can electrically hold the wiring BL in a floating state after applying the initialization voltage V _initial to the wiring BL.

The transistor 336 is a circuit having a function of applying the precharge voltage V _precharge to the wiring BL and a function of _{bringing the} wiring BL into an electrically floating state. Specifically, it is a switch that _{applies a} precharge voltage V _precharge to the wiring BL under the control of the precharge control signal Pre_EN and then electrically _{brings the} wiring BL into a floating state. By including the transistor 336, the column selection driver 330 can electrically hold the wiring BL in a floating state after _{applying the} precharge voltage V _precharge to the wiring BL.

[Configuration example of A / D converter]
22 is a block diagram showing a configuration example of the A / D converter 340 described with reference to FIG.

The A / D converter 340 illustrated in FIG. 22 includes a comparator 341, an encoder 342, a latch circuit 343, and a buffer 344. The comparator 341, the encoder 342, the latch circuit 343, and the buffer 344 are provided for each column. Further, the buffer 344 in each column outputs the data Dout.

The comparator 341 has a function of comparing the potential of the wiring BL with the level of the potential of the reference voltages Vref0 to Vref14 and determining whether the potential of the wiring BL corresponds to any of multivalued data. Is. Specifically, a plurality of comparators 341 are provided, the potential of the wiring BL and different reference voltages Vref0 to Vref14 are given to each comparator 341, and it is determined whether the potential of the wiring BL is between any of the potentials. It is a circuit to do. By including the comparator 341, the A / D converter 340 can determine whether the potential of the wiring BL corresponds to any of multivalued data.

Note that, as an example, the reference voltages Vref0 to Vref14 shown in FIG. 22 are potentials given when multi-valued data is 4-bit data, that is, 16-valued data.

The encoder 342 is a circuit having a function of generating a multi-bit digital signal based on a signal which is output from the comparator 341 and determines the potential of the wiring BL. Specifically, it is a circuit that performs encoding based on high-level or low-level signals output from the plurality of comparators 341 to generate a digital signal. By including the encoder 342, the A / D converter 340 can convert the data read from the memory cell 20 into digital value data.

The latch circuit 343 is a circuit having a function of temporarily storing input digital value data. Specifically, the flip-flop circuit receives the latch signal LAT and outputs the data stored in accordance with the latch signal LAT to the buffer 344. By including the latch circuit 343, the A / D converter 340 can output data at an arbitrary timing. Note that the latch circuit 343 can be omitted.

The buffer 344 is a circuit having a function of amplifying the data output from the latch circuit 343 and outputting it as the output signal Dout. Specifically, it is a circuit including an even number of inverter circuits. By including the buffer 344, the A / D converter 340 can reduce noise with respect to the digital signal. The buffer 344 can be omitted.
<Computer configuration example>
FIG. 23 is a block diagram showing a configuration example of a computer having the above storage device.

The computer 400 has an input device 410, an output device 420, a central processing unit 430, and a storage device (main memory) 440.

The central processing unit 430 has a control circuit 431, an arithmetic circuit 432, a memory circuit (register) 433, and a memory circuit (cache memory) 434.

The input device 410 has a function of inputting data to the computer 400 from the outside.

The output device 420 has a function of outputting data from the computer 400 to the outside.

The control circuit 431 has a function of outputting a control signal for controlling these devices to the input device 410, the output device 420, and the storage device (main memory) 440.

The arithmetic circuit 432 has a function of performing arithmetic on input data.

The storage device (register) 433 is used for holding data used by the arithmetic circuit 432 for calculation and the like.

The storage device (cache memory) 434 is used to copy frequently used information in the storage device (main memory) 440.

Since the storage device (cache memory) 434 can be accessed faster than the storage device (main memory) 440, the processing speed of the central processing unit 430 is improved. The capacity of the main memory is larger than the capacity of the cache memory, and the capacity of the cache memory is larger than the capacity of the register. The operation of the cache memory and the register is faster than that of the main memory. The memory device 300 in FIG. 19 can be used for any of the memory circuit (register) 433, the memory circuit (cache memory) 434, or the memory device (main memory) 440.

The structure and the method described in this embodiment can be combined with structures and methods described in other embodiments as appropriate.

(Embodiment 5)
In this embodiment, a structural example of an OS transistor which can be used in one embodiment of the present invention will be described.

<Structure example 1>
FIG. 24 shows an example of the structure of the OS transistor. FIG. 24A is a top view illustrating an example of the structure of the OS transistor. 24B is a sectional view taken along the line y1-y2, FIG. 24C is a sectional view taken along the line x1-x2, and FIG. 24D is a sectional view taken along the line x3-x4. Here, the direction of the y1-y2 line may be referred to as the channel length direction, and the x1-x2 line direction may be referred to as the channel width direction. Therefore, FIG. 24B is a diagram showing a cross-sectional structure in the channel length direction of the OS transistor, and FIGS. 24C and 24D are diagrams showing a cross-sectional structure in the channel width direction of the OS transistor. is there. Note that in order to clarify the device structure, some components are omitted in FIG.

The transistor 581 which is an OS transistor is formed over an insulating surface. Here, it is formed on the insulating layer 511. The insulating layer 511 is formed on the surface of the substrate 510. The transistor 581 is covered with the insulating layer 516. Note that the insulating layer 516 can be regarded as a component of the transistor 581. The transistor 581 includes an insulating layer 512, an insulating layer 513, an insulating layer 514, an insulating layer 515, semiconductor layers 521 to 523, a conductive layer 530, a conductive layer 531, a conductive layer 532, and a conductive layer 533. Here, the semiconductor layers 521 to 523 are collectively referred to as a semiconductor region 520.

The conductive layer 530 functions as a gate electrode, and the conductive layer 533 functions as a back gate electrode. The conductive layers 531 and 532 each function as a source electrode or a drain electrode. The insulating layer 511 has a function of electrically separating the substrate 510 and the conductive layer 533. The insulating layer 515 functions as a gate insulating layer, and the insulating layers 513 and 514 function as a gate insulating layer on the back channel side.

Note that the channel length is, for example, in a top view of a transistor, a region where a semiconductor (or a portion of a semiconductor in which a current flows when the transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed. , The distance between the source (source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be set to one value. Therefore, in this specification and the like, the channel length is any one value, a maximum value, a minimum value, or an average value in a region where a channel is formed.

The channel width is, for example, a region where a semiconductor (or a portion of a semiconductor in which a current flows when a transistor is in an on state) and a gate electrode overlap with each other, or a source and a drain face each other in a region where a channel is formed. It is the length of the part where it exists. Note that in one transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of one transistor may not be set to one value. Therefore, in this specification, the channel width is any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, an apparent channel width). May be different from. For example, in a transistor having a three-dimensional structure, the effective channel width becomes larger than the apparent channel width shown in the top view of the transistor, and the effect thereof may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the proportion of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to actually measure the effective channel width. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the semiconductor shape is known. Therefore, it is difficult to measure the effective channel width accurately when the shape of the semiconductor is not known accurately.

Therefore, in this specification, in a top view of a transistor, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as an “enclosed channel width (SCW)”. : Surrounded Channel Width) ". Further, in the present specification, when simply described as channel width, it may indicate an enclosed channel width or an apparent channel width. Alternatively, in this specification, the term “channel width” may mean an effective channel width. The channel length, channel width, effective channel width, apparent channel width, enclosing channel width, etc. can be determined by acquiring a cross-sectional TEM image and analyzing the image. it can.

Note that when the field-effect mobility of the transistor, the current value per channel width, or the like is calculated and obtained, the enclosed channel width may be used in some cases. In that case, the value may be different from the value calculated by using the effective channel width.

As shown in FIGS. 24B and 24C, the semiconductor region 520 has a portion in which the semiconductor layer 521, the semiconductor layer 522, and the semiconductor layer 523 are stacked in this order. The insulating layer 515 covers this laminated portion. The conductive layer 530 overlaps with the stacked portion with the insulating layer 513 provided therebetween. The conductive layer 531 and the conductive layer 532 are provided on a stacked layer including the semiconductor layer 521 and the semiconductor layer 523, and are in contact with an upper surface of this stacked layer and a side surface in the same channel length direction, respectively. The stacked layers of the semiconductor layers 521 and 522 and the conductive layers 531 and 532 are formed by an etching process using the same mask.

The semiconductor layer 523 is formed so as to cover the semiconductor layers 521 and 522 and the conductive layers 531 and 532. The insulating layer 515 covers the semiconductor layer 523. Here, the semiconductor layer 523 and the insulating layer 515 are etched using the same mask.

A conductive layer 530 is formed so as to surround the stacked portion of the semiconductor layers 521 to 523 in the channel width direction with the insulating layer 515 interposed therebetween (see FIG. 24C). Therefore, a gate electric field from the vertical direction and a gate electric field from the side surface direction are also applied to this laminated portion. In the transistor 581, a gate electric field refers to an electric field formed by a voltage applied to the conductive layer 530 (gate electrode layer). Since the gate electric field can electrically surround the entire stacked portion of the semiconductor layers 521 to 523, a channel may be formed in (bulk) over the entire semiconductor layer 522 in some cases. Therefore, the transistor 581 can have a high on-state current. Further, with the s-channel structure, the high frequency characteristics of the transistor 581 can be improved. Specifically, the cutoff frequency can be improved.

Since the s-channel structure can obtain a high on-state current, it can be said that the s-channel structure is suitable for a semiconductor device such as an LSI (Large Scale Integration) that requires a miniaturized transistor. Since the s-channel structure can obtain a high on-state current, it can be said that the s-channel structure is suitable for a transistor which needs to operate at high frequency. A semiconductor device including the transistor can be a semiconductor device which can operate at high frequency.

By miniaturization of the OS transistor, a highly integrated or small semiconductor device can be provided. For example, the OS transistor has a channel length of preferably 10 nm or more and less than 1 μm, more preferably 10 nm or more and less than 100 nm, further preferably 10 nm or more and less than 70 nm, further preferably 10 nm or more and less than 60 nm, further preferably 10 nm or more, It has a region of less than 30 nm. For example, the transistor has a channel width of preferably 10 nm or more and less than 1 μm, more preferably 10 nm or more and less than 100 nm, further preferably 10 nm or more and less than 70 nm, further preferably 10 nm or more and less than 60 nm, further preferably 10 nm or more, 30 nm. Having an area of less than.

Note that an oxide semiconductor such as an In—Ga—Zn oxide has lower heat conductivity than silicon. Therefore, when an oxide semiconductor is used for the semiconductor layer 522, heat is likely to be generated particularly at the drain-side end portion of the channel formation region of the semiconductor layer 522. However, in the transistor 581 illustrated in FIG. 24B, since the conductive layers 531 and 532 overlap with the conductive layer 530, the conductive layers 531 and 532 are provided in the vicinity of the channel formation region of the semiconductor layer 522. Therefore, heat generated in the channel formation region of the semiconductor layer 522 is conducted to the conductive layers 531 and 532. That is, the conductive layers 531 and 532 can be used to dissipate heat in the channel formation region.

Next, details of each layer shown in FIG. 24 will be described.

[substrate]
As the substrate 510, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. The insulator substrate is, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), or a resin substrate. The semiconductor substrate is, for example, a single semiconductor substrate made of silicon, germanium or the like, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide. The semiconductor substrate may be a bulk type or an SOI (Silicon On Insulator) type in which a semiconductor layer is provided on the semiconductor substrate via an insulating region. The conductor substrate is a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like. Alternatively, a substrate including a metal nitride, a substrate including a metal oxide, or the like can be given. Further, a substrate provided with a conductor or a semiconductor on an insulator substrate, a substrate provided with a conductor or an insulator on a semiconductor substrate, a substrate provided with a semiconductor or an insulator on a conductor substrate, and the like. Alternatively, a substrate provided with an element may be used. Elements provided on the substrate are a capacitive element, a resistive element, a switch element, a light emitting element, a memory element, and the like.

The substrate 510 may be a flexible substrate. As a method for providing a transistor over a flexible substrate, a transistor is manufactured over a non-flexible substrate (eg, a semiconductor substrate), the transistor is separated, and the transistor is transferred to the substrate 510 which is a flexible substrate. There is also. In that case, a separation layer may be provided between the non-flexible substrate and the transistor. Note that as the substrate 510, a sheet, a film, a foil, or the like in which a fiber is woven may be used. In addition, the substrate 510 may have elasticity. The substrate 510 may also have a property of returning to its original shape when bending or pulling is stopped. Alternatively, it may have a property of not returning to the original shape. The thickness of the substrate 510 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less. When the substrate 510 is thin, the weight of the semiconductor device can be reduced. Further, by thinning the substrate 510, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, a shock or the like applied to the semiconductor device over the substrate 510 due to dropping or the like can be mitigated. That is, a durable semiconductor device can be provided.

The substrate 510 which is a flexible substrate is, for example, a metal, an alloy, a resin, glass, or a fiber thereof. It is preferable that the flexible substrate has a lower linear expansion coefficient because the deformation due to the environment is suppressed. For the flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less may be used. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, polytetrafluoroethylene (PTFE), and the like. In particular, aramid is suitable as a material for a flexible substrate because it has a low coefficient of linear expansion.

[Insulation layer]
The insulating layers 511 to 516 are formed of an insulating layer having a single layer structure or a stacked structure. Examples of the material forming the insulating layer include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and oxide. Hafnium, tantalum oxide, etc. are available.

Note that in this specification, an oxynitride refers to a compound having a higher oxygen content than nitrogen, and a nitride oxide refers to a compound having a higher nitrogen content than oxygen. In this specification and the like, the oxide used for the insulating material includes an oxide having a nitrogen concentration of less than 1 atomic%.

Since the insulating layers 514 and 515 are in contact with the semiconductor region 520, the insulating layer 514 and the insulating layer 515 preferably contain an oxide, and particularly preferably an oxide material from which oxygen is released by heating. It is preferable to use an oxide containing more oxygen than that satisfying the stoichiometric composition. A part of oxygen is desorbed by heating in an oxide film containing more oxygen than the stoichiometric composition. Oxygen desorbed from the insulating layers 514 and 515 is supplied to the semiconductor region 520 which is an oxide semiconductor, so that oxygen vacancies in the oxide semiconductor can be reduced. As a result, variation in electric characteristics of the transistor can be suppressed and reliability can be improved.

An oxide film containing more oxygen than the stoichiometric composition has, for example, a TDS (Thermal Desorption Spectroscopy) analysis showing a desorption amount of oxygen of 1.0 × 10 5 in terms of oxygen atoms. ^The oxide film has a thickness of ¹⁸ atoms / cm ³ or higher, preferably 3.0 × 10 ²⁰ atoms / cm ³ or higher. The surface temperature of the film during the TDS analysis is preferably 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower.

The insulating layer 513 has a passivation function of preventing oxygen contained in the insulating layer 514 from being combined with a metal contained in the conductive layer 533 and reducing oxygen contained in the insulating layer 514. The insulating layer 516 has a passivation function of preventing oxygen contained in the insulating layer 515 from decreasing.

The insulating layers 511, 513, and 516 preferably have a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, and the like. By providing the insulating layers 511, 513, and 516, diffusion of oxygen from the semiconductor region 520 to the outside and entry of hydrogen, water, or the like from the outside to the semiconductor region 520 can be prevented. In order to have such a function, the insulating layers 511, 513, and 516 have, for example, silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, or oxide. At least one insulating layer formed of yttrium, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like may be provided.

[Conductive layer]
The conductive layer 531 and the conductive layer 532 are formed of copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel. (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (Sr) low It is preferable to use a simple substance made of a resistance material, an alloy, or a single layer or a laminated layer of a conductive film containing a compound containing these as a main component. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum, which has both heat resistance and conductivity. Further, it is preferably formed of a low resistance conductive material such as aluminum or copper. Further, it is preferable to use a Cu—Mn alloy because manganese oxide is formed at the interface with an insulator containing oxygen and the manganese oxide has a function of suppressing diffusion of Cu.

The conductive layer 531 and the conductive layer 532 are made of a hard mask used for forming a stack of the semiconductor layer 521 and the semiconductor layer 522. Therefore, the conductive layers 531 and 532 do not have regions in contact with the side surfaces of the semiconductor layers 521 and 522. For example, the semiconductor layers 521 and 522 and the conductive layers 531 and 532 can be manufactured through the following steps. A two-layer oxide semiconductor film which forms the semiconductor layers 521 and 522 is formed. A single-layer or stacked-layer conductive film is formed over the oxide semiconductor film. The conductive film is etched to form a hard mask. Using this hard mask, the two-layer oxide semiconductor film is etched to form a stack of the semiconductor layer 521 and the semiconductor layer 522. Next, the hard mask is etched to form the conductive layer 531 and the conductive layer 532.

The conductive layer 530 and the conductive layer 530 can be formed using the same material as the conductive layer 531 and the conductive layer 532.

[Semiconductor layer]
The semiconductor layer 522 is, for example, an oxide semiconductor containing indium (In). The semiconductor layer 522 has a high carrier mobility (electron mobility) when it contains indium, for example. Further, the semiconductor layer 522 preferably contains the element M. The element M is preferably aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), or the like. Other elements that can be applied to the element M include boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo). ), Lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), and tungsten (W). However, in some cases, a combination of a plurality of the above-mentioned elements may be used as the element M. The element M is, for example, an element having a high binding energy with oxygen. For example, it is an element having a binding energy with oxygen higher than that of indium. Alternatively, the element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. In addition, the semiconductor layer 522 preferably contains zinc (Zn). The oxide semiconductor may be easily crystallized when it contains zinc.

However, the semiconductor layer 522 is not limited to an oxide semiconductor containing indium. The semiconductor layer 522 may be, for example, an oxide semiconductor containing zinc, an oxide semiconductor containing gallium, an oxide semiconductor containing gallium, an oxide semiconductor containing gallium, which does not contain indium, such as zinc tin oxide or gallium tin oxide. . For the semiconductor layer 522, for example, an oxide with a wide energy gap is used. The energy gap of the semiconductor layer 522 is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less. The semiconductor region 520 is preferably formed using a CAAC-OS described later. Alternatively, at least the semiconductor layer 522 is preferably formed using a CAAC-OS.

For example, the semiconductor layer 521 and the semiconductor layer 523 are oxide semiconductors including one or more elements other than oxygen included in the semiconductor layer 522, or two or more elements. Since the semiconductor layer 521 and the semiconductor layer 523 are composed of one or more elements other than oxygen, which form the semiconductor layer 522, or two or more elements, the interface between the semiconductor layer 521 and the semiconductor layer 522, and the semiconductor layer 522 and the semiconductor layer 523. An interface level is hard to be formed at the interface with and.

Note that when the semiconductor layer 521 is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, more preferably 25 atomic%. And M is higher than 75 atomic%. When the semiconductor layer 521 is formed by a sputtering method, a sputtering target with the above composition is preferably used. For example, In: M: Zn = 1: 3: 2 is preferable.

Further, when the semiconductor layer 522 is an In-M-Zn oxide, In is higher than 25 atomic%, M is less than 75 atomic%, more preferably In is 34 atomic% when the sum of In and M is 100 atomic%. It is higher and M is less than 66 atomic%. When the semiconductor layer 522 is formed by a sputtering method, a sputtering target with the above composition is preferably used. For example, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1 :. 2, In: M: Zn = 4: 2: 4.1 is preferable. In particular, when an atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as a sputtering target, the atomic ratio of the semiconductor layer 522 to be formed is In: Ga: Zn = 4: 2 :. It may be close to 3.

In addition, when the semiconductor layer 523 is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, more preferably In is 25 atomic%. And M is higher than 75 atomic%. Note that the semiconductor layer 523 may be formed using the same oxide as the semiconductor layer 521. However, in some cases, the semiconductor layer 521 and / or the semiconductor layer 523 may not contain indium. For example, the semiconductor layer 521 and / or the semiconductor layer 523 may be gallium oxide.

With reference to FIG. 25, the function and effect of the semiconductor region 520 formed by stacking the semiconductor layer 521, the semiconductor layer 522, and the semiconductor layer 523 will be described. 25A is a partially enlarged view of FIG. 24B and is an enlarged view of the active layer (channel portion) of the transistor 581. 25B shows the energy band structure of the active layer of the transistor 581, and shows the energy band structure of the portion indicated by the dashed line z1-z2 in FIG.

Ec 514, Ec 521, Ec 522, Ec 523, and Ec 515 in FIG.

Here, the difference between the vacuum level and the energy at the lower end of the conduction band (also referred to as “electron affinity”) is defined as the energy gap from the difference between the vacuum level and the energy at the upper end of the valence band (also referred to as ionization potential). It will be the subtracted value. The energy gap can be measured using a spectroscopic ellipsometer. The energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) device.

Since the insulating layers 515 and 516 are insulators, Ec513 and Ec512 are closer to the vacuum level (electron affinity is lower) than Ec521, Ec522, and Ec523.

For the semiconductor layer 522, an oxide having an electron affinity higher than those of the semiconductor layers 521 and 523 is used. For example, the semiconductor layer 522 has an electron affinity of 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less than the semiconductor layers 521 and 523. Larger oxides are used. The electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

Note that indium gallium oxide has a low electron affinity and a high oxygen blocking property. Therefore, the semiconductor layer 523 preferably contains indium gallium oxide. The gallium atomic ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, more preferably 90% or more. At this time, when a gate voltage is applied, a channel is formed in the semiconductor layer 522 having a high electron affinity among the semiconductor layers 521, 522, and 523.

Here, a mixed region of the semiconductor layer 521 and the semiconductor layer 522 may be provided between the semiconductor layer 521 and the semiconductor layer 522. Further, a mixed region of the semiconductor layers 522 and 523 may be provided between the semiconductor layers 522 and 523. In the mixed region, the interface state density becomes low. Therefore, the stacked body of the semiconductor layer 521, the semiconductor layer 522, and the semiconductor layer 523 has a band structure in which energy continuously changes (also referred to as a continuous junction) in the vicinity of each interface.

At this time, the electrons mainly move in the semiconductor layer 522, not in the semiconductor layers 521 and 523. As described above, by lowering the interface state density at the interface between the semiconductor layer 521 and the semiconductor layer 522 and the interface state density at the interface between the semiconductor layer 522 and the semiconductor layer 523, electrons move in the semiconductor layer 522. It is less likely to be disturbed, and the on-current of the transistor can be increased.

The on-state current of the transistor can be increased as the number of factors that hinder the movement of electrons is reduced. For example, if there is no factor that obstructs the movement of electrons, it is estimated that the electrons move efficiently. The movement of electrons is also hindered, for example, when the physical unevenness of the channel formation region is large. Alternatively, for example, even when the defect level density in the region where the channel is formed is high, the electron transfer is hindered.

To increase the on-state current of the transistor 581, for example, the root mean square (RMS) of the upper surface or the lower surface (formation surface, here, the semiconductor layer 521) of the semiconductor layer 522 in a range of 1 μm × 1 μm is used. The roughness may be less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. The average surface roughness (also referred to as Ra) in the range of 1 μm × 1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. Further, the maximum height difference (also referred to as PV) in the range of 1 μm × 1 μm is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, further preferably less than 7 nm. RMS roughness, Ra and PV can be measured using a scanning probe microscope system.

For example, in the case where the semiconductor layer 522 has oxygen vacancies (also referred to as V 2 _O ), hydrogen may enter a site of oxygen vacancies to form a donor level. The following may be referred to a state that has entered the hydrogen to oxygen vacancies in the site as V _{O H.} Since V _OH scatters electrons, it becomes a factor that reduces the on-current of the transistor. Note that oxygen-deficient sites are more stable when oxygen enters than when hydrogen enters. Therefore, in some cases, the on-state current of the transistor can be increased by reducing oxygen vacancies in the semiconductor layer 522.

For example, at a certain depth of the semiconductor layer 522 or in a certain region of the semiconductor layer 522, the hydrogen concentration measured by Secondary Ion Mass Spectroscopy (SIMS) is 1 × 10 ¹⁶ atoms / cm 2. ³ or more and 2 × 10 ²⁰ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more, 1 × It is 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less.

In order to reduce oxygen vacancies in the semiconductor layer 522, for example, there is a method of moving excess oxygen contained in the insulating layer 515 to the semiconductor layer 522 through the semiconductor layer 521. In this case, the semiconductor layer 521 is preferably a layer having oxygen permeability (a layer which allows oxygen to pass through or transmits).

When the transistor 581 has an s-channel structure, a channel is formed over the entire semiconductor layer 522. Therefore, the thicker the semiconductor layer 522, the larger the channel region. That is, the thicker the semiconductor layer 522 is, the higher the on-state current of the transistor 581 can be.

Further, in order to increase the on-state current of the transistor 581, it is preferable that the thickness of the semiconductor layer 523 be smaller. The semiconductor layer 523 may have a region of less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less. On the other hand, the semiconductor layer 523 has a function of blocking an element (hydrogen, silicon, or the like) other than oxygen which is included in an adjacent insulator from entering the semiconductor layer 522 in which a channel is formed. Therefore, the semiconductor layer 523 preferably has a certain thickness. The semiconductor layer 523 may have a region with a thickness of 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more. In addition, the semiconductor layer 523 preferably has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from the insulating layer 515 and the like.

In addition, in order to increase the reliability of the transistor 581, the semiconductor layer 521 is preferably thick and the semiconductor layer 523 is preferably thin. The semiconductor layer 521 may have a region with a thickness of, for example, 10 nm or more, preferably 20 nm or more, further preferably 40 nm or more, more preferably 60 nm or more. By increasing the thickness of the semiconductor layer 521, the distance from the interface between the adjacent insulator and the semiconductor layer 521 to the semiconductor layer 522 where the channel is formed can be increased. However, since the productivity of the semiconductor device may be reduced, the semiconductor layer 521 may have a region with a thickness of, for example, 200 nm or less, preferably 120 nm or less, further preferably 80 nm or less.

In order to impart stable electric characteristics to the transistor 581, it is effective to reduce the impurity concentration in the semiconductor region 520 and make the semiconductor layer 522 intrinsic or substantially intrinsic. Note that in this specification and the like, when an oxide semiconductor is substantially intrinsic, the carrier density of the oxide semiconductor is less than 8 × 10 ¹¹ pieces / cm ³ , preferably less than 1 × 10 ¹¹ pieces / cm ^3. And more preferably less than 1 × 10 ¹⁰ pieces / cm ³ and 1 × 10 ⁻⁹ pieces / cm ³ or more.

In the oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main components are impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor. The impurity level serves as a trap and may deteriorate the electrical characteristics of the transistor. Therefore, it is preferable to reduce the impurity concentration in the layers of the semiconductor layer 521, the semiconductor layer 522, and the semiconductor layer 523, or at each interface.

For example, a region having a silicon concentration of 1 × 10 ¹⁶ atoms / cm ³ or more and less than 1 × 10 ¹⁹ atoms / cm ³ is provided between the semiconductor layer 522 and the semiconductor layer 521. Silicon concentration more be less than 1 × ¹⁰ 16 atoms / cm ³ or more and 5 × ¹⁰ 18 atoms / cm ³ is preferably less than 1 × ¹⁰ 16 atoms / cm ³ or more and 2 × ¹⁰ 18 atoms / cm ³ preferable. In addition, a region having a silicon concentration of 1 × 10 ¹⁶ atoms / cm ³ or more and less than 1 × 10 ¹⁹ atoms / cm ³ is provided between the semiconductor layers 522 and 523. The silicon concentration is preferably 1 × 10 ¹⁶ atoms / cm ³ or more and less than 5 × 10 ¹⁸ atoms / cm ^3, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and less than 2 × 10 ¹⁸ atoms / cm ³ . The silicon concentration can be measured by SIMS, for example.

Further, in order to reduce the hydrogen concentration of the semiconductor layer 522, it is preferable to reduce the hydrogen concentration of the semiconductor layers 521 and 523. The semiconductor layers 521 and 523 each have a region with a hydrogen concentration of 1 × 10 ¹⁶ atoms / cm ³ or more and 2 × 10 ²⁰ atoms / cm ³ or less. The hydrogen concentration is preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 1 × 10 ¹⁹ atoms / cm ³ or less, 1 It is more preferably not less than × 10 ¹⁶ atoms / cm ^{3 and not} more than 5 × 10 ¹⁸ atoms / cm ³ . The hydrogen concentration can be measured by SIMS, for example.

In order to reduce the nitrogen concentration of the semiconductor layer 522, it is preferable to reduce the nitrogen concentration of the semiconductor layers 521 and 523. The semiconductor layers 521 and 523 each have a region with a nitrogen concentration of 1 × 10 ¹⁶ atoms / cm ³ or more and less than 5 × 10 ¹⁹ atoms / cm ³ . The nitrogen concentration is preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 1 × 10 ¹⁸ atoms / cm ³ or less, and 1 × More preferably, it is 10 ¹⁶ atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less. The nitrogen concentration can be measured by SIMS.

Further, the off-state current of a transistor including a highly purified oxide semiconductor in a channel formation region as described above is extremely low. For example, when the voltage between the source and the drain is about 0.1 (V), 5 (V), or 10 (V), the off-current standardized by the channel width of the transistor is several yA / μm. To several zA / μm can be reduced.

FIG. 24 shows an example in which the semiconductor region 520 has three layers, but the invention is not limited to this. For example, a two-layer structure without the semiconductor layer 521 or the semiconductor layer 523 may be used. Alternatively, a semiconductor layer similar to the semiconductor layers 521 to 523 can be provided over or below the semiconductor layer 521 or above or below the semiconductor layer 523 to have a four-layer structure. Alternatively, a semiconductor layer similar to the semiconductor layers 521 to 523 is provided at any two or more positions above the semiconductor layer 521, below the semiconductor layer 521, above the semiconductor layer 523, and below the semiconductor layer 523 to form an n-layer structure. (N is an integer of 5 or more).

When the transistor 581 is a transistor without a back gate electrode, the conductive layer 533 may not be provided. In this case, the insulating layer 512 is not provided and the insulating layer 513 may be formed over the insulating layer 511.

<Structure example 2>
In the transistor 581 illustrated in FIG. 24, the semiconductor layer 523 and the insulating layer 515 can be etched using the conductive layer 530 as a mask. An example of a structure of an OS transistor which has undergone such a process is shown in FIG. In the transistor 582 illustrated in FIG. 26A, the end portions of the semiconductor layer 523 and the insulating layer 515 substantially match the end portions of the conductive layer 530. The semiconductor layer 523 and the insulating layer 515 exist only under the conductive layer 530.

<Structure example 3>
A transistor 583 illustrated in FIG. 26B has a device structure in which a conductive layer 535 and a conductive layer 536 are added to the transistor 582. A pair of electrodes serving as a source electrode and a drain electrode of the transistor 582 includes a stack of a conductive layer 535 and a conductive layer 531 and a stack of a conductive layer 536 and a conductive layer 532.

The conductive layers 535 and 536 are formed using a single-layer or stacked conductor. For example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and tungsten. A conductor containing one or more kinds can be used. The conductor may be an alloy film or a compound, including a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, and titanium and nitrogen. A conductor or the like may be used.

The conductive layers 535 and 536 may have a property of transmitting visible light. Alternatively, the conductive layers 535 and 536 may have a property of not transmitting visible light, ultraviolet light, infrared light, or X-ray by reflecting or absorbing it. With such a property, variation in electrical characteristics of the transistor 582 due to stray light can be suppressed in some cases.

As the conductive layers 535 and 536, it is preferable to use a layer which does not form a Schottky barrier with the semiconductor layer 522 or the like. Thus, the on characteristics of the transistor 583 can be improved.

As the conductive layers 535 and 536, it may be preferable to use a film having a higher resistance than the conductive layers 531 and 532. In some cases, the conductive layers 535 and 536 preferably have lower resistance than the channel of the transistor 583 (specifically, the semiconductor layer 522). For example, the resistivity of the conductive layers 535 and 536 may be 0.1 Ωcm or more and 100 Ωcm or less, or 0.5 Ωcm or more and 50 Ωcm or less, or 1 Ωcm or more and 10 Ωcm or less. By setting the resistivity of the conductive layers 535 and 536 within the above range, electric field concentration at the boundary between the channel and the drain can be reduced. Therefore, variation in electric characteristics of the transistor 583 can be reduced. In addition, punch-through current due to the electric field generated from the drain can be reduced. Therefore, the saturation characteristics can be improved even in a transistor having a short channel length. Note that in some circuit configurations in which the source and the drain are not interchanged, it may be preferable to dispose only one of the conductive layers 535 and 536 (for example, the drain side).

<Structure example 4>
In the transistor 581 illustrated in FIG. 24, the conductive layer 531 and the conductive layer 532 may be in contact with side surfaces of the semiconductor layers 521 and 522. An example of such a structure is shown in FIG. In the transistor 584 illustrated in FIG. 26C, the conductive layer 531 and the conductive layer 532 are in contact with the side surface of the semiconductor layer 521 and the side surface of the semiconductor layer 522.

<Crystal structure of oxide semiconductor film>
The structure of the oxide semiconductor film included in the semiconductor region 520 is described below. Note that in this specification, a trigonal crystal or a rhombohedral crystal is referred to as a hexagonal crystal system.

The oxide semiconductor film is roughly classified into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film refers to a CAAC-OS film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, or the like.

In this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of -5 ° or more and 5 ° or less is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° or more and 30 ° or less. Further, “vertical” means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

[CAAC-OS film]
The CAAC-OS film is one of oxide semiconductor films including a plurality of c-axis aligned crystal parts.

Confirming a plurality of crystal parts by observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of the CAAC-OS film by a transmission electron microscope (TEM). You can On the other hand, a clear boundary between crystal parts, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed by a high-resolution TEM image. Therefore, it can be said that in the CAAC-OS film, electron mobility is less likely to be reduced due to the crystal grain boundaries.

When a high-resolution TEM image of a cross section of the CAAC-OS film is observed from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in a layered manner in the crystal part. Each layer of metal atoms has a shape that reflects unevenness of a surface (also referred to as a formation surface) or a top surface of the CAAC-OS film which is to be formed, and is arranged in parallel to the formation surface or the top surface of the CAAC-OS film. .

On the other hand, when a high-resolution TEM image of the plane of the CAAC-OS film is observed from a direction substantially perpendicular to the sample surface, it can be confirmed that the metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

When the structural analysis of the CAAC-OS film is performed using an X-ray diffraction (XRD) apparatus, for example, in the analysis of the CAAC-OS film including a crystal of InGaZnO ₄ by the out-of-plane method, A peak may appear near the diffraction angle (2θ) of 31 °. Since this peak belongs to the (009) plane of the InGaZnO ₄ crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis faces a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

In the analysis of the CAAC-OS film including an InGaZnO ₄ crystal by the out-of-plane method, a peak may appear near 2θ of 36 ° in addition to the peak at 2θ of 31 °. The peak near 2θ of 36 ° indicates that a part of the CAAC-OS film contains a crystal having no c-axis orientation. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

The CAAC-OS film is an oxide semiconductor film with low impurity concentration. The impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, an element such as silicon which has a stronger bonding force with oxygen than a metal element forming the oxide semiconductor film deprives the oxide semiconductor film of oxygen and thus disturbs the atomic arrangement of the oxide semiconductor film to cause crystallinity. Will be a factor to reduce. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have a large atomic radius (or molecular radius); therefore, when contained in the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed and crystallinity is increased. Will be a factor to reduce. Note that the impurities contained in the oxide semiconductor film might serve as carrier traps or carrier generation sources.

The CAAC-OS film is an oxide semiconductor film having a low density of defect states. For example, oxygen vacancies in the oxide semiconductor film might serve as carrier traps or carrier generation sources by capturing hydrogen.

The low impurity concentration and low defect level density (low oxygen deficiency) is called high-purity intrinsic or substantially high-purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film rarely has negative threshold voltage (is rarely normally on). Further, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor including the oxide semiconductor film has high variation in electric characteristics and high reliability. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave like fixed charge. Therefore, a transistor including an oxide semiconductor film having a high impurity concentration and a high density of defect states might have unstable electric characteristics.

An OS transistor including a CAAC-OS film has little variation in electric characteristics due to irradiation with visible light or ultraviolet light.

[Microcrystalline oxide semiconductor film]
The microcrystalline oxide semiconductor film has a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. A crystal part included in the microcrystalline oxide semiconductor film is often 1 nm to 100 nm inclusive, or 1 nm to 10 nm inclusive. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystals) of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is referred to as an nc-OS (nanocrystalline Oxide Semiconductor) film. Further, in the nc-OS film, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly confirmed in some cases.

The nc-OS film has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In the nc-OS film, no regularity is found in crystal orientation between different crystal parts. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS film may be indistinguishable from the amorphous oxide semiconductor film depending on the analysis method. For example, when a structural analysis is performed on the nc-OS film by using an XRD apparatus that uses X-rays having a diameter larger than that of the crystal part, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction (also referred to as selected area electron diffraction) using an electron beam having a probe diameter (eg, 50 nm or more) larger than that of a crystal portion is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. To be done. On the other hand, spots are observed when the nc-OS film is subjected to nanobeam electron diffraction using an electron beam having a probe diameter close to or smaller than that of the crystal part. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed like a circle (in a ring shape). Further, when nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region.

The nc-OS film is an oxide semiconductor film having higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. However, in the nc-OS film, there is no regularity in crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.

[Amorphous oxide semiconductor film]
The amorphous oxide semiconductor film is an oxide semiconductor film in which atomic arrangement in the film is irregular and which does not have a crystal part. An example is an oxide semiconductor film having an amorphous state such as quartz.

In the high-resolution TEM image of the amorphous oxide semiconductor film, crystal parts cannot be found. When a structural analysis using an XRD apparatus is performed on the amorphous oxide semiconductor film, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. When electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. When nanobeam electron diffraction is performed on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

The oxide semiconductor film may have a structure having physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS: amorphous-like oxide semiconductor) film.

In the high-resolution TEM image of the a-like OS film, a void may be observed. In addition, in the high-resolution TEM image, there is a region where a crystal part can be clearly confirmed and a region where a crystal part cannot be confirmed. The a-like OS film may be crystallized by the irradiation of a small amount of electrons as observed with a TEM, and growth of a crystal part may be observed. On the other hand, in the case of a good nc-OS film, almost no crystallization due to a small amount of electron irradiation as observed by TEM is observed.

The size of the crystal part of the a-like OS film and the nc-OS film can be measured using a high resolution TEM image. For example, a crystal of InGaZnO ₄ has a layered structure and includes two Ga—Zn—O layers between In—O layers. The unit cell of the InGaZnO ₄ crystal has a structure in which three layers of In—O layers and six layers of Ga—Zn—O layers, nine layers in total, are layered in the c-axis direction. Therefore, the distance between these adjacent layers is about the same as the lattice distance (also referred to as the d value) of the (009) plane, and the value is determined to be 0.29 nm from the crystal structure analysis. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, each lattice fringe corresponds to the ab plane of the InGaZnO ₄ crystal at the place where the lattice fringe spacing is 0.28 nm or more and 0.30 nm or less.

The oxide semiconductor film may have different film density depending on the structure. For example, if the composition of an oxide semiconductor film is known, the structure of the oxide semiconductor film can be estimated by comparing with the film density of a single crystal oxide semiconductor film having the same composition. For example, the film density of the a-like OS film is greater than or equal to 78.6% and less than 92.3% of the film density of the single crystal oxide semiconductor film. Further, for example, with respect to the film density of the single crystal oxide semiconductor film, the film density of the nc-OS film and the film density of the CAAC-OS film are 92.3% or more and less than 100%. Note that it is difficult to form an oxide semiconductor film having a film density of less than 78% with respect to the film density of a single crystal oxide semiconductor film.

The above will be described using a specific example. For example, in an oxide semiconductor film that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the film density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, In: Ga: Zn = 1 : 1: 1 in the oxide semiconductor film which satisfies the atomic ratio of the film density of a-like OS film 5.0 g / cm ³ or more 5.9 g / cm ³ Less than Further, for example, in an oxide semiconductor film satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the film density of the nc-OS film and the film density of the CAAC-OS film are 5.9 g / cm ^3. The above is less than 6.3 g / cm ³ .

Note that a single crystal oxide semiconductor film having the same composition may not exist. In that case, by combining single crystal oxide semiconductor films having different compositions at an arbitrary ratio, the film density corresponding to the single crystal oxide semiconductor film having a desired composition can be calculated. The film density of a single crystal oxide semiconductor film having a desired composition may be calculated using a weighted average with respect to a ratio of combining single crystal oxide semiconductor films having different compositions. However, the film density is preferably calculated by combining as few kinds of single crystal oxide semiconductor films as possible.

Note that the oxide semiconductor film may be, for example, a stacked film including two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film. .

<Film forming method>
As a method for forming an insulating layer, a conductive layer, a semiconductor layer, and the like which form a semiconductor device, a sputtering method and a plasma CVD method are typical. It can be formed by another method, for example, a thermal CVD method. As the thermal CVD method, for example, a MOCVD (Metal Organic Chemical Vapor Deposition) method or an ALD (Atomic Layer Deposition) method can be used.

Since the thermal CVD method is a film forming method that does not use plasma, it has an advantage that defects are not generated due to plasma damage. In the thermal CVD method, the inside of the chamber may be at atmospheric pressure or reduced pressure, the source gas and the oxidant may be simultaneously sent into the chamber, and the reaction may be performed in the vicinity of the substrate or on the substrate to deposit the film on the substrate. .

In the ALD method, the film may be formed by setting the inside of the chamber under atmospheric pressure or reduced pressure, sequentially introducing the raw material gases for the reaction into the chamber, and repeating the order of introducing the gas. For example, by switching respective switching valves (also referred to as high-speed valves), two or more kinds of raw material gases are sequentially supplied to the chamber, and at the same time as or after the first raw material gas is mixed so that plural kinds of raw material gases are not mixed. An active gas (argon, nitrogen, or the like) is introduced, and a second source gas is introduced. When the inert gas is introduced at the same time, the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second source gas is introduced. Further, instead of introducing the inert gas, the second raw material gas may be introduced after exhausting the first raw material gas by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first monoatomic layer, and reacts with a second source gas introduced later, so that the second monoatomic layer becomes the first monolayer. A thin film is formed by stacking on the atomic layer. By repeating the gas introduction sequence a plurality of times while controlling the gas introduction sequence, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, it is possible to precisely adjust the film thickness, which is suitable for producing a fine FET.

The thermal CVD method such as MOCVD method or ALD method can form the conductive film and the semiconductor film disclosed in the above-described embodiments. For example, in the case of forming an InGaZnO _X (X> 0) film. For this, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula of trimethylindium is In (CH ₃ ) ₃ . The chemical formula of trimethylgallium is Ga (CH ₃ ) ₃ . The chemical formula of dimethylzinc is Zn (CH ₃ ) ₂ . Further, without being limited to these combinations, triethylgallium (chemical formula Ga (C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethyl zinc (chemical formula Zn (C ₂ H ₅ )) can be used instead of dimethylzinc. ₂ ) can also be used.

For example, when forming a tungsten film by a film forming apparatus using ALD, WF ₆ gas and B ₂ H ₆ gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF ₆ gas and H ₂ gas are added. A tungsten film is formed using gas. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, when an oxide semiconductor film, for example, an InGaZnO _x (X> 0) film is formed by a film forming apparatus using ALD, In (CH ₃ ) ₃ gas and O ₃ gas are sequentially and repeatedly introduced to introduce InO _Two layers are formed, and then a GaO layer is formed by using Ga (CH ₃ ) ₃ gas and O ₃ gas, and further, a ZnO layer is formed by using Zn (CH ₃ ) ₂ gas and O ₃ gas. The order of these layers is not limited to this example. Further, a mixed compound layer such as an InGaO ₂ layer, an InZnO ₂ layer, a GaInO layer, a ZnInO layer, or a GaZnO layer may be formed by mixing these gases. Incidentally, instead of the O ₃ gas may be used the H _{2 O} gas obtained by bubbling with an inert gas such as Ar, but better to use an O ₃ gas containing no H are preferred. Further, In _{(CH 3)} 3 in place of the gas may be used _{In (C 2} H _{5) 3} gas. Further, Ga (C ₂ H ₅ ) ₃ gas may be used instead of Ga (CH ₃ ) ₃ gas. Alternatively, Zn (CH ₃ ) ₂ gas may be used.

The structure and the method described in this embodiment can be combined with structures and methods described in other embodiments as appropriate.

(Embodiment 6)
In this embodiment, as an example of a semiconductor device, an electronic component, an electronic device including the electronic component, and the like will be described.

FIG. 27A is a flowchart illustrating an example of a method for manufacturing an electronic component. Electronic components are also called semiconductor packages, IC packages, or packages. This electronic component has a plurality of standards and names depending on the direction in which the terminal is taken out and the shape of the terminal. Therefore, in this embodiment, an example thereof will be described.

A semiconductor device including a transistor is completed by assembling a plurality of detachable components on a printed circuit board through an assembly process (post process). The post-process can be completed by passing through each process shown in FIG. Specifically, after the element substrate obtained in the previous step is completed (step S1), a dicing step of separating the substrate into a plurality of chips is performed (step S2). Before the substrate is divided into a plurality of parts, the substrate is thinned to reduce the warp of the substrate in the previous process and to reduce the size of parts.

A die bonding process of picking up the chip, mounting it on the lead frame and bonding it is performed (step S3). Adhesion between the chip and the lead frame in the die bonding process may be performed with resin or tape. As the bonding method, a method suitable for the product may be selected. In the die bonding process, a chip may be mounted on the interposer and bonded. In the wire bonding step, the leads of the lead frame and the electrodes on the chip are electrically connected with a thin metal wire (step S4). A silver wire or a gold wire can be used as the thin metal wire. The wire bonding may be either ball bonding or wedge bonding.

The wire-bonded chip is sealed with epoxy resin or the like and subjected to a molding process (step S5). The lead of the lead frame is plated. Then, the lead is cut and molded (step S6). It is possible to prevent the lead from rusting by the plating process, and to more reliably perform soldering when mounting on a printed circuit board later. A printing process (marking) is performed on the surface of the package (step S7). Through the inspection process (step S8), the electronic component is completed (step S9). By incorporating the semiconductor device of any of the above-described embodiments, a small electronic component with low power consumption can be provided.

FIG. 27B is a schematic perspective view of the completed electronic component. As an example, FIG. 27B shows a QFP (Quad Flat Package). The electronic component 800 illustrated in FIG. 27B includes a lead 801 and a circuit portion 803. The circuit portion 803 includes, for example, the semiconductor device, the memory device, and other logic circuits described in the above embodiment. The electronic component 800 is mounted on the printed board 802, for example. A plurality of such electronic components 800 are combined and electrically connected to each other on the printed circuit board 802, whereby the electronic component 800 can be mounted on an electronic device. The completed circuit board 804 is provided inside an electronic device or the like. For example, the electronic component 800 can be used as a processing unit that executes various processes such as a random access memory that stores data, a CPU, an MCU, an FPGA, and a wireless IC. By mounting the electronic component 800, the power consumption of the electronic device can be reduced. Alternatively, it becomes easy to downsize the electronic device.

Therefore, the electronic component 800 includes digital signal processing, software defined radio, avionics (electronic equipment related to aviation such as communication equipment, navigation system, autopilot, and flight management system), ASIC prototyping, medical image processing, voice recognition, It can be applied to electronic components (IC chips) of electronic devices in a wide range of fields such as encryption, bioinformatics (bioinformatics), mechanical device emulators, and radio telescopes in radio astronomy. Examples of such electronic devices include a display device, a personal computer (PC), an image reproducing device having a recording medium (a device for reproducing a recording medium such as a DVD, a Blu-ray disc, a flash memory, and an HDD, and an image display device. Device having a display section). In addition, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a camera (a video camera, a digital still camera, or the like) can be used as an electronic device in which the semiconductor device of one embodiment of the present invention can be used. , Wearable type display device (head mount type, goggle type, glasses type, armband type, bracelet type, necklace type, etc.) navigation system, sound reproduction device (car audio, digital audio player, etc.), copier, facsimile, printer, printer Examples include multifunction machines, automatic teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIGS.

A portable game machine 900 illustrated in FIG. 28A includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like.

A portable information terminal 910 illustrated in FIG. 28B includes a housing 911, a housing 912, a display portion 913, a display portion 914, a connection portion 915, operation keys 916, and the like. The display portion 913 is provided in the housing 911 and the display portion 914 is provided in the housing 912. The housing 911 and the housing 912 are connected by the connecting portion 915, and the angle between the housing 911 and the housing 912 can be changed by the connecting portion 915. Therefore, the image displayed on the display portion 913 may be switched depending on the angle between the housing 911 and the housing 912 in the connection portion 915. A display device with a touch panel may be used for the display portion 913 and / or the display portion 914.

A laptop PC 920 illustrated in FIG. 28C includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

An electric refrigerator-freezer 930 illustrated in FIG. 28D includes a housing 931, a refrigerator compartment door 932, a freezer compartment door 933, and the like.

A video camera 940 illustrated in FIG. 28E includes a housing 941, a housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation keys 944 and the lens 945 are provided in the housing 941, and the display portion 943 is provided in the housing 942. The housing 941 and the housing 942 are connected by a connecting portion 946, and the connecting portion 946 can change the angle between the housing 941 and the housing 942. Depending on the angle of the housing 942 with respect to the housing 941, the orientation of the image displayed on the display portion 943 may be changed, the display / non-display of the image may be switched, or the like.

An automobile 950 illustrated in FIG. 28F includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.

The structure and the method described in this embodiment can be combined with structures and methods described in other embodiments as appropriate.

(Example)
In this embodiment, measurement results of characteristics of the OS transistor which can be used in the above embodiments will be described.

<Temperature characteristics>
First, the temperature characteristics of the OS transistor and the Si transistor were measured. In FIG. 29 (A), the gate voltage _{V G} of the OS transistor - shows the temperature dependence of the measurement results of the field-effect mobility _{mu FE} characteristics - drain current _{I D} characteristics, and the gate voltage _{V G.} Further, in FIG. 29 (B), a channel formation region a gate voltage _{V G} of the Si transistor - shows the temperature dependence of the field-effect mobility _{mu FE} characteristics - drain current _{I D} characteristics, and the gate voltage _{V G.} Note that FIGS. 29A and 29B show the measurement results of each electric characteristic at temperatures of −25 ° C., 50 ° C., and 150 ° C. The drain voltage V _D is set to 1V.

Note that the electric characteristics of the OS transistor illustrated in FIG. 29A are graphs when the channel length L = 0.45 μm, the channel width W = 10 μm, and the thickness Tox = 20 nm of the oxide film of the gate insulating layer. The electrical characteristics of the Si transistor illustrated in FIG. 29B are graphs when L = 0.35 μm, W = 10 μm, and Tox = 20 nm.

The oxide semiconductor layer of the OS transistor was formed using an In—Ga—Zn-based oxide, and the Si transistor was formed using a silicon wafer.

From FIGS. 29A and 29B, it is found that the temperature dependence of the rising gate voltage in the OS transistor is small. Further, the off-current of the OS transistor is equal to or lower than the measurement lower limit (I ₀ ) regardless of the temperature, but the off-current of the Si transistor has large temperature dependence. The measurement result of FIG. 29B shows that at 150 ° C., the off-state current of the Si transistor rises and the current on / off ratio does not become sufficiently large.

From the graphs of FIGS. 29A and 29B, when the semiconductor device of one embodiment of the present invention is formed using an OS transistor, the semiconductor device can operate even at a temperature higher than or equal to 150 ° C. Therefore, a semiconductor device having excellent heat resistance can be realized.

<Pressure resistance>
Next, the withstand voltage of the OS transistor and the Si transistor were measured. FIG. 30 shows the measurement result of the VD-ID characteristics of the Si transistor and the OS transistor. In FIG. 30, in order to compare the breakdown voltage under the same conditions for the Si transistor and the OS transistor, the channel length is 0.9 μm, the channel width is 10 μm, and the thickness of the gate insulating film using silicon oxide is 20 nm. I am trying. The gate voltage is 2V.

As shown in FIG. 30, in the Si transistor, the avalanche breakdown occurs at about 4V with the increase of the drain voltage, whereas in the OS transistor, the avalanche breakdown does not occur up to about 26V with the increase of the drain voltage. It can be seen that a constant current can be applied to.

FIG. 31A shows the measurement result of VD-ID characteristics of the OS transistor when the gate voltage is changed. Further, FIG. 31B shows a measurement result of VD-ID characteristics of the Si transistor when the gate voltage is changed. In order to compare the breakdown voltages of the Si transistor and the OS transistor under the same conditions, the channel length is 0.9 μm, the channel width is 10 μm, and the thickness of the gate insulating film using silicon oxide is 20 nm. . In addition, in the OS transistor in FIG. 31A, the gate voltage was changed to 0.1 V, 2.06 V, 4.02 V, 5.98 V, and 7.94 V for measurement. Further, in the Si transistor in FIG. 31B, the gate voltage was changed to 0.1 V, 1.28 V, 2.46 V, 3.64 V, and 4.82 V, and measurement was performed.

As shown in FIGS. 31A and 31B, in the Si transistor, avalanche breakdown occurs at about 4 V to 5 V as the drain voltage increases, whereas in the OS transistor, as the drain voltage increases. It can be seen that at about 9 V, a constant current can flow without causing avalanche breakdown.

From FIGS. 30 and 31, it can be seen that the OS transistor has a higher breakdown voltage than the Si transistor. Therefore, in the memory cell according to one embodiment of the present invention, the range of voltage that the node FN can take can be widened and the distribution of potential that can be held can be increased.

10 semiconductor device 20 memory cell 21 holding portion 21a holding portion 21b holding portion 22 transistor 23 capacitance element 30 circuit 31 transistor 32 capacitance element 40 circuit 41 transistor 42 capacitance element 43 transistor 50 circuit 51 transistor 52 transistor 61 layer 62 layer 63 layer 71 transistor 72 transistor 100 substrate 101 element isolation region 102 impurity region 103 impurity region 104 channel formation region 105 insulating film 106 gate electrode 111 insulating film 112 conductive film 113 conductive film 114 conductive film 116 conductive film 117 conductive film 118 conductive film 120 insulating film 121 insulation Film 122 Insulating film 130 Semiconductor film 130a Oxide semiconductor film 130b Oxide semiconductor film 130c Oxide semiconductor film 131 Gate insulating film 132 Conductive film 133 Conductive film 134 Gate charge 300 memory device 310 memory cell array 320 row selection driver 321 decoder 322 control circuit 330 column selection driver 331 decoder 332 latch circuit 333 D / A converter 334 switch circuit 335 transistor 336 transistor 340 A / D converter 341 comparator 342 encoder 343 latch circuit 344 buffer 400 computer 410 input device 420 output device 430 central processing unit 431 control circuit 432 arithmetic circuit 510 substrate 511 insulating layer 512 insulating layer 513 insulating layer 514 insulating layer 515 insulating layer 516 insulating layer 520 semiconductor region 521 semiconductor layer 522 semiconductor layer 523 semiconductor Layer 530 Conductive layer 531 Conductive layer 532 Conductive layer 533 Conductive layer 535 Conductive layer 536 Conductive layer 581 Transistor 582 Transistor 583 Transistor 584 Transistor 800 Electronic component 801 Lead 802 Printed circuit board 803 Circuit part 804 Circuit board 900 Handheld game console 901 Housing 902 Housing 903 Display 904 Display 905 Microphone 906 Speaker 907 Operation key 908 Stylus 910 Mobile information terminal 911 Housing 912 Housing 913 Display 914 Display 915 Connection 916 Operation keys 921 Housing 922 Display 923 Keyboard 924 Pointing device 930 Electric freezer / refrigerator 931 Housing 932 Refrigerator compartment door 933 Freezer compartment door 940 Video camera 941 enclosure Body 942 Housing 943 Display 944 Operation keys 945 Lens 946 Connection 950 Automobile 951 Car body 952 Wheels 953 Dashboard 954 Light

Claims (3)

Have memory cells,
The memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance element, and a second capacitance element,
The gate of the first transistor is electrically connected to the first wiring,
Wherein one of the first source or drain of the transistor, to one electrode electrically connected to the gate and the first capacitor of the second transistor,
The other of the source and the drain of the first transistor is electrically connected to the second wiring,
One of a source and a drain of the second transistor is electrically connected to the second wiring,
The other of the source and the drain of the second transistor is electrically connected to a third wiring,
A gate of the third transistor is electrically connected to a fourth wiring,
One of a source and a drain of the third transistor is electrically connected to one electrode of the second capacitor,
The other of the source and the drain of the third transistor is electrically connected to the second wiring,
The gate of the fourth transistor is electrically connected to the fifth wiring,
One of a source and a drain of the fourth transistor is electrically connected to the second wiring,
The other of the source and the drain of the fourth transistor is electrically connected to a sixth wiring ,
The other electrode of the first capacitor is electrically connected to the seventh wiring,
A semiconductor device in which the other electrode of the second capacitor is electrically connected to the eighth wiring . In claim 1,
A semiconductor device in which the first transistor and the third transistor each include an oxide semiconductor in a channel formation region. In claim 1 or 2,
The first transistor is provided on the second transistor,
The semiconductor device in which the third transistor and the fourth transistor are provided on the first transistor.