JP6349677B2 - Scanning line driving circuit, electro-optical device driving method, electro-optical device, and electronic apparatus - Google Patents

Description

  The present invention relates to a scanning line driving circuit, an electro-optical device driving method, an electro-optical device, and an electronic apparatus.

  In an electronic apparatus having a display function, a transmissive electro-optical device or a reflective electro-optical device is used. Light is irradiated to these electro-optical devices, and transmitted light or reflected light modulated by the electro-optical device becomes a display image, or is projected on a screen to become a projection image. A liquid crystal device is known as an electro-optical device used in such an electronic apparatus, which forms an image using the dielectric anisotropy of liquid crystal and the optical rotation of light in the liquid crystal layer. . In the liquid crystal device, scanning lines and signal lines are arranged in an image display area, and pixels are arranged in a matrix at intersections thereof. A pixel transistor is provided in the pixel, and an image is formed by supplying an image signal to each pixel through the pixel transistor.

  In order to obtain a stereoscopic video (three-dimensional video) or a video with high display quality with an electronic device having a display function, the liquid crystal device needs to display a high-definition image at high speed. Such a high-definition image high-speed display method is described in Patent Document 1, for example. In Patent Document 1, after two scanning lines are selected and a first image with half the resolution is displayed, the scanning lines to be combined are shifted by one, and are selected again two by two and the second with half the resolution. The first image and the second image are combined into a high-resolution image.

  Further, area scanning is known as a driving method of a liquid crystal device. This is because, as shown in Patent Document 2, a plurality of subfield areas are used to display one image (one frame image), and the subfield areas move within the display area. It is a driving method. When this driving method is used, it is possible to express time-reversed gradations by polarity inversion driving or digital driving.

JP 2013-19989 A JP 2004-177930 A

  However, the display method described in Patent Document 1 requires a dedicated drive circuit for realizing this display method, and the drive method described in Patent Document 2 is also dedicated for realizing this drive method. Drive circuit was necessary. Since these two types of drive circuits are different, the area scanning described in Patent Document 2 cannot be performed with the liquid crystal device capable of high-speed display described in Patent Document 1. That is, the conventional electro-optical device has a problem that it is difficult to achieve both high-speed display and area scanning.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

Application Example 1 A scanning line driving circuit according to this application example is a scanning line driving circuit capable of switching between a first display method and a second display method, and shifts a signal and outputs a shift output signal for each stage. A shift register circuit for outputting, a first enable signal line to which a first enable signal is supplied, a second enable signal line to which a second enable signal is supplied, and a third enable signal line to which a third enable signal is supplied A shift output signal and one of the first enable signal and the second enable signal, and a logic circuit that outputs the scan signal to the corresponding scan line, and the logic circuit includes the first enable signal or the second enable signal. A common control circuit for inputting either one of the two enable signals. In the first display method, the first drive method and the second drive method are alternately performed. The communication control circuit has a first enable for a first logic circuit corresponding to the first scan line and a second logic circuit corresponding to a second scan line adjacent to the first scan line in the shift direction. A signal is input, and a third logic circuit corresponding to a third scanning line adjacent to the second scanning line in the shift direction and a fourth scanning line adjacent to the third scanning line in the shift direction are corresponded. The second enable signal is input to the fourth logic circuit, and in the second drive method, the common control circuit inputs the first enable signal to the first logic circuit, and the second logic circuit and the third logic circuit The second enable signal is input to the logic circuit, and the third enable signal is input to the fourth logic circuit.
According to this configuration, in the first driving method, the first scanning line and the second scanning line form a line pair, and the third scanning line and the fourth scanning line form a line pair. Therefore, area scanning can be realized by using these line pairs (referred to as line pair scanning). On the other hand, in the second driving method, since the second scanning line and the third scanning line form a line pair, this line pair is used (referred to as shifted line pair scanning) to realize area scanning. Can do. That is, according to this configuration, it is possible to perform area scanning by both line pair scanning that enables high-speed display and shifted line pair scanning.

Application Example 2 In the scanning line driving circuit according to Application Example 1, the first control output line, the second control output line, the third control output line, and the first control output line to which the output signal from the common control circuit is supplied. 4 control output lines, a first control output line is electrically connected to the first logic circuit, a second control output line is electrically connected to the second logic circuit, and a third logic circuit Preferably, a third control output line is electrically connected to the circuit, and a fourth control output line is electrically connected to the fourth logic circuit.
According to this configuration, the interval between adjacent scanning lines can be reduced. Therefore, when the scanning line driving circuit is applied to an electro-optical device, the electro-optical device having a high-resolution display area can perform both area scanning by line pair scanning that enables high-speed display and shifted line pair scanning. Can do.

Application Example 3 In the scanning line driving circuit according to Application Example 1 or 2, the common control circuit is disposed outside a region where the shift register circuit and the logic circuit are disposed, and the first control output line is provided. The extending direction of the second control output line, the third control output line, and the fourth control output line preferably intersects the extending direction of the first scanning line.
According to this configuration, the interval between adjacent scanning lines can be reduced. Therefore, when the scanning line driving circuit is applied to an electro-optical device, the electro-optical device having a high-resolution display area can perform both area scanning by line pair scanning that enables high-speed display and shifted line pair scanning. Can do.

Application Example 4 A scanning line driving circuit according to this application example includes a shift register circuit, a first type control line, a second type control line, a first switch, a second switch, and a first type AND circuit. The first type output of the register circuit is electrically connected to the first input of the first type AND circuit, and the first type control line and the second input of the first type AND circuit are electrically connected via the first switch. The second type control line and the second input of the first type AND circuit are electrically connected via the second switch, and the output of the first type AND circuit is electrically connected to the first type scan line. The first switch and the second switch are arranged outside a region where the shift register circuit and the first type AND circuit are arranged.
According to this configuration, since the second input of the first type AND circuit is electrically connected to the first type control line or the second type control line, the first type scan line is shifted from the first type AND circuit. A logical product signal of a first-class output signal of the register circuit (referred to as first-class output signal) and a first-class control line signal (referred to as first-class control signal), or a first-class output signal It is possible to output a logical product signal with a signal of the second type control line (referred to as a second type control signal). That is, according to this configuration, a scanning signal output to the first type scanning line (referred to as a first type scanning signal) is a logical product of the first type output signal and the first type control signal, and the first It can be switched by a logical product signal of the seed output signal and the second kind control signal. In addition, the interval between adjacent scanning lines can be reduced.

Application Example 5 In the scanning line driving circuit according to Application Example 4, the first type control that electrically connects the second input of the first type AND circuit to the first switch and the second switch. It is preferable to provide an output line (even column control output line).
According to this configuration, the first type scanning signal, the logical product signal of the first type output signal and the first type control signal, the logical product signal of the first type output signal and the second type control signal, It can be either one of these. In addition, the interval between adjacent scanning lines can be reduced.

Application Example 6 In the scanning line driving circuit according to Application Example 4 or 5, the second type AND circuit is provided, and the second type output of the shift register circuit is electrically connected to the first input of the second type AND circuit. The second input of the second-type AND circuit is electrically connected to the first-type control line, and the output of the second-type AND circuit is electrically connected to the second-type scanning line. Is preferred.
According to this configuration, a signal output to the second type scanning line (referred to as a second type scanning signal) includes a second type output of the shift register circuit (referred to as a second type output signal) and a first type control signal. Therefore, the second type scanning signal can be the same signal as the first type scanning signal or can be a different signal. As a result, it is possible to perform area scanning both by line pair scanning that enables high-speed display and shifted line pair scanning.

Application Example 7 In the scanning line driving circuit according to Application Example 6, the second type control output line that electrically connects the second input of the second type AND circuit and the first type control line is provided. Things are preferable.
According to this configuration, it is possible to perform area scanning both by line pair scanning that enables high-speed display and shifted line pair scanning while narrowing the interval between adjacent scanning lines.

Application Example 8 In the scanning line driving circuit according to Application Example 6 or 7, the third switch is provided between the second input of the second-type AND circuit and the first-type control line. Is preferred.
A first switch is provided between the second input of the first type AND circuit and the first type control line. According to this configuration, since the third switch is provided between the second input of the second type AND circuit and the first type control line, when the first type control signal is input to the first type AND circuit. And the signal delay when the first-type control signal is input to the second-type AND circuit can be made comparable. Therefore, the phase difference between the first type scanning signal and the second type scanning signal can be reduced. As a result, when the scanning line driving circuit is applied to the electro-optical device, a uniform display without noticeable unevenness can be obtained.

Application Example 9 In the scanning line driving circuit according to Application Example 8, it is preferable that the third switch is in an ON state during a period in which the scanning line driving circuit is operating.
Since the first switch is in the ON state when the first type control signal is input to the first type AND circuit, according to this configuration, the signal delay time constant based on the first switch and the signal delay based on the third switch The time constant can be made comparable. Therefore, the signal delay when the first-type control signal is input to the first-type AND circuit and the signal delay when the first-type control signal is input to the second-type AND circuit are set to the same level. Can do.

Application Example 10 A scanning line driving circuit according to this application example is a scanning line driving circuit capable of switching between a first display method and a second display method, and shifts a signal and outputs a shift output signal for each stage. Shift register circuit to output and k lines from first group first enable signal line to which first group first enable signal is supplied to first group k enable signal line to which first group k enable signal is supplied The second group k enable signal is supplied from the first group enable signal line (k is an integer of 1 or more), and the second group first enable signal line is supplied with the second group first enable signal. Any one of the k second group enable signal lines up to the group k enable signal line, the shift output signal, and the first group first enable signal to the second group k enable signal are input, and the corresponding scanning line Output scanning signal to And the first group α-enable signal line is electrically connected to the (2α-1) th logic circuit corresponding to the (2α-1) th scan line (α is 1). The second group β enable signal line is electrically connected to the (2β) logic circuit corresponding to the (2β) scan line (β is an integer from 1 to k), In the first display method, the first drive method and the second drive method are alternately performed. In the first drive method, the first group α-enable signal and the second group α-enable signal are equal, The two-drive system is characterized in that the first group (k + 1) enable signal is the first group first enable signal, and the first group (α + 1) enable signal and the second group α enable signal are equal.
According to this configuration, the interval between adjacent scanning lines can be reduced. Therefore, when the scanning line driving circuit is applied to an electro-optical device, the electro-optical device having a high-resolution display area can perform both area scanning by line pair scanning that enables high-speed display and shifted line pair scanning. Can do.

Application Example 11 An electro-optical device driving method according to this application example includes first-type scanning lines and second-type scanning lines, and can switch between a first display method and a second display method. A driving method of the apparatus, using the first type output signal, the second type output signal, the first type control signal, and the second type control signal from the shift register circuit, and at the time of the first display method The first driving method and the second driving method are alternately performed. In the first driving method, the logical product of the first type output signal and the first type control signal is supplied to the first type scanning line. The logical product of the second type output signal and the first type control signal is supplied to the second type scanning line, and in the second driving method, the first type output signal and the second type are supplied to the first type scanning line. The logical product of the control signal is supplied, and the logical product of the second type output signal and the first type control signal is supplied to the second type scanning line. A logical product of the first type output signal and the first type control signal is supplied to the first type scanning line, and a logical product of the second type output signal and the first type control signal is supplied to the second type scanning line. It is characterized by things.
According to this method, in the first display method, the second type scanning signal can be the same signal as the first type scanning signal, or can be a different signal. As a result, it is possible to perform area scanning both by line pair scanning that enables high-speed display and shifted line pair scanning. Furthermore, it is possible to perform area scanning also in the second display method in which scanning lines are selected line by line.

Application Example 12 In the driving method of the electro-optical device according to Application Example 11, an output prohibition period is provided between the first drive method and the second drive method, and in the output prohibition period, the first It is preferable that the seed control signal and the second kind control signal correspond to logic 0.
According to this method, it is possible to avoid a malfunction that may occur when the first drive method and the second drive method are switched. For example, it is possible to suppress generation of unnecessary through current when switching between the first drive method and the second drive method. Therefore, it is possible to avoid a situation in which the electro-optical device stops operating due to a large instantaneous through current.

Application Example 13 In the driving method of the electro-optical device according to Application Example 12, one frame image formed by the first driving method or the second driving method includes f field images. (F is an integer of 2 or more) Each of the f-1 field images from the first field image is composed of an even number of subfields, and the fth field image is composed of an odd number of subfields. Preferably composed.
One frame image is preferably composed of an even number of subfields. However, depending on the even-numbered final subfield weighting (final subfield period), the output prohibition period may start while the even-numbered final subfield scans the display area. In such a case, if the even-numbered final subfield is omitted and the preceding odd-numbered subfield is the actual final subfield, the odd-numbered final subfield is set in all scanning lines at the stage when the output prohibition period starts. Since the subfield is already written, the display corresponding to the result continues. Therefore, according to this method, it is possible to avoid a display defect in the even-numbered final subfield that was originally planned and to realize a good display.

Application Example 14 An electro-optical device including the scanning line driving circuit according to any one of Application Examples 1 to 10.
According to this configuration, it is possible to perform area scanning by both line pair scanning and shifted line pair scanning that enable high-speed display, and also in the second display method in which scanning lines are selected line by line. An electro-optical device that can perform area scanning is realized.

Application Example 15 An electro-optical device that is driven by the driving method of the electro-optical device according to any one of Application Examples 11 to 13.
According to this configuration, it is possible to perform area scanning by both line pair scanning and shifted line pair scanning that enable high-speed display, and also in the second display method in which scanning lines are selected line by line. An electro-optical device that can perform area scanning is realized.

Application Example 16 An electronic apparatus including the electro-optical device according to Application Example 14 or 15.
According to this configuration, it is possible to perform area scanning by both line pair scanning and shifted line pair scanning that enable high-speed display, and also in the second display method in which scanning lines are selected line by line. Thus, an electronic apparatus including an electro-optical device that can perform area scanning is realized.

The schematic diagram of an example projection type display apparatus of an electronic device. The circuit block diagram of an electronic device. The circuit diagram of a pixel. FIG. 3 is a circuit configuration diagram of a scanning line driving circuit according to the first embodiment. An example of a shift register circuit used in a scan line driver circuit. The figure explaining the enable signal which changes with mode signals MODE. An example of the timing chart in a 2nd display system. An example of the timing chart at the time of switching from a 1st drive system to a 2nd drive system by a 1st display system. An example of a timing chart when switching from the second drive method to the first drive method in the first display method. The figure explaining the display method. FIG. 6 is a circuit configuration diagram of a scanning line driving circuit according to a second embodiment. The timing chart explaining the drive method at the time of performing the display of a 2nd drive system, after performing the display of a 1st drive system by forward shift. The timing chart explaining the drive method at the time of performing the display of a 1st drive system, after performing the display of a 2nd drive system by forward shift. The timing chart in the modification 1. The timing chart in the modification 1. The timing chart in the modification 2. The timing chart in the modification 2.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the scale of each layer and each member is made different from the actual scale so that each layer and each member can be recognized.

(Embodiment 1)
"Outline of electronic equipment"
FIG. 1 is a schematic diagram of a projection display device (a three-plate projector) that is an example of an electronic apparatus. Hereinafter, the configuration of the electronic apparatus will be described with reference to FIG.

  The electronic apparatus (projection type display device 1000) includes three electro-optical devices 20 (refer to FIG. 2; hereinafter, abbreviated as first panel 201, second panel 202, and third panel 203) and these electro-optical devices 20. And at least a control device 30 for supplying a control signal. The first panel 201, the second panel 202, and the third panel 203 are the three electro-optical devices 20 corresponding to different display colors (red, green, and blue). Hereinafter, unless it is particularly necessary to distinguish the first panel 201, the second panel 202, and the third panel 203, they are collectively referred to as the electro-optical device 20.

  The illumination optical system 1100 supplies the red component r of the emitted light from the illumination device (light source) 1200 to the first panel 201, supplies the green component g to the second panel 202, and supplies the blue component b to the third panel 203. To supply. Each electro-optical device 20 functions as a light modulator (light valve) that modulates each color light supplied from the illumination optical system 1100 according to a display image. The projection optical system 1300 synthesizes the emitted light from each electro-optical device 20 and projects it onto the projection surface 1400.

"Circuit configuration of electronic equipment"
FIG. 2 is a circuit configuration diagram of the electronic device. Next, the circuit configuration of the electronic device will be described with reference to FIG.

  The electronic apparatus according to this embodiment includes an electro-optical device that can switch between the first display method and the second display method. As an example, the first display method is a method of displaying a three-dimensional image that makes an observer perceive a stereoscopic effect. On the other hand, a 2nd display system is a system which displays a high-definition two-dimensional image as an example. As shown in FIG. 2, the electronic apparatus includes at least stereoscopic glasses 10, an electro-optical device 20, and a driving device 50, and further includes a glasses control circuit 31 that controls the stereoscopic glasses 10. Yes. With this configuration, it is possible to make an observer recognize a three-dimensional image in the first display method. The reason why the first display method and the second display method can be switched is that the scanning line driving circuit supports the switching operation.

  The stereoscopic glasses 10 are glasses-type instruments worn by an observer when viewing a three-dimensional image displayed by the electro-optical device 20, and include a right-eye shutter 12 and a left-eye that are positioned in front of the observer's right eye. And a shutter 14 for the left eye located in front of the camera. Each of the right-eye shutter 12 and the left-eye shutter 14 is controlled to an open state that transmits the irradiation light and a closed state that blocks the irradiation light. For example, a liquid crystal shutter that changes from one of the open state and the closed state to the other depending on the alignment direction of the liquid crystal according to the applied voltage can be employed as the right-eye shutter 12 and the left-eye shutter 14.

  The electro-optical device 20 includes a display area 42 in which a plurality of pixels 21 are arranged. In the display area 42, scanning lines 22 and signal lines 23 intersecting each other are formed. The scanning lines 22 extend in the row direction (X direction), and the signal lines 23 extend in the column direction (Y direction) intersecting the extending direction of the scanning lines 22. When the i-th scanning line 22 is specified among the scanning lines 22, it is expressed as a scanning line Gi. Each pixel 21 is arranged in a matrix corresponding to each intersection of the scanning line 22 and the signal line 23. In the electro-optical device 20, a display area 42 (m is an integer of 4 or more and n is an integer of 1 or more) including m scanning lines 22 and n signal lines 23 is formed.

  The electro-optical device 20 is driven by a driving device 50. The drive device 50 includes a drive circuit 51 that drives each pixel 21, a display signal supply circuit 32 that supplies a display signal to the drive circuit 51, and a storage circuit 33 that temporarily stores a frame image. Composed. As will be described later, one frame image constituting one frame includes odd-numbered subfields and even-numbered subfields. A display signal to be a field or even subfield is produced and supplied to the drive circuit 51.

  The drive circuit 51 includes a scanning line drive circuit 52 and a signal line drive circuit 53. The scanning line driving circuit 52 outputs a scanning signal for selecting or deselecting a pixel in the row direction to each scanning line 22, and the scanning line 22 transmits this scanning signal to the pixel 21. In other words, the scanning signal has a selected state and a non-selected state, and the scanning line 22 can be appropriately selected in response to the scanning signal from the scanning line driving circuit 52. As will be described later, the scanning line driving circuit 52 includes a shift register circuit 55 (see FIG. 5), and a signal for shifting the shift register circuit 55 is output as a shift output signal for each stage. A scanning signal is formed using this shift output signal. The signal line driving circuit 53 supplies the image signal Vij to each of the n signal lines 23 in synchronization with the selection of the scanning line 22, where i is an integer from 1 to m and j is from 1 to n. Is an integer. An image signal Vij is supplied to the pixel 21 located in i row and j column.

  In this way, the electro-optical device 20 includes the first scanning line 22 (for example, the first scanning line G1), the first pixel 21 connected to the first scanning line 22, and the first scanning line. 22, the second scanning line 22 adjacent to the shift register circuit 55 in the shift direction (for example, the second scanning line G2), the second pixel 21 connected to the second scanning line 22, and the second The third scanning line 22 adjacent to the scanning line 22 in the shift direction of the shift register circuit 55 (for example, the third scanning line G3), and the third pixel 21 connected to the third scanning line 22. The fourth scanning line 22 (for example, the fourth scanning line G4) adjacent to the third scanning line 22 in the shift direction of the shift register circuit 55 and the fourth scanning line 22 are connected to the fourth scanning line 22. Pixel 21, first pixel 21, second pixel 21, third pixel 21, and fourth pixel 21 A signal line for supplying an image signal to the element 21, and includes at least a. In the present embodiment, the electro-optical device and the driving method thereof will be described with m = 820 and n = 1300 as an example. In this case, a WXGA image of 800 rows × 1280 rows is displayed in the display area 42 of 820 rows × 1300 columns.

  Note that the first scanning line 22 does not necessarily mean only the first scanning line G1, and the (2kp + 1) th scanning line G (2kp + 1) is generally the first scanning line 22. Here, k is the number of enable signals described later, and p is an integer from 0 to m / (2k) -1. In this embodiment, since m = 820 and k = 10, p is an integer from 0 to 40. Therefore, the first scanning line 22 includes the first scanning line G1 (p = 0), the 21st scanning line G21 (p = 1), the 41st scanning line G41 (p = 2), This corresponds to the scanning line G801 (p = 40) in the 801th row. Similarly, the second scanning line 22 is generally the (2 kp + 2) -th scanning line G (2 kp + 2). In the present embodiment, the second scanning line G2 (p = 0), the 22nd-row scanning line G The scanning line G22 (p = 1), the 42nd scanning line G42 (p = 2), and the 802th scanning line G802 (p = 40) correspond to the second scanning line 22. The third scanning line 22 is generally the (2 kp + 3) -th scanning line G (2 kp + 3). In this embodiment, the third scanning line G3 (p = 0) and the 23-th scanning The line G23 (p = 1), the 43rd scanning line G43 (p = 2), and the 803th scanning line G803 (p = 40) correspond to the third scanning line 22. The fourth scanning line 22 is generally the (2 kp + 4) -th scanning line G (2 kp + 4). In the present embodiment, the fourth scanning line G4 (p = 0) and the 24th scanning line are used. The line G24 (p = 1), the 44th scanning line G44 (p = 2), and the 804th scanning line G804 (p = 40) correspond to the fourth scanning line 22. Similarly, the 2k-th scanning line 22 is generally the (2kp + 2k) -th scanning line G (2kp + 2k). In this embodiment, k = 10, so the 20th-row scanning line G20 ( p = 0), the 40th scanning line G40 (p = 1), the 60th scanning line G60 (p = 2), and the 820th scanning line G820 (p = 40). Corresponds to the scanning line 22.

  In this embodiment, the electro-optical device 20 is formed using a glass substrate (not shown), and the drive circuit 51 is formed on the glass substrate using a thin film element such as a thin film transistor. Further, the spectacles control circuit 31, the display signal supply circuit 32, and the storage circuit 33 constitute a control device 30. In addition to this configuration, the electro-optical device 20 may be formed using a glass substrate, and the drive circuit 51 may be an integrated circuit formed on a single crystal semiconductor substrate. Both the electro-optical device 20 and the drive circuit 51 may be a single crystal semiconductor. It is good also as a structure formed in a board | substrate. Further, a configuration in which the spectacles control circuit 31, the display signal supply circuit 32, and the storage circuit 33 are mounted on a single integrated circuit, or a configuration in which two of these circuits are mounted on a single integrated circuit, A configuration in which the signal supply circuit 32, the eyeglass control circuit 31, and the storage circuit 33 are distributed in separate integrated circuits may be employed.

`` Pixel configuration ''
FIG. 3 is a circuit diagram of each pixel. Next, the configuration of the pixel 21 will be described with reference to FIG.

  The electro-optical device 20 of the present embodiment is a liquid crystal device, and the electro-optical material is the liquid crystal 26. As shown in FIG. 3, each pixel 21 includes a liquid crystal element CL and a pixel transistor 24. The liquid crystal element CL is an electro-optical element having a pixel electrode 25 and a common electrode 27 facing each other, and a liquid crystal 26 of an electro-optical material is disposed between these electrodes. The transmittance of light passing through the liquid crystal 26 changes according to the electric field applied between the pixel electrode 25 and the common electrode 27. As the electro-optic material, an electrophoretic material may be used instead of the liquid crystal 26. In that case, the electro-optical device 20 becomes an electrophoretic device and is used for an electronic book or the like.

  The pixel transistor 24 is composed of an N-type thin film transistor having a gate connected to the scanning line 22, and is interposed between the liquid crystal element CL and the signal line 23 to establish electrical connection (conduction / non-conduction) between the two. Control. Accordingly, the pixel 21 (liquid crystal element CL) performs display in accordance with the potential (image signal Vij) of the signal line 23 when the pixel transistor 24 is controlled to be in the on state. Note that illustration of an auxiliary capacitor connected in parallel to the liquid crystal element CL is omitted.

"Scanning line drive circuit"
FIG. 4 is a schematic diagram of the overall configuration of the scanning line driving circuit according to the first embodiment. FIG. 5 is an example of a shift register circuit used in the scan line driver circuit. Next, the configuration of the scanning line driving circuit 52 will be described with reference to FIGS.

  The scanning line driving circuit 52 is a circuit capable of switching between the first display method and the second display method. The first display method is a method for displaying a three-dimensional image at high speed, and the first drive method and the second drive method are alternately repeated. In the present embodiment, the first driving method is line pair scanning, and the second driving method is shifted line pair scanning. Since high-speed driving uses a driving method called area scanning, in the first display system, area scanning is performed by the first driving system (line pair scanning) and the second driving system (shifted line pair scanning). Line pair scanning and shifted line pair scanning will be described in detail later. The second display method is a method of displaying a high-resolution two-dimensional image at high speed, and is a display method in which scanning lines are selected one by one and area scanning is performed. The area scanning will be described later in detail.

  The scanning line driving circuit 52 includes a circuit that performs single scanning for selecting one scanning line 22 from the m scanning lines 22 in order to perform the second display method. At the same time, the scanning line driving circuit 52 performs line pair scanning for selecting each line pair as a pair of two scanning lines 22 adjacent to the m scanning lines 22 in order to perform the first display method. In addition, in the two adjacent scanning lines 22 from the m scanning lines 22, the scanning line 22 combined with the line pair is shifted by one, and a set of different scanning lines 22 is shifted as a shifted line pair. It also includes a circuit that performs shifted line pair scanning that is selected every time. An image formed using line pair scanning may be referred to as a line pair image, and an image formed using shifted line pair scanning may be referred to as a shifted line pair image.

  Single scanning is a scanning method in which the scanning lines 22 are appropriately selected one by one. For example, the first scanning line G1, the second scanning line G2, and the third scanning line G3 are appropriate one by one. A scan line 22 is selected. The line pair scanning is, for example, a line pair of the first scanning line G1 and the second scanning line G2, a line pair of the third scanning line G3 and the fourth scanning line G4, and five lines. A line pair of the sixth scanning line G5 and the sixth scanning line G6, and the (2s-1) th scanning line G (2s-1) and the (2s) th scanning line G (2s). Select appropriately as a pair (s is an integer from 1 to m / 2). The shifted line pair scanning is, for example, a line pair of the second scanning line G2 and the third scanning line G3, a line pair of the fourth scanning line G4 and the fifth scanning line G5, 6 A line pair of the scanning line G6 of the row and the scanning line G7 of the seventh row, and a scanning line G (2t) of the (2t) row and a scanning line G (2t + 1) of the (2t + 1) row are paired. Select as appropriate (t is an integer from 1 to m / 2-1). Thus, the scanning line 22 to be combined is shifted by one in the line pair and the shifted line pair.

  The selection of a specific scanning line 22 means that a scanning signal in a selected state (a signal corresponding to logic 1) is supplied to the scanning line 22. In addition, when a specific scanning line 22 is not selected (a specific scanning line 22 is not selected), a scanning signal in a non-selected state (a signal corresponding to logic 0) is supplied to the scanning line 22. Means that In this embodiment, since an N-type thin film transistor is used for the pixel transistor 24, the scanning signal in the selected state is a high potential (eg, positive power supply potential Vdd), and the scanning signal in the non-selected state is a low potential (eg, negative potential). Power supply potential Vss). In this specification, a high potential signal is represented by a high potential signal H, and a low potential signal is represented by a low potential signal L.

  As shown in FIG. 4, the display signal supplied from the control device 30 to the drive circuit 51 includes a signal (referred to as a Y start pulse signal DY) supplied to the scan line drive circuit 52 and the scan line drive circuit 52. A clock signal (referred to as a Y clock CKY) supplied to the signal, a signal (referred to as a Y clock bar CKYB) supplied to the scanning line driving circuit 52 and having a phase opposite to that of the Y clock CKY, and a scanning line driving circuit 52 The supplied shift direction signal (referred to as Y direction DIRY), the signal supplied to the scanning line driving circuit 52 and having a phase opposite to that of the Y direction DIRY (referred to as Y direction bar DIRYB), and the scanning line driving circuit 52 The enable signal supplied, the mode signal MODE supplied to the scanning line driving circuit 52, and the mode signal supplied to the scanning line driving circuit 52. It includes opposite-phase become signals (referred to as a mode bar signal MODEB), against MODE. The enable signals include k types from the first enable signal ENB1 to the kth enable signal ENBk. The number k of enable signals is an integer equal to or greater than 2, and m / (2k) is an integer. This simplifies the configuration of display signals such as enable signals. In this embodiment, k = 10 and m / (2k) = 820/20 = 41. That is, ten types of enable signals from the first enable signal ENB1 to the tenth enable signal ENB10 are used. The display signal supplied from the control device 30 to the drive circuit 51 includes a Y start pulse signal DY, a Y clock CKY, a Y direction DIRY, an enable signal, and a mode signal MODE. May be. In this case, negative phase signals such as the Y clock bar CKYB, the Y direction bar DIRYB, and the mode bar signal MODEB are generated in the scanning line driving circuit 52 using a negative circuit (inverter circuit).

  FIG. 4 shows an example of a circuit configuration that enables the various scanning methods described above. The scanning line driving circuit 52 includes at least a shift register circuit 55, a first type control line, a second type control line, a logic circuit, and a common control circuit 54.

  As shown in FIG. 5, the shift register circuit 55 is a bidirectional type, shifts a signal (Y start pulse signal DY), and outputs a shift output signal for each stage. That is, the shift register circuit 55 sequentially transfers the Y start pulse signal DY in synchronization with the Y clock CKY and the Y clock bar CKYB, so that the shift output signal is transferred to the first stage output SR1 and the second stage output SR2. ,... Are sequentially output to the m-th stage output SRm. An example of a specific configuration of the shift register circuit 55 is shown in FIG. 5. When the Y direction DIRY is the low potential signal L and the Y direction bar DIRYB is the high potential signal H, the Y start pulse signal DY is the first one. The data is transferred from the stage output SR1 to the m-th stage output SRm (from top to bottom in FIG. 4) (referred to as a forward shift). On the other hand, when the Y direction DIRY is the high potential signal H and the Y direction bar DIRYB is the low potential signal L, the Y start pulse signal DY is changed from the mth stage output SRm to the first stage output SR1 (in FIG. 4, from bottom to top). ) Are transferred (referred to as reverse shift). The i-th stage output SRi of the shift register circuit 55 corresponds to the i-th scanning line Gi (i is an integer from 1 to m).

  The output of the shift register circuit 55 is classified into a first type output and a second type output. In the present embodiment, the first type output corresponds to the even-numbered stage output and corresponds to the (2s) -th stage output SR (2s), and the second type output corresponds to the odd-numbered stage output and the (2s-1) -th stage. The output SR (2s-1) corresponds (s is an integer from 1 to m / 2). Similarly, the scanning line 22 is classified into a first type scanning line and a second type scanning line. In other words, the first-type scanning line is a scanning line corresponding to the first-type output, and in the present embodiment, the even-numbered scanning line 22 corresponds to the (2s) -th scanning line G (2s). The second type scanning line is a scanning line corresponding to the second type output, and in the present embodiment, the odd-numbered scanning line 22 corresponds to the (2s-1) th scanning line G (2s-1). (S is an integer from 1 to m / 2).

  The logic circuit is provided for each scanning line 22 and outputs a logical product of input signals to the corresponding scanning line 22 as a scanning signal. Specifically, the logic circuit corresponding to the first type scan line (the scan line 22 in the even-numbered row in this embodiment) is the first type AND circuit AND1, and therefore the output of the first type AND circuit AND1 is the first type. It is electrically connected to a kind of scanning line. Similarly, the logic circuit corresponding to the second type scanning line (the odd-numbered scanning line 22 in this embodiment) is the second type AND circuit AND2, and the output of the second type AND circuit AND2 is the second type scanning line. Is electrically connected. More specifically, the logic circuit corresponding to the first scan line is the first logic circuit, the logic circuit corresponding to the second scan line is the second logic circuit, and the third scan line is The corresponding logic circuit is the third logic circuit, the logic circuit corresponding to the fourth scan line is the fourth logic circuit, and so on.

  The logic circuit has at least two inputs, a first input and a second input, one of which is electrically connected to the output stage of the shift register circuit 55. Specifically, the first input of the first-type AND circuit AND1 is electrically connected to the first-type output of the shift register circuit 55 (in this embodiment, the even-stage output), and the first input of the second-type AND circuit AND2. The input is electrically connected to the second type output of the shift register circuit 55 (odd stage output in this embodiment). The second input of the logic circuit will be described later.

  In this specification, that the terminal 1 and the terminal 2 are electrically connected means that the terminal 1 and the terminal 2 can be in the same logic state. Specifically, in addition to the case where the terminal 1 and the terminal 2 are directly connected by wiring, the case where they are connected via a resistance element, a switching element, a capacitive element, a buffer circuit, or the like is included. That is, even if the potential at the terminal 1 and the potential at the terminal 2 are slightly different, if the same logic is given on the circuit, the terminal 1 and the terminal 2 are electrically connected. Therefore, for example, even when a buffer circuit including an even number of inverter circuits connected in series is included between the logic circuit and the scanning line 22, the output of the logic circuit and the scanning line 22 are electrically connected. It will be a thing. Also, when a switching element for blocking or passing the output signal of the logic circuit is provided between the output terminal of the logic circuit and the scanning line 22, the output of the logic circuit is in an on state. Since the signal is supplied to the scanning line 22, the two are electrically connected.

  The first type control line and the second type control line are wires to which an enable signal is supplied. There are k kinds of enable signals, and the enable signal lines corresponding to the respective enable signals are provided in the scanning line driving circuit 52. That is, the kth enable signal ENBk is supplied to the kth enable signal line. For example, the first enable signal line is supplied with the first enable signal ENB1, the second enable signal line is supplied with the second enable signal ENB2, and the third enable signal line is supplied with the third enable signal ENB3. . In this embodiment, since k = 10, the scanning line driving circuit 52 includes the first enable signal line to the tenth enable signal line.

  The first-type control line and the second-type control line are the scanning line 22 ((2s-1) -th scanning line G (2s-1) and (2s) -th scanning line G (2s) of the line pair. , S is an enable signal line classified with respect to 1 to m / 2, and in each line pair, a second-type AND circuit AND2 (in this embodiment, a logic located on the odd-numbered scanning line 22). The first type control line is electrically connected to the second input of the circuit), and the second input of the first type AND circuit AND1 (the logic circuit located in the even-numbered scanning line 22 in this embodiment). The second type control line can be electrically connected. A first type control line may also be electrically connected to the second input of the first type AND circuit AND1.

  The first type control line and the second type control line are related to the first type AND circuit AND1 corresponding to the scanning line G (2q) in the (2q) -th row (q is an arbitrary integer from 1 to m / 2). Enable electrically connected to the second input of the first-type AND circuit AND1 and the second input of the second-type AND circuit AND2 corresponding to the scanning line G (2q-1) in the (2q-1) th row. The signal line is a first-type control line and corresponds to the second input of the first-type AND circuit AND1 of the (2q) -th scanning line G (2q) and the (2q + 1) -th scanning line G (2q + 1). The enable signal line electrically connected to the second input of the second type AND circuit AND2 is the second type control line. In the last row of q = m / 2, since the (2q + 1) -th scanning line G (2q + 1) does not exist, this is regarded as the first scanning line G1. In FIG. 4, since the scanning line number increases from top to bottom, for convenience, the first type control line may be abbreviated as the upper enable signal line and the second type control line may be abbreviated as the lower enable signal line. is there. In short, the upper enable signal among the two enable signal lines that can be electrically connected to the second input of the first-type AND circuit AND1 located on the first-type scan line (even-numbered-row scan line in the present embodiment). The line is a first type control line, and the lower enable signal line is a second type control line. For example, in the line pair of the scanning line G1 in the first row and the scanning line G2 in the second row, the first type control line (upper enable signal line) is the first enable signal line, and the second type control line (lower Side enable signal line) is a second enable signal line. Similarly, in the line pair of the third row scanning line G3 and the fourth row scanning line G4, the first type control line (upper enable signal line) is the second enable signal line, and the second type control line ( The lower enable signal line) is a third enable signal line. In the line pair of the 819th scanning line G819 and the 820th scanning line G820, the first type control line (upper enable signal line) is the tenth enable signal line, and the second type control line (lower). Side enable signal line) is a first enable signal line.

  The common control circuit 54 includes a first switch Sw1 and a second switch Sw2, and is configured to supply any enable signal to the second input of the logic circuit. Specifically, in the common control circuit 54, the first type control line and the second input of the first type AND circuit AND1 are electrically connected via the first switch Sw1, and the second type control line and the first input are connected to the first type control circuit AND1. The second input of the seed AND circuit AND1 is electrically connected via the second switch Sw2, and the first type control line and the second input of the second kind AND circuit AND2 are electrically connected. Has been. In FIG. 4, the scanning line numbers increase from top to bottom, and the first switch Sw1 and the second switch Sw2 include the first type scanning line (even-numbered scanning line in this embodiment) and the first type AND circuit AND1. In this embodiment, the first switch Sw1 may be abbreviated as an even-row upper switch and the second switch Sw2 may be abbreviated as an even-row lower switch. .

  The first switch Sw1 and the second switch Sw2 are pass gates that perform exclusive operations. That is, when the first switch Sw1 is in a signal conduction state, the second switch Sw2 is in a signal cutoff state, and when the first switch Sw1 is in a signal cutoff state, the second switch Sw2 is a signal cutoff state. Is in a conductive state. In the present embodiment, exclusive CMOS pass gates are used for the first switch Sw1 and the second switch Sw2. Specifically, in the first switch Sw1, a first P-type transistor and a first N-type transistor are arranged in parallel between the first type control line and the second input of the first type AND circuit AND1, A mode signal MODE is supplied to the gate of the P-type transistor, and a mode bar signal MODEB is supplied to the gate of the first N-type transistor. The second switch Sw2 includes a second N-type transistor and a second N-type transistor arranged in parallel between the second-type control line and the second input of the first-type AND circuit AND1. A mode signal MODE is supplied to the gate of the second P-type transistor, and a mode bar signal MODEB is supplied to the gate of the second P-type transistor. Therefore, when the mode signal MODE is the low potential signal L and the mode bar signal MODEB is the high potential signal H, the first switch Sw1 is turned on and the second switch Sw2 is turned off. That is, when the mode signal MODE is the low potential signal L and the mode bar signal MODEB is the high potential signal H, the second input of the first type AND circuit AND1 and the first type control line are electrically connected. When the mode signal MODE is the high potential signal H and the mode bar signal MODEB is the low potential signal L, the first switch Sw1 is cut off and the second switch Sw2 is turned on. That is, when the mode signal MODE is the high potential signal H and the mode bar signal MODEB is the low potential signal L, the second input of the first type AND circuit AND1 and the second type control line are electrically connected.

  When the first switch Sw1 and the second switch Sw2 are configured by CMOS pass gates, a signal corresponding to logic 1 (for example, a high potential signal H) and a signal corresponding to logic 0 (for example, a low potential signal L) are The scanning line drive circuit 52 that can shorten the delay through the one switch Sw1 and the second switch Sw2 and can operate at high speed is realized. On the other hand, when the first switch Sw1 and the second switch Sw2 are formed of single-channel transistors, the circuit area can be reduced. In order to form the first switch Sw1 and the second switch Sw2 with single-channel transistors, a first P-type transistor is used for the first switch Sw1, and a second N-type transistor is used for the second switch Sw2. In some cases, a first N-type transistor is used for the first switch Sw1, and a second P-type transistor is used for the second switch Sw2. When a first P-type transistor is used for the first switch Sw1 and a second N-type transistor is used for the second switch Sw2, a mode signal MODE is supplied to each gate. Conversely, when a first N-type transistor is used for the first switch Sw1 and a second P-type transistor is used for the second switch Sw2, the mode bar signal MODEB is supplied to each gate. In order to make the signal delay amount via the first switch Sw1 and the signal delay amount via the second switch Sw2 approximately the same, the size of the first N-type transistor and the size of the second N-type transistor are the same, The size of the first P-type transistor and the size of the second P-type transistor are preferably the same. In order to form the first switch Sw1 and the second switch Sw2 with single-channel transistors, it is necessary that the threshold voltage of the transistors be smaller by several volts than the trip voltage of an inverter or the like.

  As shown in FIG. 4, the common control circuit 54 may further include a third switch Sw3 formed of a CMOS pass gate between the second input of the second-type AND circuit AND2 and the first-type control line. .

  In the third switch Sw3, a third P-type transistor and a third N-type transistor are arranged in parallel between the first-type control line and the second input of the second-type AND circuit AND2, and the gate of the third P-type transistor Is supplied with a low potential signal L, and the gate of the third N-type transistor is supplied with a high potential signal H. Therefore, the third switch Sw3 is always on during the period in which the scanning line driving circuit 52 is operating. That is, during the period in which the scanning line driving circuit 52 is operating, the second input of the second type AND circuit AND2 and the first type control line are always electrically connected.

  When the third switch Sw3 is composed of a CMOS pass gate, a signal corresponding to logic 1 (for example, a high potential signal H) and a signal corresponding to logic 0 (for example, a low potential signal L) pass through the third switch Sw3. The scanning line driving circuit 52 that can shorten the delay and can operate at high speed is realized. On the other hand, when the third switch Sw3 is formed of a single-channel transistor, the circuit area can be reduced. In order to form the third switch Sw3 with a single-channel transistor, there are a case where a third P-type transistor is used for the third switch Sw3 and a case where a third N-type transistor is used for the third switch Sw3. When a third P-type transistor is used for the third switch Sw3, the low potential signal L is supplied to the gate of the third P-type transistor. Conversely, when a third N-type transistor is used for the third switch Sw3, the high potential signal H is supplied to the gate of the third N-type transistor. When the third switch Sw3 is formed of a single channel type transistor, it is necessary that the threshold voltage of the transistor be smaller by several volts than the trip voltage of the inverter or the like.

  When the first-type control signal is input to the first-type AND circuit AND1, the first-type control signal comes via the first switch Sw1 that is in the on state. By providing the third switch Sw3 between the second input of the second-type AND circuit AND2 and the first-type control line, even when the first-type control signal is input to the second-type AND circuit AND2, The first type control signal comes through the third switch Sw3 in the on state. As a result, the time constant of the signal delay based on the first switch Sw1 and the time constant of the signal delay based on the third switch Sw3 can be made comparable, and the first type control signal is input to the first type AND circuit AND1. The signal delay at the time when the first type control signal is input to the second type AND circuit AND2 can be made comparable. In short, the phase difference between the first type scanning signal and the second type scanning signal can be reduced. As a result, when the scanning line driving circuit 52 is applied to the electro-optical device, a uniform display without noticeable unevenness can be obtained.

  In order to make the above effect more reliable, it is preferable that the first switch Sw1 and the third switch Sw3 have the same configuration. That is, if the first switch Sw1 is a CMOS configuration, the third switch Sw3 is also a CMOS configuration, and if the first switch Sw1 is a one-channel type of a P-type transistor, the third switch Sw3 is also a one-channel type of a P-type transistor, If the first switch Sw1 is an N-type transistor single channel type, the third switch Sw3 is also an N-type transistor single channel type. Also, it is preferable that the transistor sizes constituting these are the same in the first switch Sw1 and the third switch Sw3. Furthermore, in order to make the signal delay amount via the first switch Sw1 and the signal delay amount via the second switch Sw2 comparable, the size of the first N-type transistor and the size of the second N-type transistor are made the same, The size of the first P-type transistor and the size of the second P-type transistor are preferably the same. Accordingly, the size of the first N-type transistor, the size of the second N-type transistor, and the size of the third N-type transistor are the same, and the size of the first P-type transistor, the size of the second P-type transistor, and the size of the third P-type transistor. Most preferably, the transistor size is the same.

  The common control circuit 54 is disposed outside the region where the shift register circuit 55 and the logic circuit are disposed. That is, the common control circuit 54 is not provided in the region from each output stage of the shift register circuit 55 to the scanning line 22, and the upper or lower side outside the region where the shift register circuit 55 and the logic circuit are arranged. A common control circuit 54 is provided in the region. Therefore, in order to supply the output signal from the common control circuit 54 to the logic circuit, the first control output line CL1, the second control output line CL2, the third control output line CL3, the fourth control output line CL4,. A (2k) th control output line CL (2k) and 2k control output lines are provided. Further, a first logic circuit (a logic circuit corresponding to the scanning line G1 in the first row and a logic circuit corresponding to the scanning line G21 in the 21st row) provided in the scanning line G (2kp + 1) in the (2kp + 1) row. The first control output line CL1 is electrically connected to the logic circuit corresponding to the scanning line G41 in the 41st row and the logic circuit corresponding to the scanning line G801 in the 801th row, and (2kp + 2) rows A second logic circuit (a logic circuit corresponding to the scanning line G2 in the second row, a logic circuit corresponding to the scanning line G22 in the 22nd row, a 42nd row) The second control output line CL2 is electrically connected to the logic circuit corresponding to the scanning line G42, followed by the logic circuit corresponding to the scanning line G802 in the 802th row, and the scanning line G (2kp + 3) th row ( 2 kp + 3) third logic circuit (3 The logic circuit corresponding to the scanning line G3 of the eye, the logic circuit corresponding to the scanning line G23 of the 23rd row, the logic circuit corresponding to the scanning line G43 of the 43rd row, and the scanning line G803 of the 803th row. The third control output line CL3 is electrically connected to the corresponding logic circuit), and the fourth logic circuit (to the scanning line G4 in the fourth row) provided in the scanning line G (2kp + 4) in the (2kp + 4) row. A corresponding logic circuit, a logic circuit corresponding to the 24th scanning line G24, a logic circuit corresponding to the 44th scanning line G44, and a logic circuit corresponding to the 804th scanning line G804). The fourth control output line CL4 is electrically connected, and in the same manner, the (2k) th logic circuit (the 2kth scanning line G) provided on the (2kp + 2k) th scanning line G (2kp + 2k). Logic circuit corresponding to (2k) and 4k rows (The logic circuit corresponding to the scanning line G (4k) of the second row, the logic circuit corresponding to the scanning line G (6k) of the sixth row), and the logic circuit corresponding to the scanning line Gm of the mth row) 2k) The control output line CL (2k) is electrically connected. In short, the r-th logic circuit (the logic circuit corresponding to the r-th scanning line Gr or the (2k + r) -th scanning line G (2k + r)) provided on the (2kp + r) -th scanning line G (2kp + r). And a logic circuit corresponding to the scanning line G (4k + r) in the (4k + r) row, and a logic circuit corresponding to the scanning line G (m-2k + r) in the (m-2k + r) row. Is electrically connected to the r-th control output line CLr. Here, r is an arbitrary integer from 1 to k. For this reason, the extending direction of 2k control output lines such as the first control output line CL1, the second control output line CL2, the third control output line CL3, the fourth control output line CL4, etc. is the first scanning line, etc. It intersects with the extending direction of the scanning line 22.

  In short, the first switch Sw1, the second switch Sw2, and the third switch Sw3 are arranged outside the region where the shift register circuit 55, the first-type AND circuit AND1, and the second-type AND circuit AND2 are arranged. In addition, the first type control output line electrically connects the second input of the first type AND circuit AND1, and the first switch Sw1 and the second switch Sw2. The first type control output lines are the second control output line CL2, the fourth control output line CL4, the (2k) th control output line CL (2k), and the control output lines in even columns. Similarly, the second type control output line electrically connects the second input of the second type AND circuit AND2 and the first type control line. The second type control output lines are the first control output line CL1, the third control output line CL3, the (2k-1) th control output line CL (2k-1), and the control output lines in odd columns. By doing so, it is possible to perform area scanning by both line pair scanning and shifted line pair scanning that enable high-speed display, as described later, after narrowing the interval between adjacent scanning lines 22. become.

  In the present embodiment, the common control circuit 54 is a pass gate that performs the exclusive operation of the first switch Sw1 and the second switch Sw2. However, if the configuration of the common control circuit 54 satisfies the above-described function, Not limited. For example, the common control circuit 54 can be configured using a NAND circuit or the like. In this case, the gate load of the enable signal is always loaded. Therefore, if the common control circuit 54 is configured using pass gates that perform exclusive operations, the capacity load of the enable signal is reduced, and high-speed operation is possible.

  As a result of such a circuit configuration, the first-type AND circuit AND1 has a shift output signal (referred to as a first-type output signal) that appears at the first-type output of the shift register circuit 55 and an enable signal that appears at the first-type control line ( Or an enable signal appearing on the second type control line (referred to as a second type control signal) is input, and the logical product of these signals is output to the first type scan line. The For example, a shift output signal appearing at the second stage output SR2 of the shift register circuit 55 and the common control circuit 54 are output to the logic circuit (first-type AND circuit AND1) corresponding to the scanning line G2 in the second row. Either the first enable signal ENB1 or the second enable signal ENB2 is input. When the first enable signal ENB1 is input, the first switch Sw1 is on and the second switch Sw2 is off. On the contrary, when the second enable signal ENB2 is input, the second switch Sw2 is in the on state and the first switch Sw1 is in the off state. In short, with the above-described configuration, the scanning signal output to the first type scanning line (referred to as the first type scanning signal) is a logical product of the first type output signal and the first type control signal, and the first The signal is a logical product of the seed output signal and the second kind control signal. As a result, it is possible to switch between a logical product signal of the first type output signal and the first type control signal and a logical product signal of the first type output signal and the second type control signal.

  Further, the second type AND circuit AND2 receives a shift output signal (referred to as a second type output signal) appearing at the second type output of the shift register circuit 55 and a first type control signal, and the logical product of these is obtained. It is output to the second type scanning line (a signal output to the second type scanning line is referred to as a second type scanning signal). For example, a shift output signal that appears at the first stage output SR1 of the shift register circuit 55 and the common control circuit 54 are output to the logic circuit (second-type AND circuit AND2) corresponding to the scanning line G1 in the first row. The first enable signal ENB1 is input, and the logical product of these signals is output to the second type scanning line as the second type scanning signal.

  In this way, the scanning signal output from the logic circuit is the logical product of the shift output signal from the shift register circuit 55 and the enable signal selected by the common control circuit 54. Scanning and area scanning are realized.

"Logical Configuration"
FIG. 6 is a diagram illustrating an enable signal that is input to the second input of the logic circuit and changes according to the mode signal MODE. Next, signals referred to by the logic circuit of the scanning line driving circuit 52 configured as described above will be described.

  As a result of the configuration of the scanning line driving circuit 52 described above, the second input of the logic circuit corresponding to each scanning line 22 (a signal referred to by the logic circuit) differs depending on the mode signal MODE. When the mode signal MODE is the low potential signal L and the mode bar signal MODEB is the high potential signal H, the pair of scanning lines 22 forming a line pair refers to the same enable signal. For example, the logic circuit corresponding to the scanning line G1 in the first row and the logic circuit corresponding to the scanning line G2 in the second row refer to the first enable signal ENB1 and the logic circuit corresponding to the scanning line G3 in the third row. And the logic circuit corresponding to the scanning line G4 in the fourth row refers to the second enable signal ENB2. On the other hand, when the mode signal MODE is the high potential signal H and the mode bar signal MODEB is the low potential signal L, the pair of scanning lines 22 that are the shifted line pair refers to the same enable signal. For example, the logic circuit corresponding to the scanning line G820 in the 820th row and the logic circuit corresponding to the scanning line G1 in the first row refer to the first enable signal ENB1 and the logic circuit corresponding to the scanning line G2 in the second row. The logic circuit corresponding to the scanning line G3 in the third row refers to the second enable signal ENB2.

  Accordingly, the scanning line driving circuit 52 becomes a circuit that can switch between the first display method (three-dimensional display in the present embodiment) and the second display method (two-dimensional display in the present embodiment), and the first display. It is possible to alternately repeat the first driving method (line pair scanning in the present embodiment) and the second driving method (shifted line pair scanning in the present embodiment) while performing area scanning by the method. Further, the scanning line driving circuit 52 can perform area scanning even in the second display method.

  Specifically, the mode signal MODE is set to the low potential signal L and the mode bar signal MODEB is set to the high potential signal H in the first driving method (line pair scanning in the present embodiment). As a result, the common control circuit 54 includes the first logic circuit (the second type AND circuit AND2 corresponding to the scanning line G (2kp + 1) in the (2kp + 1) th row) and the second logic circuit ((2kp + 2). ) The first enable signal ENB1 is input to the first AND circuit AND1) in the logic circuit corresponding to the scanning line G (2kp + 2) in the row, and the scanning line G in the third logic circuit ((2kp + 3) row). A logic circuit corresponding to (2kp + 3) is a second-type AND circuit AND2), a fourth logic circuit (a logic circuit corresponding to the scanning line G (2kp + 4) in the (2kp + 4) row) and a first-type AND circuit AND1) , The second enable signal ENB2 is input, and the reference signal for the logic circuit is determined as shown by MODE = L in FIG. In short, in the case of the first driving method, the first scanning line and the second scanning line form a line pair, and the third scanning line and the fourth scanning line form a line pair. Therefore, area scanning can be realized using these line pairs.

  On the other hand, in the second driving method (shifted line pair scanning in this embodiment), the mode signal MODE is set to the high potential signal H and the mode bar signal MODEB is set to the low potential signal L. As a result, the common control circuit 54 inputs the first enable signal ENB1 to the first logic circuit, inputs the second enable signal ENB2 to the second logic circuit and the third logic circuit, and outputs the fourth logic signal. The third enable signal ENB3 is input to the circuit, and the reference signal for the logic circuit is determined as shown by MODE = H in FIG. In other words, in the second driving method, the (2k) scanning line and the first scanning line are shifted line pairs, and the second scanning line and the third scanning line are shifted line pairs. Therefore, the area scanning can be realized by using the shifted line pair. In this manner, area scanning can be performed by both line pair scanning that enables high-speed display and shifted line pair scanning. The area scanning will be described in detail later.

  In the second display method (two-dimensional display in the present embodiment), the mode signal MODE is the low potential signal L and the mode bar signal MODEB is the high potential signal H. As a result, the common control circuit 54 inputs the first enable signal to the first logic circuit and the second logic circuit, and inputs the second enable signal to the third logic circuit and the fourth logic circuit. Hereinafter, the reference signal of the logic circuit is determined as indicated by MODE = L in FIG. In short, in the second display method, the first scanning line (the first scanning line G1, the 21st scanning line G21, the 41st scanning line G41, and the 801th scanning line G801). ) And the second scanning line (the second scanning line G2, the 22nd scanning line G22, the 42nd scanning line G42, the 802th scanning line G802) and the first enable signal ENB1. The scanning line group is a third scanning line (the third scanning line G3, the 23rd scanning line G23, the 43rd scanning line G43, and the 803th scanning line G803). And the fourth scanning line (the fourth scanning line G4, the 24th scanning line G24, the 44th scanning line G44, and the 804th scanning line G804) refer to the second enable signal ENB2. In the following, each scan line group runs to the kth enable signal ENBk. It is formed the lines. Since the area scanning can be realized by using these scanning line groups, the area scanning can be performed by the second display method in which the scanning lines are selected line by line.

"Driving method"
FIG. 7 is an example of a timing chart in the second display method, specifically, a timing chart when a two-dimensional image is displayed by forward shift. FIG. 8 is an example of a timing chart when switching from the first drive method to the second drive method in the first display method. Specifically, the line pair image is displayed after the line pair image is displayed by forward shift. It is a timing chart at the time of displaying. FIG. 9 is an example of a timing chart when switching from the second drive method to the first drive method in the first display method. Specifically, the line pair image is displayed after the shifted line pair image is displayed by forward shift. It is a timing chart at the time of displaying. Next, a driving method of the scanning line driving circuit 52 configured as described above will be described.

  First, region scanning will be described with reference to FIG. In the shift register circuit 55 that performs forward shift, the Y start pulse signal DY is sequentially transferred from the first stage output SR1 to the final m-th stage output SRm. At this time, since the Y start pulse signal DY is transferred to the output of the next stage every half cycle of the Y clock CKY, in this specification, the half cycle of the Y clock CKY is called one clock period (1CK). . In the driving method shown in FIG. 7, the active signal that appears at the first stage output SR1 in the third clock period CK3 (in this embodiment, the high potential signal H corresponds to logic 1 and is referred to as the first active signal A1). Appears in the second stage output SR2 in the fourth clock period CK4, appears in the third stage output SR3 in the fifth clock period CK5, and is sequentially transferred thereafter, and the (m + 2) th clock (not shown). It appears in the m-th stage output SRm of the final stage in the period CK (m + 2).

  In a normal driving method, the next image is formed after one active signal is output from the final m-th stage output SRm (in the above example, for example, in the (m + 3) -th clock period CK (m + 3)). Active signal appears at the first stage output SR1. Therefore, at a certain moment, the output from the shift register circuit 55 is in an active state where only one stage of output is active.

  On the other hand, in the area scanning, an active signal is introduced to the first stage output SR1 and sequentially transferred. Before the active signal leaves the final m-th stage output SRm, the next active signal is output. Is a driving method that appears in the first stage output SR1. Therefore, in the area scanning, at a certain moment, the output from the shift register circuit 55 may be in an active state with a plurality of stages of outputs. In other words, it is region scanning that a plurality of active signals may be simultaneously transferred in the shift register circuit 55. Actually, in FIG. 7, the first active signal A1 appears at the fifth stage output SR5, and the next active signal (second active signal A2) appears at the first stage output SR1 during the seventh clock period CK7. . Therefore, in the seventh clock period CK7, the eighth clock period CK8, the ninth clock period CK9, and the like, the two stages are in the active state at the output of the shift register circuit 55, and the first active signal A1 And the second active signal A2 are moving in the shift register circuit 55 at the same time. A part of an image formed by using one active signal and an enable signal is called a subfield. Therefore, when region scanning is used, one frame image is composed of a plurality of subfields.

  Since the output from the logic circuit to the scanning line 22 is a logical product of the shift output signal from the shift register circuit 55 and the enable signal from the common control circuit 54, a plurality of stages are active by the output of the shift register circuit 55 Even so, the scanning signal 22 is selected one by one using the enable signal. One clock period is divided into k, and an address is assigned to each division unit. At each address, only one enable signal of k enable signals is in an active state (corresponding to logic 1). In this embodiment, since k = 10, one clock period is divided into 10 and 1 to 10 addresses are assigned to each division unit. At the first address, the second enable signal ENB2 is active and the other enable signals are inactive (corresponding to logic 0). Only the third enable signal ENB3 is in the active state at the second address, and only the first enable signal ENB1 is in the active state at the tenth address.

  By doing so, the scanning lines 22 are selected one by one. Specifically, in the case of the second display method, the logical product of the first type output signal and the first type control signal is supplied to the first type scanning line, and the second type output signal is supplied to the second type scanning line. Since the logical product with the first type control signal is supplied, for example, the first scanning line G1 is selected at the 10th address of the third clock period CK3, and the pixel is connected to the first scanning line G1. In 21, the display corresponding to the first subfield SF1 is made. Similarly, the second scanning line G2 is selected at the tenth address in the fourth clock period CK4, and the pixel 21 connected to the second scanning line G2 displays a display corresponding to the first subfield SF1. The The third scanning line G3 is selected at the tenth address in the fifth clock period CK5, and the display corresponding to the first subfield SF1 is performed on the pixel 21 connected to the third scanning line G3. The fourth scanning line G4 is selected at the tenth address in the sixth clock period CK6, and the display corresponding to the first subfield SF1 is performed on the pixel 21 connected to the fourth scanning line G4. The first scanning line G1 is selected at the eighth address in the seventh clock period CK7, and the pixel 21 connected to the first scanning line G1 displays a display corresponding to the second subfield SF2 from here. . The fifth scanning line G5 is selected at the tenth address of the seventh clock period CK7, and the display corresponding to the first subfield SF1 is performed on the pixel 21 connected to the fifth scanning line G5. The same applies hereinafter. In this way, in the case of forward shift, each subfield forms a band-like region and moves from the top to the bottom of the display region 42, and is called region scanning. A subfield refers to one scanning line 22 (for example, the scanning line G1 in the first row) using a certain active signal (for example, the first active signal A1) from the shift register circuit 55. In this example, after the first scanning line G1) is selected, the next active signal (for example, the second active signal A2) is used to scan the scanning line 22 (in this example, the first scanning line G1). It can be said that it is a period until it is selected. In FIG. 7, only the first enable signal ENB1 describes an address number at which the first enable signal ENB1 becomes active.

  When area scanning is performed, digital driving and polarity inversion driving are possible. In the present embodiment, a digital signal (image high potential signal HV and image low potential signal LV) is used as the image signal Vij, the period of each subfield is appropriately weighted, and time-division gradation expression by the digital signal is performed. Is possible. Further, an analog signal (a signal having a potential corresponding to the gradation) is used as the image signal Vij, and polarity inversion driving can be performed in the odd-numbered subfield and the even-numbered subfield.

  FIG. 8 shows the first driving method (line pair scanning in the present embodiment) while performing area scanning by the first display method in forward shift, and then performing the second driving method (this embodiment) while performing area scanning. It is a timing chart explaining the drive method at the time of performing the display of a shift line pair scan in a form. In this embodiment, the shift register circuit 55 shifts the Y start pulse signal DY forward, so that the Y direction DIRY is the low potential signal L and the Y direction bar DIRYB is the high potential signal H (not shown in FIG. 8). In FIG. 8, the moment when the scanning line G1 in the first row is selected is t1, and t2 and t3 are sequentially set every one clock period (1CK). Further, since it is difficult to describe the timing charts of all the scanning lines 22 of 820 rows, the middle is omitted. Therefore, t11 corresponds to t811.

  A driving method in which one frame image is configured by using a plurality of subfields in a driving method adapted to area scanning, and a gray scale is expressed by time division is referred to as subfield driving. Although it is possible to perform time-division driving using subframes in the normal driving method without using area scanning, this method requires ultra-high speed driving. On the other hand, in subfield driving, an image with a high gradation frequency can be displayed using a digital signal at a practical clock cycle. In the present embodiment, one frame image is composed of 40 sets of field images, and each field image is composed of two subfields. Therefore, one frame image is composed of 80 subfields.

  As shown in FIG. 8, one subfield is formed by one line pair scan or one shifted line pair scan. One frame image is formed by performing the first line pair scanning LP Scan1 to the 80th line pair scanning LP Scan80. Thereafter, after the output prohibition period OPP, the next frame image is formed from the first shifted line pair scan SLP Scan1 to the 80th shifted line pair scan SLP Scan80 (not shown). In the first frame image, the Y start pulse signal DY for generating a scanning signal in a selected state for performing the q-th line pair scanning LP Scanq (q is an integer from 1 to 80) is shown in FIG. 8 as 1 FSPq. It is. Similarly, in FIG. 8, the Y start pulse signal DY that generates a scanning signal in a selected state for performing the q-th shifted line pair scanning SLP Scanq (q is an integer from 1 to 80) in the second frame image is represented by 2FSPq. As described.

  In the first frame image, subfield driving is performed by line pair scanning. At this time, the mode signal MODE becomes the low potential signal L and the mode bar signal MODEB becomes the high potential signal H. In one set of fields, the Y start pulse signal DY is input twice. For example, the first set of field images includes a subfield based on the first line pair scanning LP Scan1 and a subfield based on the second line pair scanning LP Scan2. The first line pair scan LP Scan1 is formed using the first Y start pulse signal 1FSP1 of the first frame, and the second line pair scan LP Scan2 uses the second Y start pulse signal 1FSP2 of the first frame. Formed.

  The active period of the Y start pulse signal DY (period in which one Y start pulse signal DY is active) is 3 clock periods in the active period of the shift output signal (period in which one shift output signal is active) It is preferable to set so as to be (3CK). Since the shift output signal advances by one stage every clock period (1CK), the active period of the shift output signal at the adjacent output in the shift register circuit 55 overlaps by two clock periods (2CK). The reason why the active period of the shift output signal is 3 clock periods (3CK) is that, in order to create a scanning signal in the selected state, the 1st clock period, 2nd clock period, 3rd clock period of the active period of the shift output signal This is because the enable signal and the logical product must be obtained in each of the above. For example, in the active period of the shift output signal corresponding to the first Y start pulse signal 1FSP1 of the first frame of the first stage output SR1, the first enable signal ENB1 and the logic are output in the second clock period (period t1-t2). The product is taken, and the scanning line G1 in the first row is selected in the first line pair scanning LP Scan1. Further, in the active period of the shift output signal corresponding to the first Y start pulse signal 1FSP1 of the first frame of the second stage output SR2, the first enable signal ENB1 and the logic level in the first clock period (period t1-t2). The product is taken, and the scanning line G2 in the second row is selected in the first line pair scanning LP Scan1. Further, in the active period of the shift output signal corresponding to the second Y start pulse signal 1FSP2 of the first frame of the first stage output SR1, the first enable signal ENB1 and the logic are output in the third clock period (period t10-t11). The product is taken, and the scanning line G1 in the first row is selected in the second line pair scanning LP Scan2. As described above, the active period of the shift output signal is preferably three clock periods (3CK), but is not limited thereto. If three independent scanning signals in the active state can be created by the logical product of the shift output signal in the active state and the enable signal in the active state, for example, even if the active period of the shift output signal is 5 clock periods (5CK) good. In the present embodiment, the active period of the shift output signal is set to the shortest three clock periods (3CK) in order to ensure the maximum degree of freedom of the enable signal input timing (that is, the degree of freedom of weighting of the subfield period). Yes.

  The active period of the enable signal (the period in which one enable signal is active) is preferably one clock period (1CK). After one enable signal becomes active, the next enable signal becomes active with a delay of two clock periods (2CK). For example, the second enable signal ENB2 becomes active with a delay of two clock periods (2CK) (t3 in this example) at the instant (t1) when the first enable signal ENB1 becomes active. Further, the first enable signal ENB1 becomes active with a delay of two clock periods (2CK) at the moment when the tenth enable signal ENB10 becomes active. Therefore, the period of the enable signal during the period for forming one field image is a clock period twice the number k of enable signals, that is, (2k) clock period (2kCK).

  In order to correspond to the odd and even subfields, the enable signal becomes active twice in the period of the enable signal. When an enable signal constituting a subfield becomes active in the r-th clock period CKr, the enable signal for constituting the next subfield is an (r + s) -th clock period CK after the s clock period (sCK). (R + s). Here, s is an odd number that satisfies SRA <s <(2k−SRA), and SRA is an active period of the shift output signal. In the present embodiment, as described above, since k = 10 and SRA = 3, s is selected from odd numbers from 5 to 15. Thus, the first subfield (for example, odd subfield) is formed using one half cycle of the Y clock CKY cycle (in this example, the half cycle in which the Y clock CKY is the high potential signal H). Then, the next second subfield (for example, even subfield) has the other half cycle of the Y clock CKY cycle (in this example, the half cycle in which the Y clock CKY is the low potential signal L). This is because the first subfield and the second subfield do not interfere with each other. In other words, by setting s to an odd number, the selection signal for the scanning line 22 for forming the first subfield and the selection signal for the scanning line 22 for forming the second subfield are simultaneously activated. You can avoid the situation. Further, by setting s to a value larger than SRA and smaller than (2k−SRA), the active period of the Y start pulse signal DY that creates the first subfield and the Y that creates the second subfield. The active period of the start pulse signal DY can be separated, and area scanning is realized. In the present embodiment, the enable signal constituting the next even subfield is activated after 9 clock periods (9 CK) behind the enable signal constituting the odd subfield. That is, s = 9. In response to this, the enable signal constituting the next odd subfield becomes active after 11 clock periods (11CK) of (2 k-s) from the enable signal constituting the even subfield. For example, in FIG. 8, corresponding to the first line pair scanning LP Scan1, the first enable signal ENB1 becomes active during the period from t1 to t2, and is delayed by 9 clock periods (9CK). In order to correspond to the scan LP Scan2, the first enable signal ENB1 is active again during the period from t10 to t11.

  In the first display method, the first drive method and the second drive method are alternately performed. In the first drive method, the first type output signal and the first type control signal are applied to the first type scan line. Is supplied, and the logical product of the second type output signal and the first type control signal is supplied to the second type scanning line, so that reference is made for each line pair as indicated by MODE = L in FIG. Enable signals to be determined are determined. Further, as described above, the active period of the shift output signal at the adjacent output in the shift register circuit 55 is overlapped by two clock periods (2CK). As a result, as shown in FIG. 8, the first scanning line G1, the second scanning line G2, the third scanning line G3, the fourth scanning line G4, and the fifth scanning line G5. And the scanning line G6 in the sixth row, and the scanning line 22 is selected. In this way, the first line pair scanning LP Scan1 is performed as the first subfield.

  Next, the second Y start pulse signal 1FSP2 of the first frame is input to the shift register circuit 55 to form the second subfield. In the present embodiment, the second Y start pulse signal 1FSP2 in the first frame is delayed from the first Y start pulse signal 1FSP1 in the first frame by 8 clock periods (8CK). Then, in the same manner as before, the first scanning line G1, the second scanning line G2, the third scanning line G3, the fourth scanning line G4, the fifth scanning line G5, and the sixth scanning line G6. The scanning line 22 becomes a selected state as a line pair such as the scanning line G6 of the eye. That is, the second line pair scanning LP Scan2 is realized as the second subfield. At this time, as described above, the enable signals (the first enable signal ENB1 to the tenth enable signal ENB10) are activated every 9 clock periods (9CK) or 11 clock periods (11CK), respectively. Therefore, the selection period of the scanning line 22 does not overlap between the first line pair scanning LP Scan1 and the second line pair scanning LP Scan2. Thus, area scanning by line pair scanning is established.

  The timing for starting the second line pair scanning LP Scan2 is set so that the area scanning is realized in accordance with the weighting ratio between the odd-numbered subfield and the even-numbered subfield. That is, the period from when the first Y start pulse signal 1FSP1 of the first frame is input to the shift register circuit 55 until the second Y start pulse signal 1FSP2 of the first frame is input to the shift register circuit 55 is Depending on the period of the first subfield and the period of the second subfield, the region scanning is set to be realized. As described above, in the present embodiment, the even-numbered Y start pulse signal (for example, 1FSP2) in the first frame is delayed by 8 clock periods (8CK) from the odd-numbered Y start pulse signal (for example, 1FSP1) immediately before it. This delay amount is not limited to this value. For example, it is possible to start the second Y start pulse signal 1FSP2 of the first frame at the timing indicated by the broken line in FIG. 8 (described as (1FSP2) in FIG. 8).

  In general, an interval between an enable signal for configuring a certain subfield (for example, the first subfield) and an enable signal for configuring the next subfield (in this example, the second subfield) is an s clock period. In the case of (sCK) (in this embodiment, as an example, s = 9), a Y start pulse signal for forming the first subfield (in this example, the first subfield) (in this example, the first Y The interval between the start pulse signal 1FSP1) and the Y start pulse signal (in this example, the second Y start pulse signal 1FSP2) for forming the next subfield (in this example, the second subfield) is (s -1 + 2 kr) clock period ((s-1 + 2 kr) CK). Here, k is the number of enable signals, and r is an integer of 0 or more. In the present embodiment, s = 9, k = 10, and r = 0. In the case of the second Y start pulse signal (1FSP2) indicated by the broken line in FIG. 8, r = 1. When this relationship is satisfied, area scanning is realized by line pair scanning.

  Thereafter, similarly up to the 80th line pair scanning LP Scan 80 is performed as the 80th subfield, and the area scanning by the first driving method is realized. After the 80th line pair scan LP Scan 80 is completed, the mode signal MODE and the mode bar signal MODEB are inverted so that the mode signal MODE is the high potential signal H and the mode bar signal MODEB is the low potential signal L. In this way, in the second drive method, the logical product of the first type output signal and the second type control signal is supplied to the first type scanning line, and the second type output signal and the second type control signal are supplied to the second type scanning line. Since a logical product with a kind of control signal is supplied, an enable signal to be referred to is determined for each shifted line pair, as indicated by MODE = H in FIG. As a result, a shifted line pair scan is possible.

  When inverting the mode signal MODE and the mode bar signal MODEB, it is desirable to provide an output inhibition period OPP for inhibiting the output of the enable signal as shown in FIG. That is, an output prohibition period OPP is provided between the first drive method and the second drive method, and in the output prohibition period, it is preferable that the first type control signal and the second type control signal correspond to logic 0. . That is, it is preferable that all enable signals are inactive during the output inhibition period. This is because malfunctions that may occur when the first drive method and the second drive method are switched can be avoided. When the first drive method and the second drive method are switched (when the mode signal MODE and the mode bar signal MODEB are inverted), the enable signal lines having different logic states are switched. Specifically, the connection destination of the second input of the first type AND circuit AND1 is exchanged between the first type control line and the second type control line. For this reason, if an output prohibition period is not provided, a through current is generated when the connection destination is replaced, causing a voltage drop of the power supply, and the electro-optical device may be unintentionally shut down. On the other hand, generation of an unnecessary through current can be suppressed by providing an output prohibition period. Therefore, by providing the output prohibition period, it is possible to avoid a situation where the electro-optical device is stopped due to a momentary large through current.

  When the output inhibition period is provided, weighting of the last even subfield (in this embodiment, the 80th line pair scan LP Scan80 in this embodiment) for forming one frame image (that is, the start of the 80th line pair scan LP Scan80). Depending on the position, there is a possibility that the output signal is disabled during the last even-numbered subfield while scanning the screen. In such a case, the 80th line pair scanning LP Scan 80 may be omitted.

  Usually, one frame image is composed of an even number of subfields. One frame image formed by the first driving method or the second driving method is composed of f field images (f is an integer of 2 or more, and in this embodiment, f = 40 as an example) Each field image is generally composed of an even number of subfields. Actually, in this embodiment, one field image is composed of two subfields. However, depending on the even-numbered final subfield weighting (final subfield period), the output prohibition period may start while the even-numbered final subfield scans the display area. In such a case, if the even-numbered final subfield is omitted and the preceding odd-numbered subfield is the actual final subfield, the odd-numbered final subfield is set in all scanning lines at the stage when the output prohibition period starts. Since the subfield is already written, the display corresponding to the result continues. In short, each of the f-1 field images from the first field image is composed of an even number of subfields, and the fth field image is composed of an odd number of subfields. In this way, display failure in the even-numbered final subfield that was originally scheduled is avoided, and good display can be realized. As shown in FIG. 10B, in the first display method, the 21st to 40th subfields and the 61st to 80th subfields are switched between the right eye video and the left eye video. Because of the black display. Therefore, since black is written in the 79th subfield, it can be used as black in the 80th subfield without any new writing operation.

  The output inhibition period is preferably k clock periods (kCK) or an integer multiple thereof. This is because the display signal can be easily controlled. It is also possible to set the output prohibition period only in the last subfield and not set the output prohibition period in the other subfields. To make it easier to control the display signal, It is preferable to provide an output prohibition period of the same period. In this embodiment, since one field image is composed of two subfields, and each subfield has an output prohibition period of k clock periods (kCK), 2 k clock periods are included in one field image. An odd subfield feedback period OSRP of (2 kCK) is provided. The odd-numbered subfield feedback period OSRP refers to the scanning of the odd-numbered subfields of the next field image (for example, the first line-pair scanning LP Scan1) after the scanning of the odd-numbered subfields of a certain field image (for example, the first line pair scanning LP Scan1). 3 is a period until the line pair scanning LP Scan3) of 3 is started. Actually, in FIG. 8, the first line pair scanning LP Scan1 ends at time t820, and after the odd subfield feedback period OSRP of 20 clock periods (20CK), the third line pair scanning LP Scan3 starts at time t841. Has been.

  After the mode signal MODE and the mode bar signal MODEB are inverted during the output inhibition period OPP, the second drive method is started to form the next frame image. The second frame image is formed by subfield driving by shifted line pair scanning. That is, one set of field images is composed of odd and even subfields by shifted line pair scanning. For example, the first set of field images includes a subfield based on the first shifted line pair scan SLP Scan1 and a subfield based on the second shifted line pair scan SLP Scan2. The first shifted line pair scan SLP Scan1 is formed using the first Y start pulse signal 2FSP1 of the second frame, and the second shifted line pair scan SLP Scan2 is the second Y start pulse signal 2FSP2 of the second frame. It is formed using.

  In order to perform shifted line pair scanning, a Y start pulse signal (in this example, the first Y start pulse signal 2FSP1) for forming the first subfield (in this example, the first subfield) and the next subfield are formed. The interval from the Y start pulse signal (in this example, the second Y start pulse signal 2FSP2) for constituting the field (in this example, the second subfield) is (s + 1 + 2 kr) clock period ((s + 1 + 2 kr) CK) And Here, k is the number of enable signals, and r is an integer of 0 or more. In this embodiment, s = 9, k = 10, and r = 0, and the interval between the first Y start pulse signal 2FSP1 and the second Y start pulse signal 2FSP2 is 10 clock periods (10CK). Yes. In this way, the interval between the odd-numbered Y start pulse signal DY and the subsequent even-numbered Y start pulse signal DY when performing area scanning by shifted line pair scanning is the odd number when performing area scanning by line pair scanning. The time is also increased by two clock periods (2CK) depending on the interval between the Y-th start pulse signal DY and the subsequent even-numbered Y start pulse signal DY.

  As a result, the enable signal referred to by the first-type AND circuit AND1 is changed as indicated by MODE = H in FIG. 6, so that the first scanning line G1, the second scanning line G2, and the third scanning line are changed. A shifted line pair such as a shifted line pair with the fourth scanning line G3, a shifted line pair with the fourth scanning line G4 and the fifth scanning line G5, and a scanning line G820 with the 820th line. Thus, the scanning line 22 is selected, and the first shifted line pair scanning SLP Scan1 becomes possible.

  The second Y start pulse signal 2FSP2 in the second frame image is input to the shift register circuit 55 with a delay of 10 clock periods (10CK) with respect to the first Y start pulse signal 2FSP1 in the second frame image. Then, similarly to the previous case, the first scanning line G1, the scanning line G2 of the second row, and the scanning line G3 of the third row are shifted line pairs, the scanning line G4 of the fourth row and the scanning of the fifth row The scan line 22 is selected as a shift line pair such as a shift line pair with the line G5, and the scan line G820 in the 820th row, and the second shift line pair scan SLP Scan2 becomes possible. Similar to line pair scanning, each enable signal is active every s clock periods (sCK) or (2k-s) clock periods ((2k-s) CK), so the first shifted line pair scanning SLP There is no overlap between the period in which the scanning line 22 is in the selected state in Scan1 and the period in which the scanning line 22 is in the selected state in the second shifted line pair scanning SLP Scan2. In this way, area scanning by shifted line pair scanning is established.

  FIG. 9 shows the first driving method (main book) while performing area scanning after displaying the second driving method (shifted line pair scanning in this embodiment) while performing area scanning by the first display method by forward shift. 6 is a timing chart illustrating a driving method when performing display of line pair scanning in the embodiment. In this embodiment, the shift register circuit 55 shifts the Y start pulse signal DY forward, so that the Y direction DIRY is the low potential signal L and the Y direction bar DIRYB is the high potential signal H (not shown in FIG. 9). In FIG. 9, the moment when the scanning line G1 in the first row is selected is t1, and t2 and t3 are sequentially set every clock period (1CK). Further, since it is difficult to describe the timing charts of all the scanning lines 22 of 820 rows, the middle is omitted. Therefore, t11 corresponds to t811.

  First, it is assumed that the mode signal MODE is the high potential signal H and the mode bar signal MODEB is the low potential signal L. In this way, in the second drive method, the logical product of the first type output signal and the second type control signal is supplied to the first type scanning line, and the second type output signal and the second type control signal are supplied to the second type scanning line. Since a logical product with a kind of control signal is supplied, an enable signal to be referred to is determined for each shifted line pair, as indicated by MODE = H in FIG. As a result, a shifted line pair scan is possible. In this state, the first Y start pulse signal 1FSP1 in the first frame image is introduced into the shift register circuit 55. Then, the first scanning line G1, the second scanning line G2 and the third scanning line G3 are shifted line pairs, the fourth scanning line G4 and the fifth scanning line G5 are shifted lines. The scanning line 22 is selected as a pair,... 820th scanning line G820, and the scanning line 22 is selected, and the first shifted line pair scanning SLP Scan1 becomes possible.

  The second Y start pulse signal 1FSP2 in the first frame image is input to the shift register circuit 55 with a delay of 10 clock periods (10CK) with respect to the first Y start pulse signal 1FSP1 in the first frame image. Then, similarly to the previous case, the first scanning line G1, the scanning line G2 of the second row, and the scanning line G3 of the third row are shifted line pairs, the scanning line G4 of the fourth row and the scanning of the fifth row The scan line 22 is selected as a shift line pair such as a shift line pair with the line G5, and the scan line G820 in the 820th row, and the second shift line pair scan SLP Scan2 is possible. Similarly, up to the 80th shifted line pair scanning SLP Scan 80 is performed.

  In general, an interval between an enable signal for forming a certain subfield (for example, the first subfield) and an enable signal for forming the next subfield (in this example, the second subfield) is s In the case of the clock period (sCK) (in this embodiment, s = 9 as an example), a Y start pulse signal (in this example, the first subfield) for forming the first subfield (in this example, the first subfield) The Y start pulse signal 1FSP1) and the Y start pulse signal (in this example, the second Y start pulse signal 1FSP2) for forming the next subfield (in this example, the second subfield) are The period is (s + 1 + 2 kr) clock periods ((s + 1 + 2 kr) CK). Here, k is the number of enable signals, and r is an integer of 0 or more. In this embodiment, s = 9, k = 10, and r = 0, and the interval between the first Y start pulse signal 1FSP1 and the second Y start pulse signal 1FSP2 is 10 clock periods (10CK). Yes. Not limited to this, the interval between the Y start pulse signal for forming the odd subfield and the Y start pulse signal for forming the next even subfield is set to (s + 1 + 2 kr) clock period ((s + 1 + 2 kr) CK). For example, the second Y start pulse signal (1FSP2) may be introduced at the timing indicated by the broken line in FIG. Incidentally, in this case, r = 1 is set. By satisfying this relationship, area scanning is realized by shifted line pair scanning.

  After the 80th shifted line pair scan SLP Scan 80 is performed, the second frame image is formed by using line pair scan after an output prohibition period. The second frame image forming method is the same as the line pair image forming method described above with reference to FIG.

"Display method"
10A and 10B are diagrams illustrating a display method. FIG. 10A illustrates a second display method, and FIG. 10B illustrates a first display method. Next, a high-definition two-dimensional image display method and a three-dimensional image display method will be described with reference to FIG.

  As shown in FIG. 10A, in order to digitally display a high-definition two-dimensional image by the second display method, one frame image is formed by four field images, and each field image has 10 Consists of subfields. Therefore, one frame image is composed of 40 subfields. In one subfield, each pixel 21 performs bright display or dark display digital display. Since each subfield constituting one field image has a different subfield period, it is possible to finely set a bright display period and a dark display period for each pixel 21 by 40 subfields. Thus, high gradation expression is realized in the high-definition display area 42.

  As shown in FIG. 10B, in order to digitally display a three-dimensional image by the first display method, the first drive method (line pair scan LP Scan) and the second drive method (shifted line pair scan SLP Scan). And are repeated alternately. One frame image formed by the first driving method or the second driving method is formed by 40 field images, and each field image has two subfields (that is, the first subfield and the second subfield). ). Therefore, one frame image is composed of 80 subfields. In the 40 field images, the weights of the first subfield and the second subfield are the same. That is, the periods of the 40 odd subfields constituting the 80 subfields are all the same, and the periods of the 40 even subfields constituting the 80 subfields are the same. In this way, the display signal can be easily controlled.

  Of the 40 field images constituting the first frame image, the first 10 field images (first subfield SF1 to 20th subfield SF20) are line pair images for the right eye. In the line pair image for the right eye, a bright display period and a dark display period are finely set for each pixel 21 using 20 subfields, thereby realizing time-division digital gradation expression. The next 10 field images (21st subfield SF21 to 40th subfield SF40) are dark display images, and the right eye shutter 12 and left eye shutter 14 of the stereoscopic glasses 10 are switched during this period. It is done. The next ten field images (41st subfield SF41 to 60th subfield SF60) are line pair images for the left eye. In the line pair image for the left eye, a bright display period and a dark display period are finely set for each pixel 21 using 20 subfields, thereby realizing time-division digital gradation expression. The next ten field images (the 61st subfield SF61 to the 80th subfield SF80) are dark display images, and during this period, the right eye shutter 12 and the left eye shutter 14 of the stereoscopic glasses 10 are turned on again. Can be switched.

  Of the 40 field images constituting the second frame image, the first 10 field images (first subfield SF1 to twentieth subfield SF20) are shifted line pair images for the right eye. In the shifted line pair image for the right eye, a bright display period and a dark display period are finely set for each pixel 21 using 20 subfields, thereby realizing time-division digital gradation expression. The next 10 field images (21st subfield SF21 to 40th subfield SF40) are dark display images, and the right eye shutter 12 and left eye shutter 14 of the stereoscopic glasses 10 are switched during this period. It is done. The next ten field images (41st subfield SF41 to 60th subfield SF60) are left-eye shifted line pair images. In the shifted line pair image for the left eye, a bright display period and a dark display period are finely set for each pixel 21 using 20 subfields, thereby realizing time-division digital gradation expression. The next ten field images (the 61st subfield SF61 to the 80th subfield SF80) are dark display images, and during this period, the right eye shutter 12 and the left eye shutter 14 of the stereoscopic glasses 10 are turned on again. Can be switched. Thereafter, the same cycle is repeated to realize a three-dimensional display.

  In the first display method, an odd-numbered frame image displays an odd-numbered image using line pair scanning, and an even-numbered frame image displays an even-numbered image using shifted line pair scanning.

  An odd-numbered image is formed using an image signal in an odd-numbered row from an original one-frame image (referred to as a full-frame image, in this embodiment, a WXGA image of 800 pixels long × 1280 pixels wide). It is an image. In other words, an image obtained by selecting an image displayed in an odd row from a full frame image is an odd image. In the present embodiment, since there are 800 pixels in the vertical direction of one full frame image, the image signal V1j in the first row of the full frame image, the image signal V3j in the third row of the full frame image, and the five rows of the full frame image. An odd-numbered image is formed using an image signal on the odd-numbered rows for 400 rows, such as the image signal V5j for the eyes. At that time, the same image signal is supplied to the pixels 21 connected to two adjacent scanning lines 22 as a line pair. For example, the image signal V1j of the first row of the full frame image is supplied to the pixels 21 connected to the scanning line G11 of the 11th row and the scanning line G12 of the 12th row, and the scanning line G13 of the 13th row and the 14th row The image signal V3j of the third row of the full frame image is supplied to the pixel 21 connected to the scanning line G14, and the same is applied to the scanning line G809 of the 809th row and the scanning line G810 of the 810th row. An image signal V779j in the 799th line of the full frame image is supplied to the pixel 21. Note that the display area 42 of the electro-optical device 20 includes an image area and an adjustment area. The image area is an area where an image is actually displayed, and adjustment areas for ten scanning lines 22 are provided above and below the image area. An image signal is supplied to the pixel 21 in the image area, and a black signal Black is supplied to the pixel 21 in the adjustment area. In the line pair scanning, the adjustment region includes the pixels 21 connected to the scanning lines 22 from the first scanning line G1 to the tenth scanning line G10, and the m-9th scanning line Gm-9 to the mth row. This is an area formed by the pixels 21 connected to the scanning line 22 up to the scanning line Gm of the eye, and the image area is a scanning line from the scanning line G11 of the 11th row to the scanning line Gm-10 of the m-10th row. 22 is an area formed by the pixel 21 connected to the line 22.

  An even-numbered image is an image formed by using even-numbered image signals from one original full frame image. In other words, an image obtained by selecting an image displayed in even rows from a full frame image is an even image. In the present embodiment, the even-numbered lines for 400 lines, such as the image signal V2j for the second line of the full frame image, the image signal V4j for the fourth line of the full frame image, and the image signal V6j for the sixth line of the full frame image. An even image is formed using the image signal of the eye. At that time, the same image signal is supplied to the pixels 21 connected to the two adjacent scanning lines 22 as a shift line pair. For example, the second row image signal V2j of the full frame image is supplied to the pixels 21 connected to the 12th row scanning line G12 and the 13th row scanning line G13, and the 14th row scanning line G14 and the 15th row. The image signal V4j of the fourth row of the full frame image is supplied to the pixel 21 connected to the scanning line G15, and the same is applied to the scanning line G810 of the 810th row and the scanning line G811 of the 811th row. The pixel 21 is supplied with the image signal V800j in the 800th row of the full frame image. At this time, the adjustment region includes the pixels 21 connected to the scanning lines 22 from the first scanning line G1 to the eleventh scanning line G11, and the m-8th scanning line Gm-8 to the mth row. And the pixel 21 connected to the scanning line 22 up to the scanning line Gm, and the image area is the scanning line 22 from the twelfth scanning line G12 to the m-9th scanning line Gm-9. This is a region formed by the pixel 21 connected to the. As before, the black signal Black is supplied to the pixel 21 in the adjustment area. Thus, since the even image is shifted downward by one scanning line with respect to the odd image, it becomes possible to accurately display a high-definition full frame image in a time division manner.

"Other electronic devices"
The electro-optical device 20 is driven by the above-described driving method. As an electronic apparatus incorporating the electro-optical device 20, in addition to the projector described with reference to FIG. Mobile phones, portable audio devices, personal computers, video camera monitors, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, video phones, POS terminals, digital still cameras, and the like.

(Embodiment 2)
"Form using the second group enable"
FIG. 11 is a circuit configuration diagram of a scanning line driving circuit according to the second embodiment. Next, the scanning line driving circuit 52 according to the second embodiment will be described with reference to FIG. In addition, about the component same as Embodiment 1, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

  The scanning line driving circuit 52 of the present embodiment shown in FIG. 11 uses the second group enable signal in addition to the first group enable signal, as compared with the scanning line driving circuit 52 of the first embodiment shown in FIG. Is different. Other configurations are almost the same as those of the first embodiment. In the scanning line driving circuit 52 (FIG. 4) of the first embodiment, k enable signal lines and the common control circuit 54 are used. On the other hand, in this embodiment, the common control circuit 54 is eliminated, and k enable signal lines are used instead.

  Also in this embodiment, the scanning line driving circuit is a circuit that can switch between the first display method and the second display method, and shifts the signal and outputs a shift output signal for each stage. A circuit, a logic circuit, and an enable signal line; The enable signal lines include a first group enable signal line and a second group enable signal line. The first group enable signal line is supplied with the first group enable signal 1GENB (α), and the first group first enable signal line from which the first group first enable signal 1GENB1 is supplied is supplied with the first group k enable signal. A group of k first group enable signal lines up to the first group kth enable signal line to which 1GENBk is supplied. Note that k is an integer of 1 or more, and α is an integer from 1 to k. The second group enable signal line is supplied with the second group enable signal 2GENB (β) and supplied with the second group first enable signal 2GENB1 to the second group k enable signal from the second group first enable signal line. This is a group of k second group enable signal lines up to the second group kth enable signal line to which 2GENBk is supplied. β is also an integer from 1 to k. The first group enable signal 1GENB (α) corresponds to the enable signal in the first embodiment.

  The logic circuit receives a shift output signal from the shift register circuit 55 and any one of the first group first enable signal to the second group k enable signal, and receives these signals, The circuit outputs a scanning signal to the corresponding scanning line.

  In order to supply an enable signal from the first group enable signal line and the second group enable signal line to the logic circuit, the first control output line CL1, the second control output line CL2, the third control output line CL3, the fourth The control output line CL4, (2k) th control output line CL (2k), and 2k control output lines are provided. Further, a first control output line CL1 is electrically connected to the first logic circuit, a second control output line CL2 is electrically connected to the second logic circuit, and a third logic circuit is connected to the first logic output line CL1. The third control output line CL3 is electrically connected, the fourth logic circuit is electrically connected to the fourth control output line CL4, and so on. Similarly, the (2k) th logic circuit is the (2k) th. The control output line CL (2k) is electrically connected. For this reason, the extending direction of 2k control output lines such as the first control output line CL1, the second control output line CL2, the third control output line CL3, the fourth control output line CL4, etc. is the first scanning line, etc. It intersects with the extending direction of the scanning line 22.

  In short, the first group enable signal 1GENB (α) is transmitted to the scanning line G (2α-1 + 2kp) of the (2α-1 + 2kp) row (p is an integer from 0 to m / (2k) -1). The group α-enable signal line is electrically connected to the (2α-1) th logic circuit corresponding to the (2α-1) th scan line (α is an integer from 1 to k). That is, the second type control output line electrically connects the second input of the second type AND circuit AND2 and the first group enable signal line. The second type control output lines are the first control output line CL1, the third control output line CL3, the (2k-1) th control output line CL (2k-1), and the control output lines in odd columns. Specifically, the first group first enable signal line is connected to the second input of the logic circuit (second-type AND circuit AND2) of the first scanning line 22 through the first control output line CL1, and the first group The second enable signal line is connected to the second input of the logic circuit (second-type AND circuit AND2) of the third scanning line 22 through the third control output line CL3, and so on. The signal line is connected to the second input of the logic circuit (second-type AND circuit AND2) of the (2k-1) th scanning line 22 through the (2k-1) control output line CL (2k-1).

  Similarly, the second group enable signal 2GENB (β) is transmitted to the scanning line G (2β + 2kp) in the (2β + 2kp) th row (p is an integer from 0 to m / (2k) −1). The β enable signal line is electrically connected to the (2β) logic circuit corresponding to the (2β) scan line (β is an integer from 1 to k). That is, the first type control output line electrically connects the second input of the first type AND circuit AND1 and the second group enable signal line. The first type control output lines are the second control output line CL2, the fourth control output line CL4, the (2k) th control output line CL (2k), and the control output lines in even columns. Specifically, the second group first enable signal line is connected to the second input of the logic circuit (first type AND circuit AND1) of the second scanning line 22 through the second control output line CL2, and the second group. The second enable signal line is connected to the second input of the logic circuit (first-type AND circuit AND1) of the fourth scanning line 22 through the fourth control output line CL4, and so on. The signal line is connected to the second input of the logic circuit (first-type AND circuit AND1) of the (2k) th scanning line 22 through the (2k) th control output line CL (2k).

  With the above-described configuration, it is possible to perform area scanning by both line pair scanning and shifted line pair scanning that enable high-speed display while narrowing the interval between adjacent scanning lines 22. Next, the driving method in the present embodiment will be described with reference to FIGS.

  FIG. 12 shows the first driving method (line pair scanning in this embodiment) while performing area scanning by the first display method in forward shift, and then the second driving method (this embodiment) while performing area scanning. It is a timing chart explaining the drive method at the time of performing the display of a shift line pair scan in a form. In this embodiment, the shift register circuit 55 shifts the Y start pulse signal DY forward, so that the Y direction DIRY is the low potential signal L and the Y direction bar DIRYB is the high potential signal H (not shown in FIG. 12).

  Also in the present embodiment, the first drive method and the second drive method are alternately performed in the first display method, and in the first drive method, the first group α enable signal 1GENB (α) and the second group. The α-th enable signal 2GENB (α) becomes equal. For example, as shown in FIG. 12, the first group first enable signal 1GENB1 and the second group first enable signal 2GENB1 are equal during line pair scanning.

  In the second driving method, the first group (α + 1) enable signal 1 GENB (α + 1) and the second group α enable signal 2 GENB (α) are equal. For example, as shown in FIG. 12, the first group second enable signal 1GENB2 and the second group first enable signal 2GENB1 are equal during the shifted line pair scanning. Since the first group enable signals are k, the first group (k + 1) enable signal 1GENB (k + 1) is the first group first enable signal 1GENB1.

  FIG. 13 shows the second drive method (shifted line pair scan in this embodiment) while performing area scanning by the first display method with forward shift, and then performing the first drive method (main book while performing region scanning). 6 is a timing chart illustrating a driving method when performing display of line pair scanning in the embodiment. In this embodiment, since the shift register circuit 55 shifts the Y start pulse signal DY forward, the Y direction DIRY is the low potential signal L and the Y direction bar DIRYB is the high potential signal H (not shown in FIG. 13). As shown in FIG. 13, the driving method for changing from shifted line pair scanning to line pair scanning is the same.

  In the present embodiment, unlike the first embodiment, switching between the mode signal MODE and the mode bar signal MODEB is not required, so that the output prohibition period OPP may not be provided.

  As described above, according to the present embodiment, since no special circuit is required between the shift register circuit 55 and the logic circuit, the interval between the adjacent scanning lines can be reduced. Therefore, when the scanning line driving circuit is applied to an electro-optical device, the electro-optical device having a high-resolution display area can perform both area scanning by line pair scanning that enables high-speed display and shifted line pair scanning. Can do.

  The present invention is not limited to the above-described embodiment, and various modifications and improvements can be added to the above-described embodiment. A modification will be described below.

(Modification 1)
"Reverse shift mode 1"
This modification corresponds to the first embodiment. FIG. 14 is a timing chart in the first modification, and is a timing chart when a shifted line pair image is displayed after a line pair image is displayed by reverse shift in the scanning line driving circuit described in detail in the first embodiment. is there. FIG. 15 is a timing chart in the first modification, and is a timing chart when a line pair image is displayed after a shifted line pair image is displayed by reverse scanning in the scanning line driving circuit described in detail in the first embodiment. is there. Next, a driving method of the scanning line driving circuit 52 in this modification will be described. In addition, about the component same as Embodiment 1, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

  In the first embodiment, the shift register circuit 55 has been described as an example of forward shift. On the other hand, the present modification is different in that the shift register circuit 55 is a reverse shift. Other configurations are almost the same as those of the first embodiment.

  In order to operate the scanning line driving circuit 52 by reverse shifting the shift register circuit 55, the Y direction DIRY is set to the high potential signal H, and the Y direction bar DIRYB (not shown) is set as shown in FIGS. The low potential signal L is used. In this way, the Y start pulse signal DY is transferred from the m-th stage output SRm (m = 820 in the present modification) toward the first stage output SR1, and the driving with the reverse shift is realized.

  Since the method of referencing the enable signal is not symmetric between the forward shift and the reverse shift, in order to drive the scanning line driving circuit 52 by the reverse shift, it is necessary to slightly change the enable signal in the forward shift. However, area scanning can be realized by line pair scanning and shifted line pair scanning. Hereinafter, this point will be described.

  As shown in FIG. 14, in order to display the shifted line pair image of the area scan after displaying the line pair image of the area scan by the reverse shift, the shifted line pair image is displayed after the line pair image is displayed by the forward shift. Compared to the display (FIG. 8), the timing at which the enable signal becomes active is changed. In this case, the reference is the first Y start pulse signal 1FSP1 of the first frame. In the case of reverse-shift line pair scanning, the same signal as the first enable signal ENB1 of the forward shift (FIG. 8) is used as the tenth enable signal ENB10 of the reverse shift (FIG. 14). The same signal as the 2 enable signal ENB2 is the ninth enable signal ENB9 of the reverse shift (FIG. 14), and the same signal as the third enable signal ENB3 of the forward shift (FIG. 8) is the eighth enable of the reverse shift (FIG. 14). The same signal as the fourth enable signal ENB4 of the forward shift (FIG. 8) is set as the signal ENB8, and the same signal as the fifth enable signal ENB5 of the forward shift (FIG. 8) is set as the seventh enable signal ENB7 of the reverse shift (FIG. 14). Is the sixth enable signal ENB6 of the reverse shift (FIG. 14), and the same signal as the sixth enable signal ENB6 of the forward shift (FIG. 8) The fifth enable signal ENB5 is the same signal as the seventh enable signal ENB7 of the forward shift (FIG. 8), the fourth enable signal ENB4 of the reverse shift (FIG. 14), and the eighth enable signal ENB8 of the forward shift (FIG. 8) The same signal is the third enable signal ENB3 for reverse shift (FIG. 14), and the same signal as the ninth enable signal ENB9 for forward shift (FIG. 8) is the second enable signal ENB2 for reverse shift (FIG. 14). The same signal as the tenth enable signal ENB10 of the shift (FIG. 8) is set as the first enable signal ENB1 of the reverse shift (FIG. 14). As a result, as shown in FIG. 14, area scanning is performed by line pair scanning with reverse shift.

  In order to display the shifted line pair image of the area scan by the reverse shift after the output prohibition period OPP, the active state is retracted for two clock periods (2CK) with respect to the first enable signal ENB1 of the forward shift (FIG. 8). This signal is the 10th enable signal ENB10 of the reverse shift (FIG. 14), and the signal obtained by reversing the active state by 2 clock periods (2CK) with respect to the second enable signal ENB2 of the forward shift (FIG. 8) is reverse shifted. The 9th enable signal ENB9 in FIG. 14 is used, and a signal obtained by reversing the active state for 2 clock periods (2CK) with respect to the third enable signal ENB3 in the forward shift (FIG. 8) is the reverse shift (FIG. 14). The 8 enable signal ENB8 is set to the active state for 2 clock periods (2CK) with respect to the 4th enable signal ENB4 of the forward shift (FIG. 8). The retired signal is a seventh enable signal ENB7 of reverse shift (FIG. 14), and a signal obtained by reversing the active state for two clock periods (2CK) with respect to the fifth enable signal ENB5 of forward shift (FIG. 8), A reverse shift (FIG. 14) is the sixth enable signal ENB6, and a signal obtained by reversing the active state for two clock periods (2CK) with respect to the forward enable (FIG. 8) sixth enable signal ENB6 is reverse shifted (FIG. 14). The fifth enable signal ENB5 of the forward shift (FIG. 8) and the 7th enable signal ENB7 of the forward shift (FIG. 8) is a signal obtained by reversing the active state for two clock periods (2CK). And a signal obtained by reversing the active state for two clock periods (2CK) with respect to the eighth enable signal ENB8 of the forward shift (FIG. 8), The third enable signal ENB3 of the shift (FIG. 14) is used, and the signal obtained by reversing the active state for two clock periods (2CK) with respect to the ninth enable signal ENB9 of the forward shift (FIG. 8) is the reverse shift (FIG. 14). The second enable signal ENB2 is a signal obtained by reversing the active state for two clock periods (2CK) with respect to the tenth enable signal ENB10 of the forward shift (FIG. 8), and the first enable signal ENB1 of the reverse shift (FIG. 14). To do. As a result, as shown in FIG. 14, region scanning is performed by reverse line shifting and line pair scanning.

  As shown in FIG. 15, in order to display the line pair image of the area scan after displaying the shifted line pair image by the reverse shift, the line pair image is displayed after the shifted line pair image is displayed by the forward shift. Compared to the display (FIG. 9), the timing at which the enable signal becomes active is changed. In this case, the reference is the first Y start pulse signal 1FSP1 of the first frame. In order to display a shifted line pair image for area scanning by reverse shift, a signal obtained by reversing the active state for two clock periods (2CK) with respect to the first enable signal ENB1 of forward shift (FIG. 9) is reverse shifted ( A signal obtained by reversing the active state for two clock periods (2CK) with respect to the second enable signal ENB2 of the forward shift (FIG. 9) is the tenth enable signal ENB10 of FIG. A signal obtained by reversing the active state of 2 clock periods (2CK) with respect to the third enable signal ENB3 of the forward shift (FIG. 9) as the enable signal ENB9 is referred to as the eighth enable signal ENB8 of the reverse shift (FIG. 15). The signal obtained by reversing the active state for two clock periods (2CK) with respect to the fourth enable signal ENB4 of the shift (FIG. 9) is reverse-shifted. A signal obtained by reversing the active state by 2 clock periods (2CK) with respect to the fifth enable signal ENB5 of the forward shift (FIG. 9) is used as the seventh enable signal ENB7 of FIG. A signal obtained by reversing the active state of 2 clock periods (2CK) with respect to the sixth enable signal ENB6 of the forward shift (FIG. 9) as the enable signal ENB6 is referred to as a fifth enable signal ENB5 of the reverse shift (FIG. 15). A signal obtained by reversing the active state for two clock periods (2CK) with respect to the seventh enable signal ENB7 of the shift (FIG. 9) is set as the fourth enable signal ENB4 of the reverse shift (FIG. 15), and the forward shift (FIG. 9). A signal obtained by reversing the active state for two clock periods (2CK) with respect to the eighth enable signal ENB8 is converted to a third shift signal of FIG. A signal obtained by reversing the active state of 2 clock periods (2CK) with respect to the 9th enable signal ENB9 of the forward shift (FIG. 9) as the enable signal ENB3 is referred to as the second enable signal ENB2 of the reverse shift (FIG. 15). A signal obtained by reversing the active state for two clock periods (2CK) with respect to the tenth enable signal ENB10 of the shift (FIG. 9) is referred to as a first enable signal ENB1 of the reverse shift (FIG. 15). As a result, as shown in FIG. 15, region scanning is performed by reverse line shifting and line pair scanning.

  In the case of reverse-shift line pair scanning after the output inhibition period OPP, the same signal as the first enable signal ENB1 of the forward shift (FIG. 9) is used as the tenth enable signal ENB10 of the reverse shift (FIG. 15). The same signal as the second enable signal ENB2 of the shift (FIG. 9) is the ninth enable signal ENB9 of the reverse shift (FIG. 15), and the same signal as the third enable signal ENB3 of the forward shift (FIG. 9) is the reverse shift ( 15) is the eighth enable signal ENB8, and the same signal as the fourth enable signal ENB4 of the forward shift (FIG. 9) is the seventh enable signal ENB7 of the reverse shift (FIG. 15). The same signal as the 5 enable signal ENB5 is set as the sixth enable signal ENB6 of the reverse shift (FIG. 15), and the same signal as the sixth enable signal ENB6 of the forward shift (FIG. 9). Is the fifth enable signal ENB5 of the reverse shift (FIG. 15), and the same signal as the seventh enable signal ENB7 of the forward shift (FIG. 9) is the fourth enable signal ENB4 of the reverse shift (FIG. 15). The same signal as the eighth enable signal ENB8 in FIG. 9) is the third enable signal ENB3 of the reverse shift (FIG. 15), and the same signal as the ninth enable signal ENB9 of the forward shift (FIG. 9) is reverse shifted (FIG. 15). ) Is the second enable signal ENB2, and the same signal as the tenth enable signal ENB10 of the forward shift (FIG. 9) is the first enable signal ENB1 of the reverse shift (FIG. 15). As a result, as shown in FIG. 15, area scanning is performed by line pair scanning with reverse shift.

(Modification 2)
"Reverse shift form 2"
This modification corresponds to the second embodiment. FIG. 16 is a timing chart in the second modification, and is a timing chart when a shifted line pair image is displayed after a line pair image is displayed by reverse shift in the scanning line driving circuit described in detail in the second embodiment. is there. FIG. 17 is a timing chart in the second modification, and is a timing chart when a line pair image is displayed after a shifted line pair image is displayed by reverse scanning in the scanning line driving circuit described in detail in the second embodiment. is there. Next, a driving method of the scanning line driving circuit 52 in this modification will be described. In addition, about the component same as Embodiment 2, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

  In the second embodiment, the shift register circuit 55 has been described as an example of forward shift. On the other hand, the present modification is different in that the shift register circuit 55 is a reverse shift. Other configurations are almost the same as those of the second embodiment.

  In order to operate the scanning line driving circuit 52 by reverse shifting the shift register circuit 55, the Y direction DIRY is set to the high potential signal H and the Y direction bar DIRYB (not shown) is set as shown in FIGS. The low potential signal L is used. In this way, the Y start pulse signal DY is transferred from the m-th stage output SRm (m = 820 in the present modification) toward the first stage output SR1, and the driving with the reverse shift is realized.

  Also in this modification, in the first driving method, the first group α-enable signal 1 GENB (α) and the second group α-enable signal 2 GENB (α) are equal. For example, as shown in FIG. 16, the first group tenth enable signal 1GENB10 and the second group tenth enable signal 2GENB10 are equal during line pair scanning.

  In the second driving method, the first group (α + 1) enable signal 1 GENB (α + 1) and the second group α enable signal 2 GENB (α) are equal. For example, as shown in FIG. 16, the first group tenth enable signal 1GENB10 and the second group ninth enable signal 2GENB9 are equal during the shifted line pair scanning.

  As shown in FIG. 17, the same applies to the case where the line pair image is displayed after the shifted line pair image is displayed.

(Modification 3)
"Forms with different scanning line types"
In the first and second embodiments, the first-type scanning lines are the even-numbered scanning lines 22 and the second-type scanning lines are the odd-numbered scanning lines 22, but the first-type scanning lines are the odd-numbered scanning lines 22. The second-type scanning lines may be the even-numbered scanning lines 22.

(Modification 4)
"Forms with different driving systems"
In the first and second embodiments, the first driving method is line pair scanning and the second driving method is shifted line pair scanning. However, the first driving method is shifted line pair scanning and the second driving method is line pair scanning. It is also good.

  AND1 ... first-type AND circuit, AND2 ... second-type AND circuit, Sw1 ... first switch, Sw2 ... second switch, Sw3 ... third switch, 10 ... stereoscopic glasses, 12 ... right eye shutter, 14 ... Left eye shutter, 20 ... electro-optical device, 21 ... pixel, 22 ... scan line, 23 ... signal line, 24 ... pixel transistor, 25 ... pixel electrode, 26 ... liquid crystal, 27 ... common electrode, 30 ... control device, 31 DESCRIPTION OF SYMBOLS ... Glasses control circuit, 32 ... Display signal supply circuit, 33 ... Memory circuit, 42 ... Display area, 50 ... Drive device, 51 ... Drive circuit, 52 ... Scan line drive circuit, 53 ... Signal line drive circuit, 54 ... Common Control circuit 55 ... Shift register circuit 201 ... First panel 202 ... Second panel 203 ... Third panel 1000 ... Projection display device 1100 ... Illumination optical system 1300 ... Projection optical system 1400 ... the projection surface.

Claims (10)

Shift the signal, output the first shift signal to the first output, output the second shift signal to the second output, output the third shift signal to the third output, A shift register circuit for outputting a fourth shift signal to the output;
A first enable signal line to which a first enable signal is supplied;
A second enable signal line to which a second enable signal is supplied;
A third enable signal line to which a third enable signal is supplied;
A first logic circuit for outputting a first scanning signal to the first scanning line;
A second logic circuit for outputting a second scanning signal to the second scanning line;
A third logic circuit for outputting a third scanning signal to the third scanning line;
A fourth logic circuit for outputting a fourth scanning signal to the fourth scanning line;
The first enable signal is input to the first logic circuit, the first enable signal or the second enable signal is input to a second logic circuit, and the second enable signal is input to the third logic circuit. A common control circuit that inputs and inputs the second enable signal or the third enable signal to a fourth logic circuit;
In the case of the first display method, the first drive method and the second drive method are alternately performed,
The common control circuit includes:
In the first driving method, a first logic circuit corresponding to a first scanning line and a second logic circuit corresponding to a second scanning line adjacent to the first scanning line in the shift direction are provided. The first enable signal is input, a third logic circuit corresponding to a third scanning line adjacent to the second scanning line in the shift direction, and a fourth logic circuit adjacent to the third scanning line in the shift direction. The second enable signal is input to a fourth logic circuit corresponding to the scanning line of
In the second drive method, the first enable signal is input to the first logic circuit, the second enable signal is input to the second logic circuit and the third logic circuit, and the fourth logic circuit The third enable signal is input to the logic circuit of
The scanning line driver circuit, wherein the common control circuit is disposed outside a region between the shift register and a region where the first logic circuit to the fourth logic circuit are disposed . A first control output line to which an output signal from the common control circuit is supplied, a second control output line, a third control output line, and a fourth control output line;
The first control output line is electrically connected to the first logic circuit;
The second control output line is electrically connected to the second logic circuit,
The third control output line is electrically connected to the third logic circuit,
The scanning line driving circuit according to claim 1, wherein the fourth control output line is electrically connected to the fourth logic circuit. The common control circuit is disposed outside a region where the shift register circuit and the logic circuit are disposed,
The extending directions of the first control output line, the second control output line, the third control output line, and the fourth control output line intersect with the extending direction of the first scanning line. 3. The scanning line driving circuit according to claim 1, wherein the scanning line driving circuit is characterized in that: A shift register circuit, a first type control line, a second type control line, a first switch, a second switch, a first type AND circuit, and a second type AND circuit,
The first type output of the shift register circuit is electrically connected to the first input of the first type AND circuit;
A second type output of the shift register circuit is electrically connected to a first input of the second type AND circuit;
The second input of the first type AND circuit is electrically connected to the first type control line via the first switch, or is electrically connected to the second type control line via the second switch. Connected to
The output of the first type AND circuit is electrically connected to the first type scan line,
A second input of the second-type AND circuit is electrically connected to the first-type control line;
A second output of the second-type AND circuit is electrically connected to the second-type scanning line;
The scanning line driving circuit according to claim 1, wherein the first switch and the second switch are disposed outside a region between the region where the shift register circuit and the first type AND circuit are disposed.   5. The scanning line according to claim 4, further comprising a first type control output line that electrically connects the second input of the first type AND circuit to the first switch and the second switch. Drive circuit.   6. The scanning line driving circuit according to claim 5, further comprising a second type control output line that electrically connects the second input of the second type AND circuit and the first type control line.   7. The scanning line driving circuit according to claim 6, wherein a third switch is provided between the second input of the second type AND circuit and the first type control line.   8. The scanning line driving circuit according to claim 7, wherein the third switch is in an ON state during a period in which the scanning line driving circuit is operating.   An electro-optical device comprising the scanning line driving circuit according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 9.

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