JP6239250B2 - 半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 239000012535 impurity Substances 0.000 claims description 224
- 239000000758 substrate Substances 0.000 claims description 154
- 229910052782 aluminium Inorganic materials 0.000 claims description 73
- 229910052757 nitrogen Inorganic materials 0.000 claims description 64
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 60
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 41
- 229910052796 boron Inorganic materials 0.000 claims description 23
- 229910052733 gallium Inorganic materials 0.000 claims description 21
- 229910052738 indium Inorganic materials 0.000 claims description 21
- 229910052698 phosphorus Inorganic materials 0.000 claims description 18
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 13
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 13
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 10
- 239000011574 phosphorus Substances 0.000 claims description 9
- 229910010271 silicon carbide Inorganic materials 0.000 description 296
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 231
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Description
本実施形態の半導体装置は、第1と第2の面を有し、p型不純物とn型不純物を含有し、p型不純物を元素A、n型不純物を元素Dとする場合に、元素Aと元素Dとの組み合わせが、Al(アルミニウム)、Ga(ガリウム)またはIn(インジウム)とN(窒素)、B(ボロン)とP(リン)の少なくとも一方の組み合わせであり、組み合わせを構成する元素Aの濃度の元素Dの濃度に対する比が0.40より大きく0.95より小さく、組み合わせを構成する元素Dの濃度が1×1018cm−3以上1×1022cm−3以下であるn型SiC基板と、第1の面上に設けられたSiC層と、第1の面側に設けられた第1の電極と、第2の面上に設けられた第2の電極と、を備える。
本実施形態の半導体装置は、ショットキーバリアダイオード(SBD)である。なお、p型不純物とn型不純物との共ドープによる作用等は、第1の実施形態と同様であるので、以下、記述を省略する。
本実施形態の半導体装置は、PiN/ショットキー混合ダイオード(MPS:Merged Pin Schottky diode)である。なお、p型不純物とn型不純物との共ドープによる作用等は、第1の実施形態と同様であるので、以下、記述を省略する。
本実施形態の半導体装置は、縦型のMOSFET(Metal Oxide Semiconductor Field Effect Transistor)である。なお、p型不純物とn型不純物との共ドープによる作用等は、第1の実施形態と同様であるので、以下、記述を省略する。
本実施形態の半導体装置は、第1と第2の面を有し、p型不純物とn型不純物を含有し、p型不純物を元素A、n型不純物を元素Dとする場合に、元素Aと元素Dとの組み合わせが、Al(アルミニウム)、Ga(ガリウム)またはIn(インジウム)とN(窒素)、B(ボロン)とP(リン)の少なくとも一方の組み合わせであり、組み合わせを構成する元素Dの濃度の元素Aの濃度に対する比が0.33より大きく1.0より小さく、組み合わせを構成する元素Aの濃度が1×1018cm−3以上1×1022cm−3以下であるp型SiC基板と、第1の面上に設けられたSiC層と、第1の面側に設けられた第1の電極と、第2の面上に設けられた第2の電極と、を備える。
本実施形態の半導体装置は、縦型のJFET(Junction Field Effect Transistor)である。なお、p型不純物とn型不純物との共ドープによる作用等は、第1の実施形態と同様であるので、以下、記述を省略する。
14 SiC層
24 第1の電極(ソース電極)
36 第2の電極(ドレイン電極)
44 第1の電極(アノード電極)
46 第2の電極(カソード電極)
52 p型SiC基板
100 PiNダイオード
200 ショットキーバリアダイオード
300 PiN/ショットキー混合ダイオード
400 MOSFET
500 IGBT
600 JFET
Claims (8)
- 第1と第2の面を有し、p型不純物とn型不純物を含有し、前記p型不純物を元素A、前記n型不純物を元素Dとする場合に、前記元素Aと前記元素Dとの組み合わせが、Al(アルミニウム)、Ga(ガリウム)またはIn(インジウム)とN(窒素)、B(ボロン)とP(リン)の少なくとも一方の組み合わせであり、前記組み合わせを構成する前記元素Aの濃度の前記元素Dの濃度に対する比が0.40より大きく0.95より小さく、前記組み合わせを構成する前記元素Dの濃度が1×1018cm−3以上1×1022cm−3以下であるn型SiC基板と、
前記第1の面上に設けられたSiC層と、
前記第1の面側に設けられた第1の電極と、
前記第2の面上に設けられた第2の電極と、を備える半導体装置。 - 前記元素Aの濃度の前記元素Dの濃度に対する比が、0.45以上0.75以下である請求項1記載の半導体装置。
- 前記元素Dの濃度が1×1019cm−3以上である請求項1または請求項2記載の半導体装置。
- 前記元素Dと前記元素Aの3量体のドナー準位が40meV以下である請求項1ないし請求項3いずれか一項記載の半導体装置。
- 前記元素Aの90%以上が前記元素Dの最近接の格子位置にある請求項1ないし請求項4いずれか一項記載の半導体装置。
- 第1と第2の面を有し、p型不純物とn型不純物を含有し、前記p型不純物を元素A、前記n型不純物を元素Dとする場合に、前記元素Aと前記元素Dとの組み合わせが、Al(アルミニウム)、Ga(ガリウム)またはIn(インジウム)とN(窒素)、B(ボロン)とP(リン)の少なくとも一方の組み合わせであり、前記組み合わせを構成する前記元素Aの濃度の前記元素Dの濃度に対する比が0.40より大きく0.95より小さく、前記組み合わせを構成する前記元素Dの濃度が1×1018cm−3以上1×1022cm−3以下であるn型SiC基板を準備し、
前記第1の面上にSiC層を形成し、
前記第1の面側に第1の電極を形成し、
前記第2の面上に第2の電極を形成する半導体装置の製造方法。 - 前記元素Aの濃度の前記元素Dの濃度に対する比が、0.45以上0.75以下である請求項6記載の半導体装置の製造方法。
- 前記元素Dの濃度が1×1019cm−3以上である請求項6または請求項7記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2013059831A JP6239250B2 (ja) | 2013-03-22 | 2013-03-22 | 半導体装置およびその製造方法 |
CN201410076369.0A CN104064586B (zh) | 2013-03-22 | 2014-03-04 | 半导体装置及其制造方法 |
US14/205,964 US9171908B2 (en) | 2013-03-22 | 2014-03-12 | SiC semiconductor device and method of manufacturing the same |
US14/855,669 US9412823B2 (en) | 2013-03-22 | 2015-09-16 | Semiconductor device and method of manufacturing the same |
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JP2013059831A JP6239250B2 (ja) | 2013-03-22 | 2013-03-22 | 半導体装置およびその製造方法 |
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JP2017164181A Division JP6400809B2 (ja) | 2017-08-29 | 2017-08-29 | 半導体装置 |
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JP2014187114A JP2014187114A (ja) | 2014-10-02 |
JP6239250B2 true JP6239250B2 (ja) | 2017-11-29 |
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US (2) | US9171908B2 (ja) |
JP (1) | JP6239250B2 (ja) |
CN (1) | CN104064586B (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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US9711660B2 (en) * | 2014-03-13 | 2017-07-18 | Infineon Technologies Ag | JFET and method of manufacturing thereof |
JP6478884B2 (ja) * | 2015-09-11 | 2019-03-06 | 株式会社東芝 | 半導体装置 |
JP6624868B2 (ja) * | 2015-09-29 | 2019-12-25 | 昭和電工株式会社 | p型低抵抗率炭化珪素単結晶基板 |
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