JP6009408B2 - Electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  A liquid crystal device which is an example of this type of electro-optical device is often used as, for example, a light modulation means (light valve) of a projection display device. In particular, in the case of a projection display device, strong light from a light source is incident on a liquid crystal light valve, and this thin film transistor (TFT: Thin Film Transistor) in the liquid crystal light valve does not cause an increase in leakage current or malfunction. As described above, a light shielding film as a light shielding means for blocking incident light is built in the liquid crystal light valve. More specifically, in order to drive the pixel electrode for each pixel, such a light shielding film has a data line and a scanning line that are wired in the display region so as to intersect vertically and horizontally, and further, the scanning line and the data for each pixel. It is formed by at least a part of a conductive film constituting various electronic elements including TFTs electrically connected to a line, or in addition to or instead of this, as a light shielding means that simply blocks incident light. In order to play only the role, it may be formed as a lattice or stripe pattern corresponding to the planar pattern shape of the data lines and the scanning lines.

  A contact hole for electrically connecting the TFT and the pixel electrode is formed in the region where the light shielding film is formed on the substrate, that is, the non-opening region where light is not transmitted on the substrate. Also, holes are opened in an interlayer insulating film that insulates various wirings formed on the lower layer side and electronic elements such as TFTs (see, for example, Patent Document 1).

JP 2004-198849 A

  However, in order to increase the definition of the electro-optical device or the pixel pitch in order to meet the general demand for high-quality display images, and in order to increase the pixel aperture ratio to display bright images. In addition, when the width of the light shielding film provided between the pixels adjacent to each other is simply narrowed, the light is likely to enter the TFT, that is, the light shielding property to the TFT may be deteriorated. There is a problem. Further, when the width of such a light-shielding film is simply reduced, there is a technical problem that it is difficult to secure a space for providing a contact hole in a non-opening region in terms of manufacturing process or design. .

  The present invention has been made in view of the above-described problems, for example. The electro-optical device capable of improving the aperture ratio while improving the light-shielding property to the transistor and displaying a bright and high-quality image, and the electro-optical device. An object is to provide an electronic device including the device.

In order to solve the above problems, an electro-optical device according to an aspect of the invention includes a data line extending in the first direction, a transistor electrically connected to the data line, and a pixel electrode provided corresponding to the transistor. A light shielding portion provided to overlap the semiconductor layer of the transistor, a first relay layer electrically connected to the semiconductor layer of the transistor, the first relay layer, and the pixel electrode electrically A second relay layer to be connected, and the light shielding portion includes a first light shielding portion extending in the first direction, a second light shielding portion extending in a second direction intersecting the first direction, A third light-shielding portion extending from each of the first and second light-shielding portions and projecting to the corner of the pixel opening region, and electrically connecting the first relay layer and the second relay layer. The first contact hole overlaps the second light shielding portion, and the second relay layer Second contact hole for electrically connecting the serial pixel electrode overlaps with the third light-blocking portion.
The first light shielding portion is provided so as to overlap the data line.
The first contact hole is provided between the data line and another data line adjacent to the data line.
The first and second relay layers are provided in layers between the semiconductor layer of the transistor and the pixel electrode, respectively.

  According to the electro-optical device of the present invention, it is possible to display an image by a so-called active matrix method in which the supply of an image signal from a data line to a pixel electrode is controlled.

  Here, the “opening region” according to the present invention is a region in the pixel that substantially emits display light, for example, a pixel electrode made of a transparent conductive material such as ITO (Indium Tin Oxide) is formed, This is a region through which light is transmitted, and is a region in which the gradation of outgoing light that has passed through an electro-optical material such as liquid crystal can be changed in accordance with a change in transmittance. In other words, the “opening region” is a light shielding body such as a wiring, a light shielding film, and various elements in which the light collected on the pixel does not transmit the light or the light transmittance is relatively smaller than that of the transparent electrode. It means the area except the non-opening area to be blocked. Here, the “non-opening region” means a region where light contributing to display is not transmitted, for example, a region where a non-transparent wiring or electrode or a light shielding body such as various elements is disposed in the pixel. To do. Further, the “aperture ratio” means the ratio of the opening area in the pixel size including the opening area and the non-opening area.

  A plurality of pixel electrodes are provided in a matrix, for example, in a region to be a display region on the substrate. In addition, the data line, the transistor, the first and second conductive films, and various other components for driving the pixel electrode are formed in the non-opening region.

  The semiconductor layer included in the transistor is formed, for example, in an intersection region corresponding to the intersection of the data line and the scanning line in the non-opening region.

  The first conductive film is formed below the pixel electrode and above the semiconductor layer. The second conductive film is formed on the upper layer side of the first conductive film via the interlayer insulating film. The first and second conductive films are electrically connected to each other through a contact hole opened in the interlayer insulating film. Note that the interlayer insulating film may be formed as a single-layer film composed of one layer, or may be formed as a multilayer film having a laminated structure of two or more layers.

  The light shielding portion is provided so as to cover the semiconductor layer of the transistor. That is, the light shielding portion is formed in a layer different from the semiconductor layer (that is, on the upper layer side or the lower layer side) so as to at least partially define the non-opening region. Further, the light shielding portion overlaps at least a part of the semiconductor layer when seen in plan on the substrate. In other words, the light shielding portion is formed so as to cover at least a part of the semiconductor layer from the upper layer side or the lower layer side. Therefore, incident light that enters the semiconductor layer vertically or obliquely from the upper layer side or return light that enters from the lower layer side can be basically blocked by the light shielding portion. The “return light” includes, for example, back surface reflection on a substrate, light emitted from another electro-optical device by a double-plate projector or the like, and penetrating through a composite optical system. Thereby, the light-shielding property with respect to a transistor can be improved, for example, the light leakage current in a transistor can be reduced.

  The light shielding portion is formed as a single layer film or a multilayer film containing a light shielding material. The light shielding portion may be formed as a data line, may be formed as a capacitor element electrically connected to the transistor, or may be formed as a scanning line.

  Particularly in the present invention, the light-shielding portion has a protruding portion that protrudes to the corner of the opening region. For example, in the intersecting region where the data line and the scanning line intersect, there is an overhanging portion that protrudes from the corner of the opening region toward the center of the opening region. In other words, when the rectangular opening area is taken as a reference, the overhanging portion protrudes from the corner of the opening area toward the center of the opening area so as to have a rectangular shape or a square shape at the four corners of the opening area. Therefore, the light incident on the semiconductor layer provided in the intersecting region can be effectively shielded by the protruding portion in the light shielding portion. That is, if the overhanging portion is formed on the upper layer side of the semiconductor layer, for example, compared with the case where such an overhanging portion does not exist, the semiconductor layer is perpendicular to the upper layer side of the semiconductor layer. Alternatively, obliquely incident light or irregularly reflected light and stray light based on the incident light can be more reliably shielded by the overhanging portion. For example, when the overhanging portion is formed below the semiconductor layer, the semiconductor layer On the other hand, return light that enters perpendicularly or obliquely from the lower layer side, diffuse reflection light based on this, stray light, and the like can be more reliably blocked by the projecting portion. That is, it is possible to enhance or enhance the light shielding property with respect to the semiconductor layer by the protruding portion. Thereby, for example, the light leakage current in the transistor can be more reliably reduced.

  Further, particularly in the present invention, the contact hole at least partially overlaps the overhanging portion when viewed in plan on the substrate. That is, a contact hole is formed in the interlayer insulating film at a position at least partially overlapping with the overhanging portion when viewed in plan on the substrate. Typically, in the non-opening region, the contact hole is disposed in a region where an overhang portion in the light shielding portion is formed (in other words, a light shielding region for improving the light shielding property for the transistor). Therefore, only for the arrangement of the contact holes, the width of the non-opening region extending along the data line or the region extending along the scanning line may be unnecessarily enlarged, or separately from the non-opening region. It is possible to prevent the portion from being unnecessarily enlarged, and to secure a larger size of the opening region in each pixel. That is, the aperture ratio can be improved.

  In addition, the contact hole is disposed so as to at least partially overlap the overhanging portion, so that the contact hole (that is, a part of the second conductive film formed in the contact hole or in the contact hole). Light incident on the semiconductor layer can be reduced by a conductive portion formed as a plug made of a light-shielding conductive material. That is, light incident obliquely on the semiconductor layer from the upper layer side can be blocked by the contact hole.

  As described above, according to the electro-optical device of the present invention, in each pixel, the aperture ratio can be improved while improving the light shielding property with respect to the transistor, and finally a bright and high-quality image can be displayed.

  In an aspect of the electro-optical device according to the aspect of the invention, the protruding portion is formed at each of the four corners of the opening region.

  According to this aspect, four overhang portions are provided around the semiconductor layer of the transistor. Therefore, the light incident on the semiconductor layer of the transistor can be more reliably shielded by the protruding portion. Furthermore, the contact hole can be easily arranged so as to at least partially overlap the overhanging portion.

  In another aspect of the electro-optical device of the present invention, the second conductive film includes a metal film and has a portion formed in the contact hole.

  According to this aspect, the light incident on the semiconductor layer of the transistor can be further reduced by the portion formed as a part of the second conductive film including the metal film in the contact hole.

  In another aspect of the electro-optical device according to the aspect of the invention, the light-shielding portion includes a lower capacitor electrode and an upper capacitor electrode that are sequentially stacked on the substrate from a lower layer side, and among the lower capacitor electrode and the upper capacitor electrode. One electrode is a capacitive element electrically connected to the pixel electrode.

  According to this aspect, in each pixel, the image signal supplied to the pixel electrode is supplied to one of the upper and lower capacitive electrodes of the capacitive element, whereby the potential of the pixel electrode is temporarily set to the capacitive element. It can be made to function as a holding capacity for holding. As a result, it is possible to improve the holding characteristics of holding the pixel electrode at a potential corresponding to the image signal in each pixel.

  Furthermore, in this aspect, it is possible to use the capacitive element as a light-shielding portion, and in comparison with the case where a separate light-shielding film is provided, in each pixel, various components such as data lines and scanning lines and transistors are provided. The configuration related to each arrangement can be further simplified.

  In the above-described aspect in which the light shielding portion is a capacitive element, the first conductive film extends from the one electrode and is electrically connected to the semiconductor layer, and the second conductive film is connected to the pixel. You may comprise so that it may be electrically connected with an electrode.

  In this case, each of the first and second conductive films functions as a relay layer that electrically connects the semiconductor layer of the transistor and the pixel electrode. Therefore, it is possible to avoid a situation in which the interlayer distance between the semiconductor layer of the transistor and the pixel electrode is long and it is difficult to connect the two with a single contact hole. Furthermore, since the first conductive film is extended from one electrode of the capacitive element, the laminated structure and the manufacturing process are hardly complicated.

  In the above-described aspect in which the light-shielding portion is a capacitive element, the light shielding portion is formed on an upper layer side than the capacitive element and the second conductive film, and is formed on the other electrode different from the one of the lower capacitive electrode and the upper capacitive electrode. An electrically connected capacitor line may be provided, the first conductive film may be formed as the other electrode, and the second conductive film may be electrically connected to the capacitor line. .

  In this case, the second conductive film functions as a relay layer that electrically relays the other electrode of the capacitor (in other words, the first conductive film) and the capacitor line. Therefore, it is possible to avoid a situation in which the interlayer distance between the other electrode of the capacitive element and the capacitive line is long and it is difficult to connect the two with a single contact hole.

  In the above-described aspect in which the light shielding portion is a capacitive element, the second conductive film is a capacitive line electrically connected to another electrode different from the one of the lower capacitive electrode and the upper capacitive electrode. The first conductive film formed may be configured to be electrically connected to the other electrode.

  In this case, the first conductive film functions as a relay layer that electrically relays the capacitor line (in other words, the second conductive film) and the other electrode of the capacitor. Therefore, it is possible to avoid a situation in which the interlayer distance between the capacitor line and the other electrode of the capacitor element is long and it is difficult to connect the two with a single contact hole.

  In the above-described aspect in which the light shielding portion is a capacitive element, the first conductive film is electrically connected to the semiconductor layer, and the second conductive film is extended from the one electrode, The pixel electrode may be electrically connected.

  In this case, each of the first and second conductive films functions as a relay layer that electrically connects the semiconductor layer of the transistor and the pixel electrode. Therefore, it is possible to avoid a situation in which the interlayer distance between the semiconductor layer of the transistor and the pixel electrode is long and it is difficult to connect the two with a single contact hole. Furthermore, since the second conductive film extends from one electrode of the capacitive element, the laminated structure and the manufacturing process are hardly complicated.

  In the aspect in which the light shielding portion is a capacitive element as described above, each of the upper capacitive electrode and the lower capacitive electrode may be formed of a metal film.

  In this case, the capacitive element has a so-called MIM (Metal-Insulator-Metal) structure in which a metal film-dielectric film (insulating film) -metal film is laminated. According to such a capacitive element, power consumption consumed by the pair of capacitive electrodes can be reduced in accordance with various signals supplied to the pair of upper and lower capacitive electrodes. In addition, compared with the case where any one of the pair of capacitor electrodes is formed of a semiconductor film, the conductivity of the one electrode can be increased and the function of the capacitor element as a storage capacitor can be further improved.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic apparatus of the present invention, since the electro-optical device of the present invention described above is provided, a projection display device, a television, a mobile phone, an electronic notebook, capable of performing bright and high-quality image display, Various electronic devices such as a word processor, a viewfinder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. In addition, as an electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, an electron emission device (Field Emission Display and Conduction Electron-Emitter Display), and a display device using these electrophoretic device and electron emission device are realized. Is also possible.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is the H-H 'sectional view taken on the line of FIG. 3 is an equivalent circuit diagram of a plurality of pixel units of the liquid crystal device according to the first embodiment. FIG. It is a top view of a plurality of pixel parts (lower layer part) in a 1st embodiment. It is a top view of a plurality of pixel parts (upper layer part) in a 1st embodiment. FIG. 6 is a cross-sectional view taken along line A-A ′ when FIG. 4 and FIG. 5 are overlapped. It is a top view which shows the overhang | projection part in 1st Embodiment. It is a top view of a plurality of pixel parts (lower layer part) in a 2nd embodiment. It is a top view of a plurality of pixel parts (upper layer part) in a 2nd embodiment. FIG. 10 is a B-B ′ cross-sectional view when FIGS. 8 and 9 are overlapped. It is a top view of a plurality of pixel parts (lower layer part) in a 3rd embodiment. It is a top view of a plurality of pixel parts (upper layer part) in a 3rd embodiment. FIG. 13 is a cross-sectional view taken along line C-C ′ when FIG. 11 and FIG. 12 are overlaid. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.
<First Embodiment>
The liquid crystal device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the overall configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line H-H ′ of FIG. 1.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. The TFT array substrate 10 is a transparent substrate such as a quartz substrate, a glass substrate, or a silicon substrate. The counter substrate 20 is also a transparent substrate like the TFT array substrate 10. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region positioned around the image display region 10a. Are bonded to each other.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The sampling circuit 7 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. The scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, a lead wiring 90 is formed for electrically connecting the external circuit connection terminal 102 to the data line driving circuit 101, the scanning line driving circuit 104, the vertical conduction terminal 106, and the like. .

  In FIG. 2, on the TFT array substrate 10, a laminated structure is formed in which wirings such as TFTs for pixel switching, scanning lines, and data lines are formed. In the image display area 10a, pixel electrodes 9a made of a transparent material such as ITO are provided in a matrix on the upper layer of wiring such as pixel switching TFTs, scanning lines, and data lines. On the pixel electrode 9a, an alignment film subjected to a predetermined alignment process such as a rubbing process is formed. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. The light shielding film 23 is formed of, for example, a light shielding metal film or the like, and is patterned, for example, in a lattice shape in the image display region 10a on the counter substrate 20. On the light shielding film 23, the counter electrode 21 made of a transparent material such as ITO is formed in a solid shape so as to face the plurality of pixel electrodes 9a. On the counter electrode 21, an alignment film subjected to a predetermined alignment process such as a rubbing process is formed. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  In the present embodiment, it is assumed that incident light incident on the liquid crystal layer 50 in the image display region 10a from the counter substrate 20 side is emitted as display light from the TFT array substrate 10 side.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, or the like may be formed.

  Next, an electrical configuration of the pixel portion of the liquid crystal device according to the present embodiment will be described with reference to FIG. FIG. 3 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming the image display area of the liquid crystal device according to this embodiment.

  In FIG. 3, a pixel electrode 9 a and a TFT 30 as an example of a “transistor” according to the present invention are formed in each of a plurality of pixels formed in a matrix form that constitutes the image display region 10 a. The TFT 30 is electrically connected to the pixel electrode 9a, and performs switching control of the pixel electrode 9a during operation of the liquid crystal device. The data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. Good.

  The scanning line 11 is electrically connected to the gate of the TFT 30, and the liquid crystal device according to this embodiment applies the scanning signals G1, G2,..., Gm to the scanning line 11 in this order at a predetermined timing. It is configured to apply line-sequentially. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the TFT 30 as a switching element for a certain period. It is written at a predetermined timing. A predetermined level of image signals S1, S2,..., Sn written to the liquid crystal constituting the liquid crystal layer 50 (see FIG. 2) via the pixel electrode 9a is between the counter electrodes formed on the counter substrate for a certain period. Retained.

  The liquid crystal constituting the liquid crystal layer 50 modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The transmittance for light is increased, and light having a contrast corresponding to an image signal is emitted from the liquid crystal device as a whole.

  In order to prevent the image signal held here from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode 21 (see FIG. 2). The storage capacitor 70 is a capacitive element that functions as a storage capacitor that temporarily holds the potential of each pixel electrode 9a in response to supply of an image signal. One electrode of the storage capacitor 70 is electrically connected to the drain of the TFT 30 in parallel with the pixel electrode 9a, and the other electrode is electrically connected to the capacitor line 300 having a fixed potential so as to have a constant potential. ing. According to the storage capacitor 70, the potential holding characteristic in the pixel electrode 9a is improved, and display characteristics such as contrast improvement and flicker reduction can be improved. As will be described later, the storage capacitor 70 also functions as a built-in light shielding film that blocks light incident on the TFT 30.

  Next, a specific configuration of the pixel portion that realizes the above-described operation will be described with reference to FIGS. 4 and 5 are plan views of a plurality of pixel portions in the present embodiment. 4 and 5 respectively show the lower layer portion (FIG. 4) and the upper layer portion (FIG. 5) in the laminated structure described later. FIG. 6 is a cross-sectional view taken along line A-A ′ when FIGS. 4 and 5 are overlapped. FIG. 7 is a plan view showing an overhang portion extending from a part of the scanning line.

  In FIG. 6, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing. In FIGS. 5 and 6, for convenience of explanation, illustration of a portion located above the pixel electrode 9 a is omitted.

  In FIG. 5, a plurality of pixel electrodes 9a are provided in a matrix on the TFT array substrate 10 (the outline is indicated by a dotted line).

  As shown in FIGS. 4 and 5, data lines 6a (that is, data lines 6a1 and 6a2) and scanning lines 11 are provided along the vertical and horizontal boundaries of the pixel electrode 9a, respectively. In other words, the scanning line 11 extends along the X direction, and the data line 6 a extends along the Y direction so as to intersect the scanning line 11. A TFT 30 (see FIG. 4) is provided in each of the intersecting regions where the scanning line 11 and the data line 6a intersect each other.

  The scanning line 11, the data line 6a, the storage capacitor 70, the relay layers 91 and 92, and the TFT 30 are planarly viewed on the TFT array substrate 10, and each pixel has an opening area corresponding to the pixel electrode 9a (that is, in each pixel). , A region where light that actually contributes to display is transmitted or reflected) is disposed in a non-opening region. That is, the scanning line 11, the storage capacitor 70, the data line 6a, the relay layers 91 and 92, and the TFT 30 are arranged not in the opening area of each pixel but in the non-opening area so as not to hinder display. . Note that the scanning line 11, the storage capacitor 70, and the data line 6a respectively define a part of the non-opening region.

  As shown in FIG. 6, on the TFT array substrate 10, various components such as a scanning line 11, a TFT 30, a storage capacitor 70, data lines 6a1 and 6a2, and a pixel electrode 9a are provided in a laminated structure. . This stacked structure includes, in order from the bottom, the first layer including the scanning line 11, the second layer including the TFT 30 having the gate electrode 3, the third layer including the storage capacitor 70, the fourth layer including the data line 6a1, etc. A fifth layer including the data lines 6a2 and the like, and a sixth layer (uppermost layer) including the pixel electrodes 9a and the like are included. Further, the base insulating film 12 is provided between the first layer and the second layer, the first interlayer insulating film 41 is provided between the second layer and the third layer, and the second interlayer insulating film 42 is provided between the third layer and the fourth layer. A third interlayer insulating film 43 is provided between the fourth layer and the fifth layer, and a fourth interlayer insulating film 44 is provided between the fifth layer and the sixth layer, so that the above-described elements are short-circuited. It is preventing. The various insulating films 12, 41, 42, 43 and 44 include, for example, a contact hole 81 for electrically connecting the data line side source / drain region 1d in the semiconductor layer 1a of the TFT 30 and the data line 6a. Is formed. Hereinafter, each of these elements will be described in order from the bottom. In the above-described laminated structure, the first layer to the first interlayer insulating film are illustrated in FIG. 4 as the lower layer portion, and the third layer to the sixth layer are illustrated in FIG. 5 as the upper layer portion. .

(Structure of the first layer-scanning line 11 etc.)
In FIG. 6, a scanning line 11 is provided as the first layer. The scanning line 11 is made of a light-shielding conductive material such as a refractory metal material such as W (tungsten), Ti (titanium), or TiN (titanium nitride). The scanning line 11 constitutes an example of the “light shielding part” according to the present invention.

  As shown in FIG. 4, the scanning lines 11 are patterned in a stripe shape along the X direction.

  As shown in FIG. 7 in addition to FIG. 4, when viewed in more detail, the scanning line 11 overlaps the main line portion 11x extending along the X direction and the data line 6a from the main line portion 11x along the Y direction. And an extending portion 11y extending in the direction. The extending portions 11y of the scanning lines 11 adjacent to each other are not connected to each other, and therefore, the scanning lines 11 are divided into individual ones. The scanning line 11 functions as a lower light-shielding film that shields the semiconductor layer 1a (especially the channel region 1a 'and its periphery) of the TFT 30 from return light that enters the device from the TFT array substrate 10 side.

  Here, in this embodiment, the overhang portion 11t is particularly provided. The overhanging portion 11t extends from the main line portion 11x and the extended portion 11y of the scanning line 11, and extends from the corner of the opening region to the center of the opening region at the intersection region where the scanning line 11 and the data line 6a intersect each other. It is formed to overhang. Therefore, compared with the case where the overhanging portion 11t does not exist, the return light incident on the semiconductor layer 1a of the TFT 30 is added to the main line portion 11x and the extended portion 11y as the lower light shielding film, and the overhanging portion 11t. It can be shielded effectively. Thereby, the light-shielding property with respect to TFT30 can be improved, for example, generation | occurrence | production of the light leakage current in TFT30 can be reduced more reliably.

  Further, particularly in the present embodiment, the overhanging portion 11t is formed at each of the four corners of the opening region of each pixel. In other words, four overhang portions 11t are provided around each semiconductor layer 1a provided in the intersecting region. Therefore, the return light incident on the semiconductor layer 1a can be more reliably shielded by the protruding portion 11t.

(Configuration of the second layer-TFT30 etc.)
In FIG. 6, a TFT 30 is provided as the second layer.

  As shown in FIGS. 4 and 6, the TFT 30 includes the semiconductor layer 1 a and the gate electrode 3.

  The semiconductor layer 1a is made of, for example, polysilicon, and has a channel region 1a ′ having a channel length along the Y direction, a data line side LDD region 1b, a pixel electrode side LDD region 1c, a data line side source / drain region 1d, and a pixel electrode. The side source / drain region 1e is formed. That is, the TFT 30 has an LDD structure.

  The data line side source / drain region 1d and the pixel electrode side source / drain region 1e are formed substantially in mirror symmetry along the Y direction with respect to the channel region 1a '. The data line side LDD region 1b is formed between the channel region 1a 'and the data line side source / drain region 1d. The pixel electrode side LDD region 1c is formed between the channel region 1a 'and the pixel electrode side source / drain region 1e. The data line side LDD region 1b, the pixel electrode side LDD region 1c, the data line side source / drain region 1d, and the pixel electrode side source / drain region 1e are formed by implanting impurities into the semiconductor layer 1a by an impurity implantation such as an ion implantation method. This is an impurity region. The data line side LDD region 1b and the pixel electrode side LDD region 1c are formed as low concentration impurity regions with less impurities than the data line side source / drain region 1d and the pixel electrode side source / drain region 1e, respectively. According to such an impurity region, when the TFT 30 is not in operation, the off-current that flows in the source region and the drain region can be reduced, and the decrease in the on-current and the increase in off-leakage current that can occur during the operation of the TFT 30 can be suppressed. The TFT 30 preferably has an LDD structure. However, the TFT 30 may have an offset structure in which no impurity implantation is performed in the data line side LDD region 1b and the pixel electrode side LDD region 1c. A self-alignment type in which the data line side source / drain region and the pixel electrode side source / drain region are formed by implanting the concentration may be used.

  The scanning line 11 and the semiconductor layer 1a are insulated by a base insulating film 12. In addition to the function of insulating the semiconductor layer 1a from the scanning line 11, the base insulating layer 12 is formed on the entire surface of the TFT array substrate 10 so that the surface of the TFT array substrate 10 becomes rough during polishing or remains after cleaning. For example, the pixel switching TFT 30 has a function of preventing deterioration of characteristics.

  As shown in FIGS. 4 and 6, the gate electrode 3 is disposed on the upper layer side of the semiconductor layer 1a via the gate insulating films 2a and 2b. That is, the TFT 30 is formed as a top gate type TFT. The gate electrode 3 is made of a light-shielding conductive material such as a refractory metal material such as W, Ti, or TiN. Note that the gate electrode 3 may be formed of, for example, conductive polysilicon.

  As shown in FIG. 4, the gate electrode 3 includes a main body portion 3 a that overlaps the channel region 1 a ′ of the TFT 30, and an extending portion 31 that extends from the main body portion 3 a along the Y direction. The gate electrode 3 is electrically connected to the scanning line 11 through a contact hole 82 opened through the gate insulating film 2 b and the base insulating film 12.

  One contact hole 82 is formed on each side of the semiconductor layer 1a as a wall-shaped light shielding body along the Y direction. Therefore, it is possible to block light incident on the semiconductor layer 1a obliquely from both sides. Therefore, the light shielding property for the TFT 30 can be improved, and for example, the light leakage current in the TFT 30 can be more reliably reduced.

  In the present embodiment, the gate electrodes 3 of the respective TFTs 30 are formed separately. However, for example, the gate electrodes 3 of the TFTs 30 corresponding to the same scanning line 11 (that is, the TFTs 30 adjacent to each other along the X direction). May be formed so as to be connected to each other. In other words, it may be formed as another scanning line including the gate electrode 3 of the TFT 30 corresponding to the same scanning line 11 and disposed in a layer opposite to the scanning line 11 with respect to the semiconductor layer 1a. In this case, the scanning line can be configured as a double wiring, and the scanning signal can be supplied to the gate electrode 3 more reliably.

(Structure of the third layer-storage capacity 70 etc.)
In FIG. 6, a storage capacitor 70 is provided as the third layer. The storage capacitor 70 is provided on the upper layer side of the TFT 30 via the first interlayer insulating film 41.

  The storage capacitor 70 is formed by arranging an upper capacitor electrode 300 a and a lower capacitor electrode 71 so as to face each other with a dielectric film 75 therebetween. The lower capacitor electrode 71, the dielectric film 75, and the upper capacitor electrode 300a are stacked in this order from the lower layer side. The lower capacitive electrode 71 is an example of a “first conductive film” according to the present invention, and the upper capacitive electrode 300a is an example of a “second conductive film” according to the present invention.

  As shown in FIGS. 5 and 6, the upper capacitor electrode 300 a is formed as a part of the capacitor line 300. The capacitance line 300 extends from the image display area 10a where the pixel electrode 9a is disposed to the periphery thereof. The upper capacitor electrode 300a is a fixed potential side capacitor electrode that is electrically connected to a constant potential source via the capacitor line 300 and maintained at a fixed potential. The upper capacitor electrode 300a is formed of a non-transparent metal film containing a metal or alloy such as Al (aluminum) or Ag (silver), for example, and also functions as an upper light shielding film (built-in light shielding film) that shields the TFT 30. To do. The upper capacitor electrode 300a is, for example, at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum), and Pd (palladium). May be composed of a single metal, an alloy, a metal silicide, a polysilicide, or a laminate of these.

  The lower capacitor electrode 71 is a pixel potential side capacitor electrode electrically connected to the pixel electrode side source / drain region 1e of the TFT 30 and the pixel electrode 9a. More specifically, the lower capacitor electrode 71 is electrically connected to the pixel electrode side source / drain region 1e through the contact hole 83 (see FIG. 4) and is opened in the second interlayer insulating film 42. The contact layer 84 is electrically connected to a relay layer 91 disposed in the same layer (that is, the fourth layer) as a data line 6a1 described later. Further, the relay layer 91 is electrically connected to the relay layer 92 disposed in the same layer (that is, the fifth layer) as a data line 6a2 described later through a contact hole 85 opened in the third interlayer insulating film 43. It is connected. Further, the relay layer 92 is electrically connected to the pixel electrode 9 a through a contact hole 86 opened in the fourth interlayer insulating film 44. That is, the lower capacitor electrode 71 relays the electrical connection between the pixel electrode side source / drain region 1e and the pixel electrode 9a together with the relay layers 91 and 92. The lower capacitor electrode 71 is made of conductive polysilicon. Therefore, the storage capacitor 70 has a so-called MIS structure. The lower capacitance electrode 71 has a function as a light absorption layer or a light shielding film disposed between the upper capacitance electrode 300a as the upper light shielding film and the TFT 30 in addition to the function as the pixel potential side capacitance electrode.

  The dielectric film 75 is made of, for example, a silicon oxide film such as an HTO (High Temperature Oxide) film, an LTO (Low Temperature Oxide) film, a silicon nitride film, or a metal oxide having an insulating property such as alumina or hafnia. It has a layer structure or a multilayer structure.

  The lower capacitor electrode 71 may be formed of a metal film in the same manner as the upper capacitor electrode 300a. That is, the storage capacitor 70 may be formed to have a so-called MIM structure having a three-layer structure of metal film-dielectric film (insulating film) -metal film.

  As shown in FIG. 5, the storage capacitor 70 has a protruding portion 70t that protrudes from the corner of the opening region toward the center of the opening region at the intersection region where the scanning line 11 and the data line 6a intersect each other. In other words, each of the upper capacitor electrode 300a and the lower capacitor electrode 71 functioning as the upper light-shielding film protrudes from the corner of the opening region toward the center of the opening region in the intersection region where the scanning line 11 and the data line 6a intersect each other. It is formed as follows. The overhanging portion 70t is formed so as to substantially overlap the overhanging portion 11t described above with reference to FIGS. 4 and 7 and to define a part of the non-opening region. Therefore, as compared with the case where the projecting portion 70t does not exist, the light incident on the semiconductor layer 1a of the TFT 30 from the upper layer side can be effectively shielded by the projecting portion 70t. Thereby, the light-shielding property with respect to TFT30 can be improved, and generation | occurrence | production of the light leakage current in TFT30 can be reduced more reliably.

(Structure of the fourth layer—data line 6a1, etc.)
In FIG. 6, the data line 6a1 is provided as the fourth layer. In the fourth layer, the relay layer 91 is formed of the same film as the data line 6a1. Here, the same film means that a thin film made of the same conductive material is simultaneously patterned.

  As shown in FIGS. 5 and 6, the data line 6a1 penetrates through the first interlayer insulating film 41, the second interlayer insulating film 42, and the gate insulating films 2a and 2b into the data line side source / drain region 1d of the semiconductor layer 1a. Is electrically connected through a contact hole 81 (see FIG. 4). The data line 6a1 and the inside of the contact hole 81 are made of, for example, an Al (aluminum) -containing material such as Al—Si—Cu or Al—Cu, Al alone, or a multilayer film including an Al layer and a TiN layer. The data line 6a1 also has a function of shielding the TFT 30 from light.

  The relay layer 91 is formed on the second interlayer insulating film 42 in the same layer as the data line 6a1. For the data line 6a1 and the relay layer 91, a thin film made of a conductive material such as a metal film is formed on the second interlayer insulating film 42 using a thin film forming method, and the thin film is partially removed. It forms in the state mutually spaced apart by patterning. Therefore, since the data line 6a1 and the relay layer 91 can be formed in the same process, the manufacturing process of the device can be simplified.

  Here, in the present embodiment, in particular, the contact hole 84 that electrically connects the lower capacitor electrode 71 and the relay layer 91 overlaps with the overhanging portions 11t and 70t when viewed in plan on the TFT array substrate 10. Is arranged. That is, a contact hole 84 is formed in the second interlayer insulating film 42 at a position overlapping with the overhanging portion 11t when viewed in plan on the TFT array substrate 10. Therefore, the contact hole 84 is disposed in the non-opening region in the region where the protruding portion 11t is formed as the light shielding region for improving the light shielding property with respect to the TFT 30. Accordingly, the width d1 of the region extending along the data line 6a or the width d2 of the region extending along the scanning line 11 in the non-opening region is unnecessarily enlarged only for the arrangement of the contact hole 84, Separately, it is possible to prevent a part of the non-opening area from being unnecessarily enlarged, and it is possible to secure a larger opening area size in each pixel. That is, the aperture ratio can be improved.

  In addition, the contact hole 84 is arranged so as to overlap the overhanging portion 11t, so that light incident obliquely from the upper layer side to the semiconductor layer 1a is transmitted through the contact hole 84 (that is, relayed). The light can be more reliably shielded by the portion of the layer 91 formed in the contact hole 84).

(Structure of the fifth layer—data line 6a2, etc.)
In FIG. 6, the data line 6a2 is provided as the fifth layer. In the fifth layer, the relay layer 92 is formed of the same film as the data line 6a2.

  As shown in FIG. 5, the data line 6a2 is formed so as to extend along the data line 6a1 (that is, along the Y direction), and a contact opened in the data line 6a1 and the third interlayer insulating film 43. It is electrically connected through a hole (not shown). That is, the data line 6a is configured as a double wiring composed of the data lines 6a1 and 6a2. The data line 6a2 is made of, for example, an Al-containing material such as Al—Si—Cu or Al—Cu, or a single Al substance, or a multilayer film including an Al layer and a TiN layer. The data line 6a2 also has a function of shielding the TFT 30 from light.

  The relay layer 92 is formed on the third interlayer insulating film 43 in the same layer as the data line 6a2.

  Note that the contact hole 85 that electrically connects the relay layer 91 and the relay layer 92, and the contact hole 84 that electrically connects the lower capacitor electrode 71 and the relay layer 91 are planar on the TFT array substrate 10. You may arrange | position so that it may mutually replace a position seeing. Also in this case, it is possible to prevent the non-opening area from being unnecessarily enlarged only for the arrangement of the contact holes 84 and 85.

  In the present embodiment, the fifth-layer wiring is configured as the second-layer data line 6a2. However, the fifth-layer wiring is configured as a shield layer between the data line 6a1 and the pixel electrode 9a by supplying a fixed potential. (In other words, a fixed potential line to which a fixed potential is supplied is formed in the fifth layer instead of the data line 6a2, and the fixed potential line is electromagnetically connected between the data line 6a1 and the pixel electrode 9a. It may function as an electromagnetic shielding film that reduces or prevents interference). Further, as in a second embodiment to be described later, a capacitive potential may be supplied and electrically connected to the upper capacitive electrode 300a. In this case, the capacitance line is configured as a double wiring.

(Structure of the sixth layer—pixel electrode 9a, etc.)
In FIG. 6, a pixel electrode 9a is provided as a sixth layer. The pixel electrode 9a is formed on the upper layer side of the data line 6a2 via the fourth interlayer insulating film 44.

  As shown in FIGS. 5 and 6, the pixel electrode 9a is connected to the pixel electrode side source / drain region 1e of the semiconductor layer 1a through the lower capacitor electrode 71, the contact holes 83, 84, 85 and 86, and the relay layers 91 and 92. Is electrically connected. An alignment film subjected to a predetermined alignment process such as a rubbing process is provided on the upper surface of the pixel electrode 9a.

  The configuration of the pixel portion described above is common to each pixel portion as shown in FIGS. Such pixel portions are periodically formed in the image display area 10a (see FIG. 1).

As described above, according to the liquid crystal device according to the present embodiment, it is possible to improve the aperture ratio while improving the light shielding property with respect to the TFT 30, and finally it is possible to display a bright and high-quality image.
Second Embodiment
Next, a liquid crystal device according to a second embodiment will be described with reference to FIGS. 8 and 9 are plan views of a plurality of pixel portions in the present embodiment. 8 and 9 respectively illustrate the lower layer portion (FIG. 8) and the upper layer portion (FIG. 9) in the laminated structure described later. FIG. 10 is a cross-sectional view taken along line BB ′ when FIGS. 8 and 9 are overlapped.

  In FIG. 10, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing. 9 and 10, for convenience of explanation, illustration of a portion located above the pixel electrode 9a is omitted.

  8 to 10, the same reference numerals are given to the same components as those according to the first embodiment shown in FIGS. 1 to 7, and description thereof will be omitted as appropriate.

  8 to 10, the liquid crystal device according to the second embodiment includes a data line 6b, a storage capacitor 70b, and a capacitor line instead of the data line 6a, the storage capacitor 70, and the capacitor line 300 in the first embodiment described above. Unlike the liquid crystal device according to the first embodiment described above, the other configuration is substantially the same as the liquid crystal device according to the first embodiment described above.

  As shown in FIGS. 8 and 9, data lines 6b and scanning lines 11 are provided along the vertical and horizontal boundaries of the pixel electrode 9a, respectively. A TFT 30 is provided in each of the intersecting regions where the scanning line 11 and the data line 6b intersect each other.

  The scanning line 11, the data line 6b, the storage capacitor 70b, the relay layers 91b, 92b and 93, and the TFT 30 are non-opening surrounding the opening region of each pixel corresponding to the pixel electrode 9a when viewed in plan on the TFT array substrate 10. Arranged in the area. Note that the scanning line 11, the storage capacitor 70b, and the data line 6b respectively define a part of the non-opening region.

  As shown in FIG. 10, on the TFT array substrate 10, various components such as a scanning line 11, a TFT 30, a storage capacitor 70b, a data line 6b, and a pixel electrode 9a are provided in a laminated structure. This stacked structure includes, in order from the bottom, a first layer including the scanning line 11, a second layer including the TFT 30 having the gate electrode 3, a third layer including the storage capacitor 70b, a fourth layer including the data line 6b, The fifth layer includes the capacitor line 320 and the like, and the sixth layer includes the pixel electrode 9a and the like. Hereinafter, each of these elements will be described in order from the bottom. In the above-described laminated structure, the first layer to the first interlayer insulating film 41 are illustrated in FIG. 8 as the lower layer portion, and the third to sixth layers are illustrated in FIG. 9 as the upper layer portion. Yes.

(Structure of the first layer-scanning line 11 etc.)
In FIG. 10, a scanning line 11 is provided as the first layer. The scanning line 11 is configured in the same manner as in the first embodiment described above, and extends so as to overlap the data line 6a along the Y direction from the main line portion 11x along the main line portion 11x extending along the X direction. And an extended portion 11y.

  In the present embodiment, an overhang portion 11t is provided as in the first embodiment described above. Therefore, the return light incident on the semiconductor layer 1a of the TFT 30 can be effectively shielded by the projecting portion 11t, compared to the case where the projecting portion 11t does not exist.

(Configuration of the second layer-TFT30 etc.)
In FIG. 10, a TFT 30 is provided as the second layer. The TFT 30 is configured in the same manner as in the first embodiment described above, and includes the semiconductor layer 1 a and the gate electrode 3.

(Structure of the third layer-storage capacity 70b etc.)
In FIG. 10, a storage capacitor 70b is provided as the third layer. The storage capacitor 70 b is provided on the upper layer side of the TFT 30 via the first interlayer insulating film 41.

  The storage capacitor 70 b is formed by disposing the upper capacitor electrode 300 b and the lower capacitor electrode 71 b so as to face each other with the dielectric film 75 interposed therebetween. The lower capacitor electrode 71b, the dielectric film 75, and the upper capacitor electrode 300b are stacked in this order from the lower layer side.

  As shown in FIGS. 9 and 10, the upper capacitor electrode 300b is formed in an island shape for each TFT 30 so as to cover the channel region 1a 'of the semiconductor layer 1a and its periphery. The upper capacitor electrode 300b is a fixed potential side capacitor electrode that is electrically connected to a constant potential power source via a capacitor line 320 to be described later and maintained at a fixed potential. More specifically, the upper capacitor electrode 300b is relayed in the same layer (that is, the fourth layer) as a data line 6b described later through a contact hole 87 formed in the second interlayer insulating film 42. It is electrically connected to the layer 93. Further, the relay layer 93 is electrically connected to the capacitor line 320 through a contact hole 88 opened in the third interlayer insulating film 43. That is, the relay layer 93 relays the electrical connection between the upper capacitor electrode 300b and the capacitor line 320. The upper capacitor electrode 300b is formed of a non-transparent metal film containing, for example, a metal such as Al or Ag, or an alloy, and also functions as an upper light shielding film that shields the TFT 30 from light. The upper capacitor electrode 300b and the relay layer 93 constitute an example of the “first conductive film” and the “second conductive film” according to the present invention, respectively, and the relay layer 93 and the capacitor line 320 each correspond to the present invention. An example of the “first conductive film” and the “second conductive film” is configured.

  The lower capacitor electrode 71b is a pixel potential side capacitor electrode electrically connected to the pixel electrode side source / drain region 1e of the TFT 30 and the pixel electrode 9a. More specifically, the lower capacitor electrode 71b is electrically connected to the pixel electrode side source / drain region 1e via the contact hole 83b, and via the contact hole 84b opened in the second interlayer insulating film 42. Thus, the data line 6b is electrically connected to the relay layer 91b disposed in the same layer (that is, the fourth layer). Further, the relay layer 91 b is electrically connected to the relay layer 92 b disposed in the same layer (that is, the fifth layer) as the capacitor line 320 through the contact hole 85 b opened in the third interlayer insulating film 43. ing. Further, the relay layer 92 b is electrically connected to the pixel electrode 9 a through a contact hole 86 b opened in the fourth interlayer insulating film 44. That is, the lower capacitor electrode 71b relays the electrical connection between the pixel electrode side source / drain region 1e and the pixel electrode 9a together with the relay layers 91b and 92b. The lower capacitor electrode 71 is made of conductive polysilicon. Therefore, the storage capacitor 70b has a so-called MIS structure.

  As shown in FIG. 9, in this embodiment, in particular, the storage capacitor 70b has an overhanging portion 70bt that protrudes from the corner of the opening region toward the center of the opening region in the intersection region where the scanning line 11 and the data line 6b intersect each other. have. In other words, each of the upper capacitor electrode 300b and the lower capacitor electrode 71b functioning as the upper light shielding film protrudes from the corner of the opening region toward the center of the opening region at the intersection region where the scanning line 11 and the data line 6b intersect each other. It is formed as follows. The overhang portion 70bt substantially overlaps the overhang portion 11t (see FIG. 8 or FIG. 7) and is formed so as to define a part of the non-opening region. Therefore, as compared with the case where the overhang portion 70bt does not exist, the light incident on the semiconductor layer 1a of the TFT 30 from the upper layer side can be effectively blocked by the overhang portion 70bt. Thereby, the light-shielding property with respect to TFT30 can be improved, for example, generation | occurrence | production of the light leakage current in TFT30 can be reduced more reliably.

  Further, particularly in the present embodiment, the overhang portions 70bt are formed at the four corners of the opening area of each pixel. In other words, four overhang portions 70bt are provided around each semiconductor layer 1a provided in the intersecting region. Therefore, the light incident on the semiconductor layer 1a from the upper layer side can be more reliably shielded by the protruding portion 70bt.

(Structure of the fourth layer-data line 6b etc.)
In FIG. 10, a data line 6b is provided as the fourth layer. In the fourth layer, relay layers 93 and 91b are respectively formed from the same film as the data line 6b.

  As shown in FIGS. 9 and 10, the data line 6b penetrates through the first interlayer insulating film 41, the second interlayer insulating film 42, and the gate insulating films 2a and 2b in the data line side source / drain region 1d of the semiconductor layer 1a. It is electrically connected through a contact hole 81b. The data line 6b and the inside of the contact hole 81b are made of, for example, an Al-containing material such as Al—Si—Cu or Al—Cu, Al alone, or a multilayer film including an Al layer and a TiN layer. The data line 6b also has a function of shielding the TFT 30 from light.

  The relay layers 91b and 93 are formed in the same layer as the data line 6b on the second interlayer insulating film 42, respectively.

  Here, in the present embodiment, in particular, the contact hole 87 that electrically connects the upper capacitor electrode 300b and the relay layer 93 overlaps the overhanging portions 11t and 70bt when viewed in plan on the TFT array substrate 10. Is arranged. That is, a contact hole 87 is opened in the second interlayer insulating film 42 at a position overlapping the projecting portions 11t and 70bt when viewed in plan on the TFT array substrate 10. Therefore, of the non-opening region defined by the data line 6b, the scanning line 11, and the storage capacitor 70b, a region where the overhang portions 11t and 70bt are formed as a light shielding region for more reliably reducing the light leakage current of the TFT 30. In addition, a contact hole 87 is arranged. Therefore, only for the arrangement of the contact hole 87, the width d1 of the region extending along the data line 6b or the width d2 of the region extending along the scanning line 11 in the non-opening region is unnecessarily enlarged, Separately, it is possible to prevent a part of the non-opening area from being unnecessarily enlarged, and it is possible to secure a larger opening area size in each pixel.

  In addition, the contact hole 87 is arranged so as to overlap the overhanging portions 11t and 70bt, so that light incident obliquely from the upper layer side to the semiconductor layer 1a is incident on the semiconductor layer 1a through the contact hole 87 (that is, The portion of the relay layer 93 formed in the contact hole 87 can more reliably shield light.

(Structure of the fifth layer—capacity line 320, etc.)
In FIG. 10, a capacitor line 320 is provided as the fifth layer. In the fifth layer, the relay layer 92 b is formed of the same film as the capacitor line 320.

  As shown in FIG. 9, the capacitor line 320 has a main line portion extending along the data line 6b (that is, along the Y direction) and an extending portion 320x extending from the main line portion along the X direction. doing. The capacitor line 320 is electrically connected to the relay layer 93 through the contact hole 88 in the extended portion 320x. The capacity line 320 is made of, for example, an Al-containing material such as Al—Si—Cu or Al—Cu, Al alone, or a multilayer film including an Al layer and a TiN layer. The capacitor line 320 also has a function of shielding the TFT 30 from light.

  Here, in the present embodiment, in particular, the contact hole 88 that electrically connects the capacitor line 320 and the relay layer 93 overlaps the protruding portions 11t and 70bt when viewed in plan on the TFT array substrate 10. Is arranged. That is, a contact hole 88 is opened in the third interlayer insulating film 43 at a position overlapping the projecting portions 11t and 70bt as viewed in plan on the TFT array substrate 10. Therefore, of the non-opening region defined by the data line 6b, the scanning line 11, and the storage capacitor 70b, a region where the overhang portions 11t and 70bt are formed as a light shielding region for more reliably reducing the light leakage current of the TFT 30. In addition, a contact hole 88 is disposed. Therefore, the width d1 of the region extending along the data line 6b or the width d2 of the region extending along the scanning line 11 in the non-opening region is unnecessarily enlarged only for the arrangement of the contact hole 88, Separately, it is possible to prevent a part of the non-opening area from being unnecessarily enlarged, and it is possible to secure a larger opening area size in each pixel.

  In addition, the contact hole 88 is arranged so as to overlap with the overhanging portions 11t and 70bt, so that light incident obliquely on the semiconductor layer 1a from the upper layer side can be caused by the contact hole 88 (that is, the contact hole 88). , The portion of the capacitor line 320 formed in the contact hole 88 can be shielded more reliably.

  The relay layer 92 b is formed on the third interlayer insulating film 43 in the same layer as the capacitor line 320.

(Structure of the sixth layer—pixel electrode 9a, etc.)
In FIG. 10, a pixel electrode 9a is provided as a sixth layer. The pixel electrode 9 a is formed on the upper layer side of the capacitor line 320 via the fourth interlayer insulating film 44.

  As shown in FIGS. 9 and 10, the pixel electrode 9a includes the lower capacitor electrode 71b, the contact holes 83b, 84b, 85b and 86b, and the relay layers 91b and 92b, and the pixel electrode side source / drain region 1e of the semiconductor layer 1a. Is electrically connected.

As described above, according to the liquid crystal device according to the present embodiment, the aperture ratio can be improved while improving the light shielding property with respect to the TFT 30, and finally a bright and high-quality image can be displayed.
<Third Embodiment>
Next, a liquid crystal device according to a third embodiment will be described with reference to FIGS. 11 and 12 are plan views of a plurality of pixel portions in the present embodiment. 11 and 12 respectively illustrate the lower layer portion (FIG. 11) and the upper layer portion (FIG. 12) in the laminated structure described later. 13 is a cross-sectional view taken along the line CC ′ when FIGS. 11 and 12 are overlapped.

  In FIG. 13, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing. In FIGS. 12 and 13, for convenience of explanation, illustration of a portion located above the pixel electrode 9 a is omitted.

  11 to 13, the same reference numerals are given to the same components as those according to the first embodiment shown in FIGS. 1 to 7, and description thereof will be omitted as appropriate.

  11 to 13, the liquid crystal device according to the third embodiment includes a TFT 30c, a data line 6c, and a storage capacitor 70c instead of the TFT 30, the data line 6a, and the storage capacitor 70 in the first embodiment described above. Thus, the liquid crystal device according to the first embodiment described above is different from the liquid crystal device according to the first embodiment in other respects and is configured in substantially the same manner as the liquid crystal device according to the first embodiment described above.

  As shown in FIG. 11, data lines 6c and scanning lines 11 are provided along the vertical and horizontal boundaries of the pixel electrode 9a. That is, the scanning line 11 extends along the X direction, and the data line 6 c extends along the Y direction so as to intersect the scanning line 11. A TFT 30c having a semiconductor layer 4a is provided in each of the intersecting regions where the scanning line 11 and the data line 6c intersect each other.

  As shown in FIGS. 11 and 12, the scanning line 11, the data line 6c, the storage capacitor 70c, the relay layer 94, and the TFT 30c are arranged on each TFT corresponding to the pixel electrode 9a when viewed in plan on the TFT array substrate 10. It arrange | positions in the non-opening area | region surrounding an opening area | region. The scanning line 11, the storage capacitor 70c, and the data line 6c each define a part of the non-opening region.

  As shown in FIG. 13, on the TFT array substrate 10, various components such as a scanning line 11, a TFT 30c, a storage capacitor 70c, a data line 6c, and a pixel electrode 9a are provided in a laminated structure. In this stacked structure, the first layer including the scanning line 11, the second layer including the TFT 30c having the gate electrode 3 and the like, the third layer including the data line 6c and the like, the fourth layer including the storage capacitor 70c and the like in order from the bottom And a fifth layer (uppermost layer) including the pixel electrode 9a and the like. Further, the base insulating film 12 is provided between the first layer and the second layer, the first interlayer insulating film 41 is provided between the second layer and the third layer, and the second interlayer insulating film 42 is provided between the third layer and the fourth layer. The third interlayer insulating film 43 is provided between the fourth layer and the fifth layer, respectively, to prevent the above-described elements from being short-circuited. Further, in these various insulating films 12, 41, 42 and 43, for example, contact holes 81c for electrically connecting the data line side source / drain regions 4d and the data lines 6c in the semiconductor layer 4a of the TFT 30c are formed. Has been. Hereinafter, each of these elements will be described in order from the bottom. Of the laminated structure described above, the first to third layers are shown in FIG. 12 as the lower layer portion, and the second interlayer insulating film 42 to the sixth layer are shown in FIG. 13 as the upper layer portion. Yes.

(Structure of the first layer-scanning line 11 etc.)
In FIG. 13, a scanning line 11 is provided as the first layer. The scanning line 11 is configured in the same manner as in the first embodiment described above, and extends so as to overlap the data line 6c along the Y direction from the main line portion 11x and the main line portion 11x extending along the X direction. The extended portion 11y is provided.

  In the present embodiment, an overhang portion 11t is provided as in the first embodiment described above. Therefore, compared with the case where the overhanging portion 11t does not exist, the return light incident on the semiconductor layer 4a of the TFT 30c can be effectively shielded by the overhanging portion 11t.

(Configuration of the second layer-TFT 30c etc.)
In FIG. 13, a TFT 30c is provided as the second layer.

  As shown in FIGS. 11 and 13, the TFT 30c includes a semiconductor layer 4a and a gate electrode 3c.

  The semiconductor layer 4a is made of, for example, polysilicon, and has a channel region 4a ′ having a channel length along the X direction, a data line side LDD region 4b, a pixel electrode side LDD region 4c, a data line side source / drain region 4d, and a pixel electrode. The side source / drain region 4e is formed. That is, the TFT 30c has an LDD structure.

  The data line side source / drain region 4d and the pixel electrode side source / drain region 4e are formed in substantially mirror symmetry along the X direction with respect to the channel region 4a '. The data line side LDD region 4b is formed between the channel region 4a 'and the data line side source / drain region 4d. The pixel electrode side LDD region 4c is formed between the channel region 4a 'and the pixel electrode side source / drain region 4e. The data line side LDD region 4b, the pixel electrode side LDD region 4c, the data line side source / drain region 4d, and the pixel electrode side source / drain region 4e are formed by implanting impurities into the semiconductor layer 4a by, for example, ion implantation. This is an impurity region. The data line side LDD region 4b and the pixel electrode side LDD region 4c are formed as low concentration impurity regions with less impurities than the data line side source / drain region 4d and the pixel electrode side source / drain region 4e, respectively. According to such an impurity region, when the TFT 30c is not in operation, the off current flowing in the source region and the drain region can be reduced, and the decrease in the on current and the increase in the off leakage current that can occur in the operation of the TFT 30c can be suppressed.

  The scanning line 11 and the semiconductor layer 4a are insulated by the base insulating film 12.

  As shown in FIGS. 11 and 13, the gate electrode 3c is arranged on the upper layer side of the semiconductor layer 4a via the gate insulating film 2a. That is, the TFT 30c is formed as a top gate type TFT. The gate electrode 3c is made of a light-shielding conductive material such as a refractory metal material such as W, Ti, or TiN. The gate electrode 3c may be made of, for example, conductive polysilicon.

  As shown in FIG. 11, the gate electrode 3c has a main body portion 3ca overlapping the channel region 4a 'of the TFT 30c, and an extending portion 32 extending from the main body portion 3ca along the X direction. The gate electrode 3 c is electrically connected to the scanning line 11 through a contact hole 82 c opened in the base insulating film 12.

  One contact hole 82c is formed on each side of the semiconductor layer 4a as a wall-shaped light shielding body along the X direction. Therefore, it is possible to block light incident obliquely from both sides with respect to the semiconductor layer 4a. Therefore, the light leakage current in the TFT 30c can be more reliably reduced.

  In this embodiment, the gate electrodes 3c of the respective TFTs 30c are formed separately from each other. However, for example, the gate electrodes 3c of the TFTs 30c corresponding to the same scanning line 11 may be formed so as to be connected to each other. In other words, it may be formed as another scanning line arranged in a layer opposite to the scanning line 11 with respect to the semiconductor layer 4a, including the gate electrode 3c of the TFT 30c corresponding to the same scanning line 11. In this case, the scanning line can be configured as a double wiring, and the scanning signal can be supplied to the gate electrode 3c more reliably.

(Configuration of the third layer—data line 6c, etc.)
In FIG. 13, a data line 6c is provided as the third layer. In the third layer, the relay layer 94 is formed of the same film as the data line 6c.

  As shown in FIGS. 11 and 13, the data line 6c includes a main line portion extending along the Y direction and an extending portion 6cx extending from the main line portion along the X direction. In the extended portion 6cx, the data line 6c is electrically connected to the data line side source / drain region 4d of the semiconductor layer 4a through a contact hole 81c opened through the first interlayer insulating film 41 and the gate insulating film 2a. Connected. The data line 6c and the inside of the contact hole 81c are made of, for example, an Al-containing material such as Al—Si—Cu or Al—Cu, Al alone, or a multilayer film including an Al layer and a TiN layer. The data line 6c also has a function of shielding the TFT 30c.

  The relay layer 94 is formed in the same layer as the data line 6 c on the first interlayer insulating film 41. The relay layer 94 is electrically connected to the pixel electrode side source / drain region 4e through a contact hole 83c opened through the first interlayer insulating film 41 and the gate insulating film 2a, and also has a second interlayer insulating property. It is electrically connected to a lower capacitor electrode 71c of a storage capacitor 70c to be described later via a contact hole 84c (see FIG. 12) opened in the film 42. Further, the lower capacitor electrode 71c is electrically connected to the pixel electrode 9a through a contact hole 85c (see FIG. 12) opened through an insulating film 61 and a third interlayer insulating film 43 described later. . That is, the relay layer 94 relays the electrical connection between the pixel electrode side source / drain region 4e and the pixel electrode 9a together with the lower capacitor electrode 71b.

  The relay layer 94 is an example of the “first conductive film” according to the present invention, and the lower capacitor electrode 71 is an example of the “second conductive film” according to the present invention.

(Fourth layer configuration-storage capacity 70c, etc.)
In FIG. 13, a storage capacitor 70c is provided as the fourth layer. The storage capacitor 70c is provided on the upper layer side through the second interlayer insulating film 42 with respect to the data line 6c.

  The storage capacitor 70c is formed by disposing the upper capacitor electrode 300c and the lower capacitor electrode 71c so as to face each other through the dielectric film 75c. The lower capacitor electrode 71c, the dielectric film 75c, and the upper capacitor electrode 300c are stacked in this order from the lower layer side.

  An insulating film 61 is provided between the second interlayer insulating film 42 and the third interlayer insulating film 43 so as to be partially interposed between the lower capacitor electrode 71c and the upper capacitor electrode 300c.

  As shown in FIGS. 12 and 13, the upper capacitor electrode 300 c is formed as a part of the capacitor line 300. The capacitance line 300 extends from the image display area 10a where the pixel electrode 9a is disposed to the periphery thereof. The upper capacitor electrode 300c is a fixed potential side capacitor electrode that is electrically connected to a constant potential source via the capacitor line 300 and maintained at a fixed potential. The upper capacitor electrode 300c is formed of a non-transparent metal film containing, for example, a metal such as Al or Ag or an alloy, and also functions as an upper light shielding film that shields the TFT 30c. The upper capacitor electrode 300c includes, for example, at least one of refractory metals such as Ti, Cr, W, Ta, Mo, and Pd, and a single metal, an alloy, a metal silicide, a polysilicide, and the like laminated. You may be comprised from things.

  The lower capacitor electrode 71c is a pixel potential side capacitor electrode electrically connected to the pixel electrode side source / drain region 4e of the TFT 30c and the pixel electrode 9a. More specifically, the lower capacitor electrode 71 is electrically connected to the pixel electrode side source / drain region 4e through the contact hole 84c, the relay layer 94, and the contact hole 83c, and is connected to the pixel electrode through the contact hole 85c. It is electrically connected to 9a. The lower capacitor electrode 71c is formed of a non-transparent metal film containing, for example, a metal such as Al or Ag or an alloy, and also functions as an upper light shielding film that shields the TFT 30c. The lower capacitor electrode 71c is formed by laminating a single metal, an alloy, a metal silicide, a polysilicide, or the like including at least one of refractory metals such as Ti, Cr, W, Ta, Mo, and Pd. You may be comprised from things.

  Therefore, the storage capacitor 70c has a so-called MIM structure. Therefore, the power consumption consumed by the upper capacitor electrode 300c and the lower capacitor electrode 71c can be reduced according to various signals supplied to the upper capacitor electrode 300c and the lower capacitor electrode 71c. In addition, as compared with the case where any one of the upper capacitor electrode 300c and the lower capacitor electrode 71c is formed of a semiconductor film, the conductivity of this one electrode is increased, and the function of the storage capacitor 70c as a storage capacitor is further improved. be able to.

  The dielectric film 75c has, for example, a single layer structure or a multilayer structure made of a silicon oxide film such as an HTO film or an LTO film, a silicon nitride film, or an insulating metal oxide such as alumina or hafnia. Yes.

  As shown in FIG. 12, in particular, in the present embodiment, the lower capacitor electrode 71c has a protruding portion that protrudes from the corner of the opening region toward the center of the opening region in the intersection region where the scanning line 11 and the data line 6a intersect each other. 71 ct. The overhang portion 71ct is formed so as to substantially overlap the overhang portion 11t described above with reference to FIGS. 4 and 7 and to define a part of the non-opening region. Therefore, as compared with the case where the overhang portion 71ct does not exist, the light incident on the semiconductor layer 4a of the TFT 30c from the upper layer side can be effectively blocked by the overhang portion 71ct. Thereby, the light-shielding property with respect to TFT30c can be improved, for example, generation | occurrence | production of the light leakage current in TFT30c can be reduced more reliably.

  Further, particularly in the present embodiment, the overhang portion 71ct is formed at each of the four corners of the opening area of each pixel. In other words, four overhang portions 71ct are provided around each semiconductor layer 4a provided in the intersecting region. Therefore, the light incident obliquely on the semiconductor layer 4a from the upper layer side can be more reliably shielded by the overhang portion 71ct.

  In addition, in the present embodiment, in particular, the contact hole 84c that electrically connects the lower capacitor electrode 71c and the relay layer 94 overlaps the overhanging portions 11t and 71ct when viewed in plan on the TFT array substrate 10. Is arranged. That is, a contact hole 84c is opened in the second interlayer insulating film 42 at a position overlapping the projecting portions 11t and 71ct when viewed in plan on the TFT array substrate 10. Therefore, in the non-opening region defined by the data line 6c, the scanning line 11, and the storage capacitor 70c, the contact hole 84c is formed in the region where the overhang portions 11t and 71ct are formed as the light shielding region for improving the light shielding property to the TFT 30c. Is arranged. Therefore, the width d1 of the region extending along the data line 6c or the width d2 of the region extending along the scanning line 11 in the non-opening region is unnecessarily enlarged only for the arrangement of the contact hole 84c. Separately, it is possible to prevent a part of the non-opening area from being unnecessarily enlarged, and it is possible to secure a larger opening area size in each pixel. That is, the aperture ratio can be improved.

  In addition, the contact hole 84c is arranged so as to overlap with the overhanging portions 11t and 71ct, so that light incident obliquely on the semiconductor layer 4a from the upper layer side is transmitted through the contact hole 84c (ie, the contact hole 84c). Further, light can be more reliably shielded by the portion of the lower capacitor electrode 71c formed in the contact hole 84c.

(Fifth layer configuration-pixel electrode 9a, etc.)
In FIG. 13, a pixel electrode 9a is provided as the fifth layer. The pixel electrode 9a is formed on the upper layer side of the storage capacitor 71c via the third interlayer insulating film 43.

  As shown in FIGS. 12 and 13, the pixel electrode 9a is electrically connected to the pixel electrode side source / drain region 4e of the semiconductor layer 4a via the lower capacitor electrode 71c, the contact holes 83c, 84c and 85c, and the relay layer 94. It is connected.

As described above, according to the liquid crystal device according to the present embodiment, it is possible to improve the aperture ratio while improving the light shielding property with respect to the TFT 30c, and finally it is possible to display a bright and high-quality image.
<Electronic equipment>
Next, the case where the above-described liquid crystal device which is an electro-optical device is applied to various electronic devices will be described with reference to FIGS. Hereinafter, a projector using the liquid crystal device as a light valve will be described. FIG. 14 is a plan view showing a configuration example of the projector.

  As shown in FIG. 14, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R and 1110B.

  In addition, since light corresponding to each primary color of R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 14, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook , Calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), The present invention is also applicable to an organic EL display, a digital micromirror device (DMD), an electrophoresis apparatus, and the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change. In addition, an electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

  6a ... Data line, 9a ... Pixel electrode, 10 ... TFT array substrate, 10a ... Image display area, 11 ... Scanning line, 11t ... Overhang, 20 ... Counter substrate, 21 ... Counter electrode, 30 ... TFT, 41, 42 , 43, 44 ... interlayer insulating film, 50 ... liquid crystal layer, 81, 82, 83, 84, 85, 86 ... contact holes, 101 ... data line driving circuit, 104 ... scanning line driving circuit.

Claims (6)

A data line extending in a first direction;
A transistor electrically connected to the data line;
A pixel electrode provided corresponding to the transistor;
A light shielding portion provided so as to overlap with a semiconductor layer of the transistor;
A first relay layer electrically connected to the semiconductor layer of the transistor;
A second relay layer provided in a layer between the first relay layer and the pixel electrode, and electrically connecting the first relay layer and the pixel electrode;
The light shielding portion includes a first light shielding portion extending in the first direction, a second light shielding portion extending in a second direction intersecting the first direction, and each of the first and second light shielding portions. A third light-shielding portion that extends and projects to the corner of the opening area of the pixel,
It said first contact hole, wherein the first relay layer and a second relay layer electrically connected is provided in overlap with so that said second light blocking portion,
A second contact hole electrically connecting the second relay layer and the pixel electrode is provided so as to overlap the third light shielding portion;
The electro-optical device, wherein the transistor is provided so that a channel region of the transistor and the data line overlap in a plan view. Having a scan line extending along the second direction;
The electro-optical device according to claim 1, wherein the transistor is provided so that a channel region of the transistor overlaps an intersecting region where the data line and the scanning line overlap in a plan view. 3. The electro-optical device according to claim 1, wherein the first light-shielding portion is provided so as to overlap with the data line. It said first contact hole, the electro-optical device according to provided to any one of claims 1 to 3, characterized in between the other data line adjacent to the data line and the data line . Said first and second relay layer, electro-optic according to any one of claims 1 to 4, characterized in that provided in a layer between the semiconductor layer and the pixel electrode of each of the transistors apparatus. An electronic device characterized by being provided with the electro-optical device according to claim 1, any one of 5.

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