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JP5890798B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5890798B2
JP5890798B2 JP2013111057A JP2013111057A JP5890798B2 JP 5890798 B2 JP5890798 B2 JP 5890798B2 JP 2013111057 A JP2013111057 A JP 2013111057A JP 2013111057 A JP2013111057 A JP 2013111057A JP 5890798 B2 JP5890798 B2 JP 5890798B2
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wire loop
gold
gold ball
electrode pad
wire
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JP2013165302A (en
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勲 栗田
勲 栗田
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Lapis Semiconductor Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48991—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on the semiconductor or solid-state body to be connected
    • H01L2224/48992—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/85951—Forming additional members, e.g. for reinforcing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

本発明は、半導体ＩＣチップと外部電極端子とをワイヤボンディングによって形成されるワイヤループで接続した構造を有する半導体装置及びその製造方法に関するものである。   The present invention relates to a semiconductor device having a structure in which a semiconductor IC chip and an external electrode terminal are connected by a wire loop formed by wire bonding, and a manufacturing method thereof.

半導体装置の製造に際して、半導体ＩＣチップの電極パッドとインナーリードとをワイヤボンディングによって電気的に接続する方法が種々提案されている（例えば、特許文献１及び２参照）。例えば、典型的なワイヤボンディングでは、図１３に示されるように、ダイパッド１上に接着剤２で固定された半導体ＩＣチップ３の電極パッド４に、ワイヤボンディング装置（図示せず）によって金球５をボンディングする工程と、金球５の頂部５ａから真上方向に所定の長さＨ６ａのネック部（垂直立ち上がり部）６ａが形成されるようにワイヤループ６を形成する工程と、ワイヤループ６をインナーリード４０まで引き出してインナーリード４０にボンディングする工程とを有している。 In manufacturing a semiconductor device, various methods for electrically connecting the electrode pads of the semiconductor IC chip and the inner leads by wire bonding have been proposed (see, for example, Patent Documents 1 and 2). For example, in typical wire bonding, as shown in FIG. 13, a gold ball 5 is applied to an electrode pad 4 of a semiconductor IC chip 3 fixed on the die pad 1 with an adhesive 2 by a wire bonding apparatus (not shown). a step of bonding, forming a wire loop 6 as neck of predetermined length H 6a right above direction from the top portion 5a of the gold sphere 5 (vertical rise portion) 6a is formed, the wire loops 6 A step of drawing the wire to the inner lead 40 and bonding it to the inner lead 40.

特開２００８−１１７８８８号公報JP 2008-117888 A 特開２００８−３４５６７号公報JP 2008-34567 A

しかしながら、上記従来の製造方法におけるワイヤボンディングでは、金球５の頂部５ａに発生するストレス（応力）を低減するために、ワイヤループ６のネック部６ａの長さＨ６ａをある程度長くする必要があった。このため、半導体ＩＣチップ３とワイヤループ６とを含む従来の半導体装置においては、ワイヤループ６の高さＨ６を十分に低くすることは困難であり、半導体装置の薄型化を十分に実現することができないという問題があった。 However, in the wire bonding in the above conventional manufacturing method, it is necessary to lengthen the length H 6a of the neck portion 6a of the wire loop 6 to some extent in order to reduce the stress (stress) generated in the top portion 5a of the gold ball 5. It was. Therefore, in the conventional semiconductor device including a semiconductor IC chip 3 and the wire loop 6, to sufficiently lower the height H 6 of the wire loops 6 is difficult to sufficiently reduce the thickness of the semiconductor device There was a problem that I could not.

そこで、本発明は、上記従来技術の課題を解決するためになされたものであり、その目的は、薄型化された半導体装置及び薄型化を実現できる製造方法を提供することにある。   Accordingly, the present invention has been made to solve the above-described problems of the prior art, and an object thereof is to provide a thinned semiconductor device and a manufacturing method capable of realizing the thinning.

本発明に係る半導体装置の製造方法は、半導体チップの表面上に形成された電極パッドに第１の金球によってワイヤの一端をボンディングし、前記電極パッドと離間して形成された外部電極に前記一端がボンディングされた前記ワイヤの他端をボンディングして、前記電極パッドから前記外部電極までのワイヤループを形成する工程と、キャピラリの先端に形成された第２の金球の中心位置が前記ワイヤループの前記一端をボンディングする前記第１の金球の中心位置よりも前記外部電極に近い位置になるように且つ前記第２の金球と前記ワイヤループの前記一端をボンディングする前記第１の金球との間に前記ワイヤループを挟むように、前記第２の金球を前記ワイヤループの前記一端と前記第１の金球に向けて押し付けて、前記第１の金球、前記第２の金球、及び前記第１の金球と前記第２の金球との間に挟まれた前記ワイヤループを形成する工程とを有することを特徴としている。 In the method of manufacturing a semiconductor device according to the present invention, one end of a wire is bonded to an electrode pad formed on the surface of a semiconductor chip by a first gold ball, and the external electrode formed apart from the electrode pad is bonded to the external electrode. Bonding the other end of the wire bonded at one end to form a wire loop from the electrode pad to the external electrode, and the center position of the second gold ball formed at the tip of the capillary is the wire The first gold for bonding the second gold ball and the one end of the wire loop so as to be closer to the external electrode than the center position of the first gold ball for bonding the one end of the loop The second gold ball is pressed against the one end of the wire loop and the first gold ball so that the wire loop is sandwiched between the first gold ball and the first gold ball. It is characterized by having the second gold spheres, and a step of forming the wire loop sandwiched between the first gold ball and the second gold spheres.

本発明によれば、ワイヤループの最上部の高さを低くすることができる位置にバンプ金球をボンディングしているので、半導体装置の薄型化を実現することができる。   According to the present invention, since the bump gold sphere is bonded at a position where the height of the uppermost portion of the wire loop can be lowered, the semiconductor device can be thinned.

本発明の第１の実施形態に係る半導体装置の製造方法の一工程（その１）を概略的に示す縦断面図である。It is a longitudinal section showing roughly one process (the 1) of a manufacturing method of a semiconductor device concerning a 1st embodiment of the present invention. 本発明の第１の実施形態に係る半導体装置の製造方法の一工程（その２）を概略的に示す縦断面図である。It is a longitudinal cross-sectional view which shows roughly 1 process (the 2) of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造方法の一工程（その３）を概略的に示す縦断面図である。It is a longitudinal cross-sectional view which shows roughly 1 process (the 3) of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態に係る半導体装置の製造方法の一工程（その４）（第１の実施形態に係る半導体装置）を概略的に示す縦断面図である。It is a longitudinal cross-sectional view which shows roughly 1 process (the 4) (semiconductor device which concerns on 1st Embodiment) of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 図４の構造体を概略的に示す平面図である。FIG. 5 is a plan view schematically showing the structure of FIG. 4. 本発明の第１の実施形態に係る半導体装置及びその製造方法を説明するための要部拡大図である。It is a principal part enlarged view for demonstrating the semiconductor device which concerns on the 1st Embodiment of this invention, and its manufacturing method. 本発明の第２の実施形態に係る半導体装置を概略的に示す縦断面図である。It is a longitudinal section showing a semiconductor device concerning a 2nd embodiment of the present invention roughly. 図７の構造体を概略的に示す平面図である。FIG. 8 is a plan view schematically showing the structure of FIG. 7. 本発明の第２の実施形態に係る半導体装置及びその製造方法を説明するための要部拡大図である。It is a principal part enlarged view for demonstrating the semiconductor device which concerns on the 2nd Embodiment of this invention, and its manufacturing method. 本発明の第３の実施形態に係る半導体装置を概略的に示す縦断面図である。It is a longitudinal section showing a semiconductor device concerning a 3rd embodiment of the present invention roughly. 図１０の構造体を概略的に示す平面図である。It is a top view which shows the structure of FIG. 10 roughly. 本発明の第３の実施形態に係る半導体装置及びその製造方法を説明するための要部拡大図である。It is a principal part enlarged view for demonstrating the semiconductor device which concerns on the 3rd Embodiment of this invention, and its manufacturing method. 従来の半導体装置を概略的に示す縦断面図である。It is a longitudinal cross-sectional view which shows the conventional semiconductor device roughly.

第１の実施形態．
図１〜図４は、本発明の第１の実施形態に係る半導体装置の製造方法の工程を概略的に示す縦断面図であり、図５は、図４の構造体を概略的に示す平面図である。 First embodiment.
1 to 4 are longitudinal sectional views schematically showing steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 5 is a plan view schematically showing the structure of FIG. FIG.

第１の実施形態に係る半導体装置の製造方法においては、先ず、図１に示されるように、ダイパッド１１上に接着剤１２で固定された半導体ＩＣチップ１３と、外部電極端子としてのインナーリード４０とを、ワイヤボンディング装置（図示せず）の所定位置に置く。このとき、一般的には、インナーリード４０は、半導体ＩＣチップ１３の表面よりも低い位置に配置される。第１の実施形態においては、半導体ＩＣチップ１３として、その上面に、インナーリード４０に向かう方向に並ぶワイヤボンディング用の第１の電極パッド１４ａと第２の電極パッド１４ｂとを備えたものを用いる。第１の電極パッド１４ａと第２の電極パッド１４ｂとは、別個の電極であるが、半導体ＩＣチップ１３内で電気的に接続されている。また、第１の実施形態においては、第１の電極パッド１４ａと第２の電極パッド１４ｂとは、上面が同じ高さに形成されている。   In the method of manufacturing a semiconductor device according to the first embodiment, first, as shown in FIG. 1, the semiconductor IC chip 13 fixed on the die pad 11 with the adhesive 12 and the inner leads 40 as external electrode terminals. Are placed at predetermined positions of a wire bonding apparatus (not shown). At this time, generally, the inner lead 40 is disposed at a position lower than the surface of the semiconductor IC chip 13. In the first embodiment, a semiconductor IC chip 13 having a first electrode pad 14a and a second electrode pad 14b for wire bonding arranged in the direction toward the inner lead 40 on the upper surface thereof is used. . The first electrode pad 14 a and the second electrode pad 14 b are separate electrodes, but are electrically connected within the semiconductor IC chip 13. In the first embodiment, the first electrode pad 14a and the second electrode pad 14b are formed with the same upper surface.

また、第１の実施形態においては、半導体ＩＣチップ１３として、その上面に、絶縁膜１８を備えたものを用いてもよい。この絶縁膜１８は、少なくともバンプ金球１７とインナーリード４０とを電気的に接続するワイヤループ１６の下に形成されていればよい。この場合には、後述するワイヤループ１６の高さが低くなりすぎて、半導体ＩＣチップ１３に接触する場合であっても、接触箇所は絶縁膜１８であるので、性能上の不具合は発生しない。   In the first embodiment, the semiconductor IC chip 13 having an insulating film 18 on the upper surface may be used. The insulating film 18 only needs to be formed under the wire loop 16 that electrically connects at least the bump gold ball 17 and the inner lead 40. In this case, even when the height of the wire loop 16 to be described later becomes too low to come into contact with the semiconductor IC chip 13, the contact location is the insulating film 18, so that there is no problem in performance.

次に、図２に示されるように、ワイヤボンディング装置のキャピラリ（図示せず）によって、半導体ＩＣチップ１３の第１の電極パッド１４ａに金球（第１の金球）１５によってワイヤの一端をボンディングし、インナーリード４０にワイヤの他端をボンディングして、第１の電極パッド１４ａからインナーリード４０までのワイヤループ１６を形成する。このとき、第１の電極パッド１４ａ側からインナーリード４０に向かってワイヤループ１６を形成することで、後の工程で第２の電極パッド１４ｂ上にワイヤループ１６を挟んでバンプ金球１７をボンディングする際に、一般に最もループが高くなるボンディング始点近傍のワイヤループ１６をバンプ金球１７で押さえ付け、かつワイヤループ１６と第１の電極パッド１４ａと電気的に接続された第２の電極パッド１４ｂとの電気的接続を図れるようになるため、ワイヤループ１６の低ループ化を図りつつも半導体ＩＣチップ１３とインナーリード４０との電気的信頼性を確保するという本願発明の効果をより得ることができる。この場合のワイヤループ１６の高さは、約８０〜１５０μｍであるが、低ループ（例えば、約８０〜１００μｍ）であることが望ましい。   Next, as shown in FIG. 2, one end of the wire is attached to the first electrode pad 14 a of the semiconductor IC chip 13 by the gold ball (first gold ball) 15 by the capillary (not shown) of the wire bonding apparatus. Bonding is performed, and the other end of the wire is bonded to the inner lead 40 to form the wire loop 16 from the first electrode pad 14 a to the inner lead 40. At this time, by forming the wire loop 16 from the first electrode pad 14 a side toward the inner lead 40, the bump gold ball 17 is bonded to the second electrode pad 14 b with the wire loop 16 sandwiched in a later step. In this case, generally, the wire loop 16 in the vicinity of the bonding start point where the loop becomes the highest is pressed by the bump gold ball 17 and the second electrode pad 14b electrically connected to the wire loop 16 and the first electrode pad 14a. Therefore, it is possible to obtain the effect of the present invention of ensuring the electrical reliability between the semiconductor IC chip 13 and the inner lead 40 while reducing the loop of the wire loop 16. it can. In this case, the height of the wire loop 16 is about 80 to 150 μm, but is preferably a low loop (for example, about 80 to 100 μm).

次に、図３に示されるように、ワイヤボンディング装置のキャピラリ５０の先端にバンプ金球（第２の金球）１７ａを形成し、その後、図４に示されるように、金球１５よりインナーリード４０側の半導体ＩＣチップ１３上の所定位置、すなわち、第２の電極パッド１４ｂ上の位置で、ワイヤループ１６の途中を半導体ＩＣチップ１３側に押し下げるように、バンプ金球１７をボンディングする。バンプ金球１７は、ワイヤループ１６を挟んで第２の電極パッド１４ｂに電気的に接続されること、及び、その第２の電極パッド１４ｂが第１の電極パッド１４ａと電気的に接続されていることをもって、低ループとしたことによって仮に金球１５上のワイヤループ１６が破断したとしても半導体ＩＣチップ１３とインナーリード４０との電気的接続の信頼性を確保することが可能となる。   Next, as shown in FIG. 3, a bump gold ball (second gold ball) 17a is formed at the tip of the capillary 50 of the wire bonding apparatus, and then, as shown in FIG. The bump gold ball 17 is bonded so as to push the middle of the wire loop 16 toward the semiconductor IC chip 13 at a predetermined position on the semiconductor IC chip 13 on the lead 40 side, that is, on the second electrode pad 14b. The bump gold ball 17 is electrically connected to the second electrode pad 14b across the wire loop 16, and the second electrode pad 14b is electrically connected to the first electrode pad 14a. Therefore, the reliability of electrical connection between the semiconductor IC chip 13 and the inner lead 40 can be ensured even if the wire loop 16 on the gold ball 15 is broken due to the low loop.

図６は、本発明の第１の実施形態に係る半導体装置及びその製造方法を説明するための要部拡大図である。図６に示されるように、前記所定位置（例えば、金球１５の中心位置とバンプ金球１７の中心位置との間の距離Ｄ１７で特定できる）は、バンプ金球１７によるワイヤループ１６のボンディング後のワイヤループ１６の最上部の高さを、バンプ金球１７によるワイヤループ１６のボンディング前のワイヤループ１６の最上部の高さよりも低くする位置であって、少なくともバンプ金球１７よりインナーリード４０側のワイヤループ１６の最上部の高さＨ１６をバンプ金球１７の頂部１７ａの高さＨ１７よりも低くする位置に設定される。また、前記所定位置は、ワイヤループ１６の全体の中の最上部の高さ（バンプ金球１７より金球１５側をも含む範囲内で最上部の高さ）を、バンプ金球１７の頂部１７ａよりも低くする位置（例えば、高さ５０μｍ以下）に設定されることが望ましい。 FIG. 6 is an enlarged view of a main part for explaining the semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention. As shown in FIG. 6, the predetermined position (for example, can be specified by a distance D 17 between the center position of the gold ball 15 and the center position of the bump gold ball 17) of the wire loop 16 by the bump gold ball 17. The position of the uppermost portion of the wire loop 16 after bonding is lower than the height of the uppermost portion of the wire loop 16 before the bonding of the wire loop 16 by the bump gold sphere 17, and is at least inner than the bump gold sphere 17. It is set to the top of the height H 16 of the lead 40 side wire loop 16 at a position lower than the height H 17 of the top portion 17a of the bump metal ball 17. Further, the predetermined position is the height of the uppermost portion of the entire wire loop 16 (the height of the uppermost portion within the range including the gold ball 15 side from the bump gold ball 17), and the top of the bump gold ball 17. It is desirable to set a position lower than 17a (for example, a height of 50 μm or less).

前記所定位置は、金球１５の位置、インナーリード４０の位置、ワイヤループ１６及びバンプ金球１７を構成する材料、使用するキャピラリの動作条件、金球１５の頂部１５ａに発生するストレスの許容値などの各種条件に基づいて、例えば、計算により、又は、実験的に求めることができる。例えば、バンプ金球１７の位置は、バンプ金球１７をボンディングする前のワイヤループ１６が最も高くなる位置又はその近傍位置にすることが好ましい。したがって、半導体ＩＣチップ１３は、第２の電極パッド１４ｂを、求められた前記所定位置に対応する位置にするように形成する必要がある。   The predetermined position includes the position of the gold ball 15, the position of the inner lead 40, the material constituting the wire loop 16 and the bump gold ball 17, the operating condition of the capillary used, and the allowable value of the stress generated on the top 15 a of the gold ball 15. For example, it can be obtained by calculation or experimentally based on various conditions such as. For example, the position of the bump gold sphere 17 is preferably set at a position where the wire loop 16 before bonding the bump gold sphere 17 is highest or in the vicinity thereof. Therefore, the semiconductor IC chip 13 needs to be formed so that the second electrode pad 14b is at a position corresponding to the predetermined position obtained.

以上に説明したように、第１の実施形態に係る半導体装置及びその製造方法によれば、ワイヤループ１６の途中を半導体ＩＣチップ１３側に押し下げるようにバンプ金球１７をボンディングすることでワイヤループ１６の最上部の高さを低くすることができるため、半導体装置の薄型化を実現することができる。   As described above, according to the semiconductor device and the manufacturing method thereof according to the first embodiment, the wire loop 17 is bonded by bonding the bump metal ball 17 so as to push the middle of the wire loop 16 toward the semiconductor IC chip 13 side. Since the height of the uppermost portion of 16 can be reduced, the semiconductor device can be thinned.

また、第１の電極パッド１４ａ及び第２の電極パッド１４ｂを別個に設けた場合には、第１の電極パッド１４ａから第２の電極パッド１４ｂまでの距離を大きく離すことができるので、第１の実施形態の半導体装置及びその製造方法は、バンプ金球１７によるボンディング位置を金球１５によるボンディング位置から大きく離す必要がある場合に好適である。例えば、ループ長が長い（例えば３ｍｍ以上）場合は、ワイヤループ１６の高い場所が半導体ＩＣチップ１３周辺付近ではなくワイヤループ１６の中央部付近となる場合があり、その場合は、第１の電極パッド１４ａから第２の電極パッド１４ｂまでの距離をある程度離して、ワイヤループ１６の高さを最も低くすることができる位置に第２の電極パッド１４ｂを設けることが効果的である。   In addition, when the first electrode pad 14a and the second electrode pad 14b are provided separately, the distance from the first electrode pad 14a to the second electrode pad 14b can be greatly separated, so that the first The semiconductor device and the manufacturing method thereof according to the embodiment are suitable when the bonding position by the bump gold sphere 17 needs to be greatly separated from the bonding position by the gold sphere 15. For example, when the loop length is long (for example, 3 mm or more), the place where the wire loop 16 is high may not be near the semiconductor IC chip 13 but near the center of the wire loop 16, and in this case, the first electrode It is effective to provide the second electrode pad 14b at a position where the height of the wire loop 16 can be minimized by separating the pad 14a from the second electrode pad 14b to some extent.

第２の実施形態．
図７は、本発明の第２の実施形態に係る半導体装置の製造方法の工程を概略的に示す縦断面図であり、図８は、図７の構造体を概略的に示す平面図であり、図９は、本発明の第２の実施形態に係る半導体装置及びその製造方法を説明するための要部拡大図である。 Second embodiment.
FIG. 7 is a longitudinal sectional view schematically showing the steps of the semiconductor device manufacturing method according to the second embodiment of the present invention, and FIG. 8 is a plan view schematically showing the structure of FIG. FIG. 9 is an enlarged view of a main part for explaining the semiconductor device and the manufacturing method thereof according to the second embodiment of the present invention.

第２の実施形態に係る半導体装置の製造方法においては、図７に示されるように、ダイパッド２１上に接着剤２２で固定された半導体ＩＣチップ２３と、インナーリード４０とを、ワイヤボンディング装置（図示せず）の所定位置に置く。このとき、一般的には、インナーリード４０は、半導体ＩＣチップ２３の表面よりも低い位置に配置される。第２の実施形態においては、半導体ＩＣチップ２３の上面には、インナーリード４０に向かう方向に長尺なワイヤボンディング用の１つの電極パッド２４が備えられている。第２の実施形態における電極パッド２４は、第１の実施形態における第１の電極パッド１４ａと第２の電極パッド１４ｂとを一体的に形成した構成をも含む。また、半導体ＩＣチップ２３の上面には、必要に応じて、絶縁膜２８を備えてもよい。この絶縁膜２８は、少なくともバンプ金球２７とインナーリード４０とを電気的に接続するワイヤループ２６の下に形成されていればよい。   In the method of manufacturing a semiconductor device according to the second embodiment, as shown in FIG. 7, a semiconductor IC chip 23 fixed on the die pad 21 with an adhesive 22 and an inner lead 40 are connected to a wire bonding apparatus ( (Not shown). At this time, generally, the inner lead 40 is disposed at a position lower than the surface of the semiconductor IC chip 23. In the second embodiment, one electrode pad 24 for wire bonding that is long in the direction toward the inner lead 40 is provided on the upper surface of the semiconductor IC chip 23. The electrode pad 24 in the second embodiment includes a configuration in which the first electrode pad 14a and the second electrode pad 14b in the first embodiment are integrally formed. In addition, an insulating film 28 may be provided on the upper surface of the semiconductor IC chip 23 as necessary. The insulating film 28 only needs to be formed under the wire loop 26 that electrically connects at least the bump gold sphere 27 and the inner lead 40.

次に、キャピラリ（図示せず）によって、半導体ＩＣチップ２３の電極パッド２４に金球２５によってワイヤの一端をボンディングし、インナーリード４０にワイヤの他端をボンディングして、電極パッド２４の金球２５からインナーリード４０までのワイヤループ２６を形成する。   Next, one end of the wire is bonded to the electrode pad 24 of the semiconductor IC chip 23 by a gold ball 25 and the other end of the wire is bonded to the inner lead 40 by a capillary (not shown), and the gold ball of the electrode pad 24 is bonded. A wire loop 26 from 25 to the inner lead 40 is formed.

次に、キャピラリの先端にバンプ金球を形成し、その後、金球２５よりインナーリード４０側の半導体ＩＣチップ２３上の所定位置、すなわち、電極パッド２４の金球２５よりインナーリード４０側のワイヤボンディング用領域に、ワイヤループ２６の途中を半導体ＩＣチップ２３側に押し下げるように、バンプ金球２７によってワイヤループ２６をボンディングする。   Next, a bump gold ball is formed at the tip of the capillary, and then a predetermined position on the semiconductor IC chip 23 on the inner lead 40 side from the gold ball 25, that is, a wire on the inner lead 40 side from the gold ball 25 of the electrode pad 24. The wire loop 26 is bonded to the bonding region by the bump gold balls 27 so as to push the middle of the wire loop 26 toward the semiconductor IC chip 23 side.

第１の実施形態の場合と同様に、前記所定位置（例えば、金球２５の中心位置とバンプ金球２７の中心位置との間の距離Ｄ２７で特定できる）は、バンプ金球２７によるワイヤループ２６のボンディング後のワイヤループ２６の最上部の高さを、バンプ金球２７によるワイヤループ２６のボンディング前のワイヤループ２６の最上部の高さよりも低くする位置であって、少なくともバンプ金球２７よりインナーリード４０側のワイヤループ１６の最上部の高さＨ２６をバンプ金球２７の頂部２７ａの高さＨ２７よりも低くする位置（例えば、高さ５０μｍ以下）に設定される。また、前記所定位置は、ワイヤループ２６の全体の中の最上部の高さをバンプ金球２７の頂部２７ａよりも低くする位置に設定されることが望ましい。 As in the case of the first embodiment, the predetermined position (for example, the distance D 27 between the center position of the gold sphere 25 and the center position of the bump gold sphere 27 can be specified) is a wire formed by the bump gold sphere 27. The height of the uppermost portion of the wire loop 26 after the bonding of the loop 26 is lower than the height of the uppermost portion of the wire loop 26 before the bonding of the wire loop 26 by the bump gold ball 27, and at least the bump gold ball 27, the height H 26 of the uppermost portion of the wire loop 16 on the inner lead 40 side is set to a position (for example, a height of 50 μm or less) that is lower than the height H 27 of the top portion 27a of the bump gold ball 27. The predetermined position is desirably set to a position where the height of the uppermost portion of the entire wire loop 26 is lower than the top portion 27 a of the bump gold ball 27.

前記所定位置は、金球２５の位置、インナーリード４０の位置、ワイヤループ２６及びバンプ金球２７を構成する材料、使用するキャピラリの動作条件、金球２５の頂部２５ａに発生するストレスの許容値などの各種条件に基づいて、例えば、計算により、又は、実験的に求めることができる。したがって、半導体ＩＣチップ２３は、電極パッド２４を、求められた前記所定位置に対応する位置を含むように広く形成する必要がある。なお、第２の実施形態のように、１つの電極パッドを採用した場合（構成を簡素化した場合）と、第１の実施形態のように複数の電極パッドを形成した場合（電極パッド材料を少なくできる場合）では、機能面において差はない。   The predetermined position includes the position of the gold ball 25, the position of the inner lead 40, the material constituting the wire loop 26 and the bump gold ball 27, the operating condition of the capillary used, and the allowable value of the stress generated on the top 25a of the gold ball 25. For example, it can be obtained by calculation or experimentally based on various conditions such as. Therefore, the semiconductor IC chip 23 needs to be widely formed so that the electrode pad 24 includes a position corresponding to the determined predetermined position. As in the second embodiment, when one electrode pad is employed (when the configuration is simplified), and when a plurality of electrode pads are formed as in the first embodiment (the electrode pad material is changed). If it can be reduced), there is no difference in functionality.

以上に説明したように、第２の実施形態に係る半導体装置及びその製造方法によれば、ワイヤループ２６の最上部の高さをバンプ金球を設けない場合よりも低くすることができる位置にバンプ金球２７をボンディングしているので、半導体装置の薄型化を実現することができる。   As described above, according to the semiconductor device and the manufacturing method thereof according to the second embodiment, the height of the uppermost portion of the wire loop 26 can be made lower than when no bump gold ball is provided. Since the bump gold balls 27 are bonded, the semiconductor device can be thinned.

また、第２の実施形態に係る半導体装置及びその製造方法によれば、１つの電極パッド２４に金球２５及びバンプ金球２７を設けるので、金球２５及びバンプ金球２７の距離を小さくしたい場合、すなわち半導体ＩＣチップの面積を小さくしたい場合に好適である。   In addition, according to the semiconductor device and the manufacturing method thereof according to the second embodiment, the gold sphere 25 and the bump gold sphere 27 are provided on one electrode pad 24. Therefore, it is desired to reduce the distance between the gold sphere 25 and the bump gold sphere 27. In other words, it is suitable for reducing the area of the semiconductor IC chip.

なお、第２の実施形態は、半導体ＩＣチップ２３の上面に、インナーリード４０に向かう方向に長尺なワイヤボンディング用の１つの電極パッド２４を備えたことを特徴としており、この特徴が、上記第１の実施形態との相違点である。   The second embodiment is characterized in that one electrode pad 24 for wire bonding that is long in the direction toward the inner lead 40 is provided on the upper surface of the semiconductor IC chip 23. This is a difference from the first embodiment.

第３の実施形態．
図１０は、本発明の第３の実施形態に係る半導体装置の製造方法の工程を概略的に示す縦断面図であり、図１１は、図１０の構造体を概略的に示す平面図であり、図１２は、第３の実施形態に係る半導体装置及びその製造方法を説明するための要部拡大図である。 Third embodiment.
FIG. 10 is a longitudinal sectional view schematically showing the steps of the method for manufacturing a semiconductor device according to the third embodiment of the present invention, and FIG. 11 is a plan view schematically showing the structure of FIG. FIG. 12 is an enlarged view of a main part for explaining the semiconductor device and the manufacturing method thereof according to the third embodiment.

第３の実施形態に係る半導体装置の製造方法においては、ダイパッド３１上に接着剤３２で固定された半導体ＩＣチップ３３と、インナーリード４０とを、ワイヤボンディング装置（図示せず）の所定位置に置く。このとき、一般的には、インナーリード４０は、半導体ＩＣチップ３３の表面よりも低い位置に配置される。第３の実施形態においては、半導体ＩＣチップ３３の上面には、ワイヤボンディング用の電極パッド３４が備えられている。また、半導体ＩＣチップ３３の上面には、必要に応じて、絶縁膜（図示せず）を備えてもよい。この絶縁膜は、少なくともバンプ金球３７とインナーリード４０とを電気的に接続するワイヤループ３６の下に形成されていればよい。   In the semiconductor device manufacturing method according to the third embodiment, the semiconductor IC chip 33 fixed on the die pad 31 with the adhesive 32 and the inner lead 40 are placed at predetermined positions of a wire bonding apparatus (not shown). Put. At this time, generally, the inner lead 40 is disposed at a position lower than the surface of the semiconductor IC chip 33. In the third embodiment, an electrode pad 34 for wire bonding is provided on the upper surface of the semiconductor IC chip 33. In addition, an insulating film (not shown) may be provided on the upper surface of the semiconductor IC chip 33 as necessary. This insulating film only needs to be formed under the wire loop 36 that electrically connects at least the bump gold ball 37 and the inner lead 40.

次に、ワイヤボンディング装置のキャピラリ（図示せず）によって、半導体ＩＣチップ３３の電極パッド３４に金球３５によってワイヤの一端をボンディングし、インナーリード４０にワイヤの他端をボンディングして、電極パッド３４の金球３５からインナーリード４０までのワイヤループ３６を形成する。   Next, one end of the wire is bonded to the electrode pad 34 of the semiconductor IC chip 33 by the gold ball 35 and the other end of the wire is bonded to the inner lead 40 by the capillary (not shown) of the wire bonding apparatus. A wire loop 36 from 34 gold balls 35 to the inner lead 40 is formed.

次に、キャピラリの先端にバンプ金球を形成し、その後、金球３５よりインナーリード４０側（図１２の距離Ｌ３７）の半導体ＩＣチップ３３上の所定位置である金球３５上であって、金球３５よりインナーリード４０側に、ワイヤループ３６の途中を半導体ＩＣチップ３３側に押し下げるように、バンプ金球３７によってワイヤループ３６をボンディングする。バンプ金球３７によってワイヤループ３６をボンディングする工程は、バンプ金球３７で金球３５の頂部に形成されているワイヤループ３６を押さえ付ける工程である。この工程において、金球３５の直上より水平方向に少しずらした位置で金球３５の頂部に形成されているワイヤループ３６をバンプ金球３７で押さえ付けてボンディングしてもよい。例えば、金球３５の中心位置よりインナーリード４０側に中心位置を持つバンプ金球３７によって、金球３５上にワイヤループ３６をボンディングしてもよい。このように、金球３５の直上より水平方向に少しずらした位置で金球３５の頂部に形成されているワイヤループ３６をバンプ金球３７で押さえ付けてボンディングすることで、バンプ金球３７で金球３５の直上から押さえ付ける場合に生じるチップの高さの問題（金球３５とバンプ金球３７との間にワイヤが入ってしまうためにその分チップ全体としての高さが高くなってしまう）を解決でき、チップ全体としての高さを低くすることができる。金球３５とバンプ金球３７とでワイヤループ３６を挟み込む工程を有することで、図１２に示されるように、低ループでワイヤループ３６を形成した場合であっても、バンプ金球３７で金球３５の頂部を補強する構造となっているので、電気的な信頼性を確保することが可能となる。 Next, a bump gold ball is formed at the tip of the capillary, and thereafter, on the gold ball 35 which is a predetermined position on the semiconductor IC chip 33 on the inner lead 40 side (distance L 37 in FIG. 12) from the gold ball 35. The wire loop 36 is bonded by the bump gold ball 37 so as to push the middle of the wire loop 36 toward the semiconductor IC chip 33 side closer to the inner lead 40 side than the gold ball 35. The step of bonding the wire loop 36 with the bump gold ball 37 is a step of pressing the wire loop 36 formed on the top of the gold ball 35 with the bump gold ball 37. In this step, the wire loop 36 formed on the top of the gold sphere 35 may be pressed and bonded by the bump gold sphere 37 at a position slightly shifted in the horizontal direction from directly above the gold sphere 35. For example, the wire loop 36 may be bonded onto the gold sphere 35 by a bump gold sphere 37 having a center position closer to the inner lead 40 than the center position of the gold sphere 35. In this way, by pressing the wire loop 36 formed on the top of the gold ball 35 at the position slightly shifted in the horizontal direction from directly above the gold ball 35 with the bump gold ball 37 and bonding, The problem of the height of the chip that occurs when pressing from directly above the gold sphere 35 (the wire enters between the gold sphere 35 and the bump gold sphere 37, so the height of the entire chip increases accordingly. ) And the overall height of the chip can be reduced. By including the step of sandwiching the wire loop 36 between the gold ball 35 and the bump gold ball 37, even if the wire loop 36 is formed with a low loop as shown in FIG. Since the top portion of the sphere 35 is reinforced, electrical reliability can be ensured.

第３の実施形態に係る半導体装置及びその製造方法によれば、第１の実施形態の場合と同様に、前記所定位置（例えば、金球３５の中心位置とバンプ金球３７の中心位置との間の距離Ｌ３７で特定できる）は、バンプ金球３７よるワイヤループ３６のボンディング後のワイヤループ３６の最上部Ｈ３６の高さを、バンプ金球３７よるワイヤループ３６のボンディング前のワイヤループ３６の最上部の高さよりも低くする位置であって、ワイヤループ３６の最上部の高さＨ３６をバンプ金球３７の頂部３７ａの高さＨ３７よりも低くする位置に設定される。すなわち、前記所定位置は、ワイヤループ３６の全体の中の最上部の高さＨ３６をバンプ金球３７の頂部３７ａの高さＨ３７よりも低くする位置に設定される。 According to the semiconductor device and the manufacturing method thereof according to the third embodiment, as in the case of the first embodiment, the predetermined position (for example, the center position of the gold ball 35 and the center position of the bump gold ball 37) The distance L 37 can be specified by the distance L 37 between the height of the uppermost portion H 36 of the wire loop 36 after the bonding of the wire loop 36 by the bump gold ball 37 and the wire loop 36 before the bonding of the wire loop 36 by the bump gold ball 37. The height H 36 of the uppermost portion of the wire loop 36 is set to a position lower than the height H 37 of the top portion 37 a of the bump gold ball 37. That is, the predetermined position is set to a position where the height H 36 at the top of the entire wire loop 36 is lower than the height H 37 at the top 37 a of the bump gold ball 37.

前記所定位置は、金球３５の位置、インナーリード４０の位置、ワイヤループ３６及びバンプ金球３７を構成する材料、使用するキャピラリの動作条件、金球３５の頂部に発生するストレスの許容値などの各種条件に基づいて、例えば、計算により、又は、実験的に求めることができる。   The predetermined position includes the position of the gold ball 35, the position of the inner lead 40, the material constituting the wire loop 36 and the bump gold ball 37, the operating condition of the capillary used, the allowable value of the stress generated on the top of the gold ball 35, and the like. Based on these various conditions, for example, it can be obtained by calculation or experimentally.

以上に説明したように、第３の実施形態に係る半導体装置及びその製造方法によれば、ワイヤループ３６の最上部の高さを低くすることができる位置にバンプ金球３７をボンディングしているので、半導体装置の薄型化を実現することができる。   As described above, according to the semiconductor device and the manufacturing method thereof according to the third embodiment, the bump gold sphere 37 is bonded to a position where the height of the uppermost portion of the wire loop 36 can be reduced. Therefore, it is possible to reduce the thickness of the semiconductor device.

また、第３の実施形態に係る半導体装置及びその製造方法によれば、金球３５の頂部３５ａを、金球３５の頂部３５ａを押え付けるバンプ金球３７で補強しているので、金球３５の頂部３５ａでワイヤループ３６が破断する危険性を低減でき、電気的性能の信頼性を確保することが可能になる。   Further, according to the semiconductor device and the manufacturing method thereof according to the third embodiment, the top part 35a of the gold sphere 35 is reinforced by the bump gold sphere 37 that presses the top part 35a of the gold sphere 35. It is possible to reduce the risk of the wire loop 36 being broken at the top portion 35a, and to ensure the reliability of the electrical performance.

１１，２１，３１ ダイパッド、 １２，２２，３２ 接着剤、 １３，２３，３３ 半導体ＩＣチップ、 １４ａ 第１の電極パッド、 １４ｂ 第２の電極パッド、 １５，２５，３５ 金球、 １６，２６，３６ ワイヤループ、 １７，２７，３７ バンプ金球、 １８，２８ 絶縁膜、 ２４，３４ 電極パッド、 ４０ インナーリード。   11, 21, 31 Die pad, 12, 22, 32 Adhesive, 13, 23, 33 Semiconductor IC chip, 14a First electrode pad, 14b Second electrode pad, 15, 25, 35 Gold ball, 16, 26, 36 Wire loop, 17, 27, 37 Bump gold ball, 18, 28 Insulating film, 24, 34 Electrode pad, 40 Inner lead.

Claims (3)

半導体チップの表面上に形成された電極パッドに第１の金球によってワイヤの一端をボンディングし、前記電極パッドと離間して形成された外部電極に前記一端がボンディングされた前記ワイヤの他端をボンディングして、前記電極パッドから前記外部電極までのワイヤループを形成する工程と、
キャピラリの先端に形成された第２の金球の中心位置が前記ワイヤループの前記一端をボンディングする前記第１の金球の中心位置よりも前記外部電極に近い位置になるように且つ前記第２の金球と前記ワイヤループの前記一端をボンディングする前記第１の金球との間に前記ワイヤループを挟むように、前記第２の金球を前記ワイヤループの前記一端と前記第１の金球に向けて押し付けて、前記第１の金球、前記第２の金球、及び前記第１の金球と前記第２の金球との間に挟まれた前記ワイヤループを形成する工程と、
を有することを特徴とする半導体装置の製造方法。 One end of a wire is bonded to the electrode pad formed on the surface of the semiconductor chip by a first gold ball, and the other end of the wire is bonded to the external electrode formed apart from the electrode pad. Bonding and forming a wire loop from the electrode pad to the external electrode;
The second gold sphere formed at the tip of the capillary is positioned so that the center position of the second gold sphere is closer to the external electrode than the center position of the first gold sphere that bonds the one end of the wire loop. The second gold ball is placed between the one end of the wire loop and the first gold ball so that the wire loop is sandwiched between the gold ball and the first gold ball that bonds the one end of the wire loop. Forming the first gold ball, the second gold ball, and the wire loop sandwiched between the first gold ball and the second gold ball by pressing toward the ball; ,
A method for manufacturing a semiconductor device, comprising: 前記電極パッドの表面から前記第２の金球の頂部の高さは、前記電極パッドの表面と同一平面上から前記ワイヤループの最上部までの高さよりも高いことを特徴とする請求項１に記載の半導体装置の製造方法。   The height of the top of the second gold sphere from the surface of the electrode pad is higher than the height from the same plane as the surface of the electrode pad to the top of the wire loop. The manufacturing method of the semiconductor device of description. 前記電極パッドと前記外部電極との間に位置する前記半導体チップの表面上には、絶縁膜が形成されていることを特徴とする請求項１又は２に記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein an insulating film is formed on a surface of the semiconductor chip located between the electrode pad and the external electrode.
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