JP5779931B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5779931B2 JP5779931B2 JP2011066475A JP2011066475A JP5779931B2 JP 5779931 B2 JP5779931 B2 JP 5779931B2 JP 2011066475 A JP2011066475 A JP 2011066475A JP 2011066475 A JP2011066475 A JP 2011066475A JP 5779931 B2 JP5779931 B2 JP 5779931B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
半導体素子に設けられた第1の電極の表面の機械加工を行って、当該機械加工前よりも粒径が小さい微結晶の第1の層を設ける工程と、
前記半導体素子が搭載される搭載部材に設けられた第2の電極の表面の機械加工を行って、当該機械加工前よりも粒径が小さい微結晶の第2の層を設ける工程と、
前記第1の電極を構成する金属が固相拡散する温度未満、かつ前記第2の電極を構成する金属が固相拡散する温度未満の温度で、前記第1の層の表面に存在する酸化膜及び前記第2の層の表面に存在する酸化膜を還元する工程と、
前記第1の層及び前記第2の層を互いに固相拡散接合する工程と、
を有することを特徴とする半導体装置の製造方法。
前記固相拡散接合の際に、前記第1の層及び前記第2の層において再結晶を生じさせることを特徴とする付記1に記載の半導体装置の製造方法。
前記第1の層と前記第2の層とを固相拡散接合する工程の前に、
前記第1の電極を構成する金属が固相拡散する温度未満、かつ前記第2の電極を構成する金属が固相拡散する温度未満の温度で、前記第1の層及び前記第2の層を互いに接触させる工程を有することを特徴とする付記1又は2に記載の半導体装置の製造方法。
前記第1の電極を構成する金属及び前記第2の電極を構成する金属は、Cu、Sn、Al又はNiを含むことを特徴とする付記1乃至3のいずれか1項に記載の半導体装置の製造方法。
前記搭載部材は、リードフレーム又は回路基板であることを特徴とする付記1乃至4のいずれか1項に記載の半導体装置の製造方法。
前記第1の層の表面に存在する酸化膜及び前記第2の層の表面に存在する酸化膜を還元する工程において、蟻酸を還元剤として用い、処理温度を100℃〜150℃とすることを特徴とする付記1乃至5のいずれか1項に記載の半導体装置の製造方法。
前記第1の層の表面に存在する酸化膜及び前記第2の層の表面に存在する酸化膜を還元する工程において、水素ラジカルを還元剤として用い、処理温度を25℃〜150℃とすることを特徴とする付記1乃至5のいずれか1項に記載の半導体装置の製造方法。
前記第1の層の表面に存在する酸化膜及び前記第2の層の表面に存在する酸化膜を還元する工程において、一酸化炭素を還元剤として用い、処理温度を50℃〜150℃とすることを特徴とする付記1乃至5のいずれか1項に記載の半導体装置の製造方法。
前記半導体素子は、高電子移動度トランジスタを含むことを特徴とする付記1乃至8のいずれか1項に記載の半導体装置の製造方法。
前記固相拡散接合を、150℃〜250℃で行うことを特徴とする付記1乃至9のいずれか1項に記載の半導体装置の製造方法。
前記固相拡散接合を、非酸化雰囲気下で行うことを特徴とする付記1乃至10のいずれか1項に記載の半導体装置の製造方法。
前記機械加工として、前記第1の電極及び前記第2の電極の表面を平坦にする加工を行うことを特徴とする付記1乃至11のいずれか1項に記載の半導体装置の製造方法。
12:電極
12a:基部
12b:微結晶層
15:ダイヤモンドバイト
30:接続材
30a:接合部
31:回路基板
32:電極
32a:基部
32b:微結晶層
41:回路基板
42:GaN系HEMT
42s:ソース接続材
42d:ドレイン接続材
42g:ゲート接続材
Claims (10)
- 半導体素子に設けられた第1の電極の表面の機械加工を行って、当該機械加工前よりも粒径が小さい微結晶の第1の層を設ける工程と、
前記半導体素子が搭載される搭載部材に設けられた第2の電極の表面の機械加工を行って、当該機械加工前よりも粒径が小さい微結晶の第2の層を設ける工程と、
前記第1の電極を構成する金属が固相拡散する温度未満、かつ前記第2の電極を構成する金属が固相拡散する温度未満の温度で、前記第1の層の表面に存在する酸化膜及び前記第2の層の表面に存在する酸化膜を還元する工程と、
前記第1の層及び前記第2の層を互いに固相拡散接合する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記固相拡散接合の際に、前記第1の層及び前記第2の層において再結晶を生じさせることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1の層と前記第2の層とを固相拡散接合する工程の前に、
前記第1の電極を構成する金属が固相拡散する温度未満、かつ前記第2の電極を構成する金属が固相拡散する温度未満の温度で、前記第1の層及び前記第2の層を互いに接触させる工程を有することを特徴とする請求項1又は2に記載の半導体装置の製造方法。 - 前記第1の電極を構成する金属及び前記第2の電極を構成する金属は、Cu、Sn、Al又はNiを含むことを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置の製造方法。
- 前記搭載部材は、リードフレーム又は回路基板であることを特徴とする請求項1乃至4のいずれか1項に記載の半導体装置の製造方法。
- 前記第1の層の表面に存在する酸化膜及び前記第2の層の表面に存在する酸化膜を還元する工程において、蟻酸を還元剤として用い、処理温度を100℃〜150℃とすることを特徴とする請求項1乃至5のいずれか1項に記載の半導体装置の製造方法。
- 前記半導体素子は、高電子移動度トランジスタを含むことを特徴とする請求項1乃至6のいずれか1項に記載の半導体装置の製造方法。
- 前記固相拡散接合を、150℃〜250℃で行うことを特徴とする請求項1乃至7のいずれか1項に記載の半導体装置の製造方法。
- 前記固相拡散接合を、非酸化雰囲気下で行うことを特徴とする請求項1乃至8のいずれか1項に記載の半導体装置の製造方法。
- 前記機械加工として、前記第1の電極及び前記第2の電極の表面を平坦にする加工を行うことを特徴とする請求項1乃至9のいずれか1項に記載の半導体装置の製造方法。
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JP6003564B2 (ja) * | 2012-11-19 | 2016-10-05 | 富士通株式会社 | 半導体装置及びその製造方法 |
EP2743972A1 (en) * | 2012-12-17 | 2014-06-18 | Imec | Method for bonding semiconductor substrates and devices obtained thereby |
EP3057123B1 (en) * | 2013-10-07 | 2021-12-08 | Furukawa Electric Co., Ltd. | Joining structure comprising layers with different average crystal grain sizes for a semiconductor chip |
JP6386746B2 (ja) * | 2014-02-26 | 2018-09-05 | 株式会社ジェイデバイス | 半導体装置 |
JP6656836B2 (ja) * | 2015-07-24 | 2020-03-04 | 新光電気工業株式会社 | 実装構造体及びその製造方法 |
JP6608640B2 (ja) * | 2015-07-28 | 2019-11-20 | 新光電気工業株式会社 | 実装構造体の製造方法 |
CN111613542A (zh) * | 2019-02-22 | 2020-09-01 | 中科院微电子研究所昆山分所 | 一种铜-铜键合的方法 |
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