JP5724394B2 - Reception circuit, transmission system, and reception method - Google Patents

Description

  The present invention relates to a receiving circuit, a transmission system, and a receiving method.

  High-speed signal transmission is performed between a plurality of circuit blocks in a chip, between LSI chips, or between a circuit board and a housing. The signal to be transmitted is serial data. On the transmission side, parallel data is converted into serial data by a multiplexer (MUX), and on the reception side, serial data is converted into parallel data by a demultiplexer (DEMUX).

  The internal circuit on the transmission side needs to operate at the same operating frequency as the baud rate frequency of the transmission data. For example, when the data rate is 10 Gbps, the internal circuit on the transmission side needs to operate at 10 GHz. However, it is difficult for the internal circuit to operate with a high-speed clock having the same speed as the transmission data, and problems such as increased power consumption occur. Therefore, generally, a lower frequency multi-phase clock is used. Multiphase clocks are clocks having the same frequency and different phases by a predetermined amount. For example, in the case of an 8-phase multiphase clock with a baud rate frequency of 10 Gbps, eight 1.25 GHz clocks are shifted by 0.1 ns. It is a clock.

  In the receiving circuit, for the same reason as that of the transmitting circuit, a multiphase clock having a frequency lower than the baud rate frequency is generally used, and the multiphase clock is input as a sampling clock to a capturing circuit including a latch circuit. In the receiving circuit, the phase interpolator (PI), duty correction circuit, etc. are used so that the phase difference between the multiphase clock and the received signal can be detected and the received signal can be captured at an appropriate timing. The phase of the multiphase clock is adjusted uniformly.

  There are a number of products from companies that have transmitter and / or receiver circuits. When performing signal transmission between such products, the characteristics of the transmission signal to be output are defined so that the reception circuit can perform correct reception. The transmission circuit of the product defines the characteristics of the transmission signal to be output, and the reception circuit of the product is required to be able to receive such a transmission signal.

  However, the number of phases of the multiphase clock is not particularly defined, and is arbitrarily set in the transmission circuit and the reception circuit. For example, the transmission circuit of a product manufactured by company A generates a transmission signal using an 8-phase multiphase clock, while the reception circuit of a product manufactured by company B uses a 4-phase multiphase clock. In some cases, the received signal is captured. The number of phases of the multi-phase clock is arbitrarily set based on the design specifications of each company that manufactures the product. In the case of a transmission circuit, the specified transmission signal characteristics are satisfied. Is required to be received.

  Since the transmission circuit uses a signal generated from the multiphase clock as the selector signal of the multiplexer (selector), for example, when a skew occurs between the multiphase clocks in the clock generation circuit, the eye pattern of the output waveform deteriorates. That is, there arises a problem that the width (opening degree) of some of the eye patterns becomes narrow. When the opening degree of the eye pattern is narrowed, the margin for adjusting the timing of the multiphase clock in the receiving circuit is reduced correspondingly, resulting in a problem that adjustment becomes difficult. The performance of the transmission / reception system is determined by the aperture of the narrowest eye pattern. This problem also occurs due to multiphase clock skew in the receiving circuit.

  As described above, the transmission circuit of the product satisfies the characteristics of the specified transmission signal, and the reception circuit of the product needs to be able to receive such a signal. Even in such a case, it is desired that transmission can be performed as stably as possible.

  As described above, when there is a skew in the multi-phase clock of the transmission circuit or the multi-phase clock of the reception circuit, it is difficult to adjust the timing of capturing the transmission signal in the reception circuit, and the transmission error rate increases. To do. With the method of uniformly adjusting the phase of the multiphase clock as described above, it is not possible to sufficiently adjust the influence of the skew of the multiphase clock of the transmission circuit. Also, if the number of phases of the multiphase clocks of the transmission circuit and the reception circuit do not match, the received signal is not an even multiple of the number of phases of the multiphase clock of the reception circuit compared to the number of phases of the multiphase clock of the transmission circuit. The effect of skew cannot be adjusted sufficiently.

Japanese Patent Laid-Open No. 11-215110 JP 2000-332736 A

H. Takauchi et al., “A CMOS Multichannel 10-Gb / s Tranceiver” IEEE J. Solid-State Circuits, vol.38, pp. 2094-2100, Dec. 2003

  According to the embodiments, a transmission system, a receiving circuit, and a receiving method with a reduced bit error rate (BER) are provided.

  According to a first aspect of the invention, a multiphase clock generation circuit capable of generating a plurality of clocks having a predetermined number of different phases and generating a multiphase clock corresponding to the number of clock phases used for reception of a predetermined number or less; An acquisition circuit that captures a received signal using a multiphase clock, a phase detection circuit that detects a phase difference between the received signal and the multiphase clock, and a multiphase clock suitable for capturing the received signal based on the detected phase difference. A receiving circuit is provided that includes an evaluation circuit that extracts a phase adjustment amount, and a phase adjustment circuit that adjusts the phase of a multiphase reception clock according to the extracted phase adjustment amount.

  According to a second aspect of the invention, there is provided a transmission system including a transmission side circuit, a transmission line, and a reception side circuit, wherein the transmission side circuit generates a plurality of transmission clocks having different phases. A clock generation circuit; a transmission phase adjustment circuit that adjusts the phases of a plurality of transmission clocks; a multiplexer that converts parallel transmission data into serial transmission data using the adjusted plurality of transmission clocks; and outputs serial transmission data And a receiving circuit that can generate a plurality of clocks having a predetermined number of different phases, and that generates a reception multiphase clock corresponding to the number of clock phases used for reception of a predetermined number or less. A clock generation circuit, a capture circuit that captures serial transmission data transmitted via a transmission line as a reception signal with a reception multiphase clock, and a reception signal and reception A phase detection circuit that detects the phase difference of the phase clock, an evaluation circuit that extracts the phase adjustment amount of the reception multiphase clock suitable for capturing the received signal based on the detected phase difference, and the extracted phase adjustment amount, A transmission circuit that transmits to the transmission side circuit via the transmission line, and the transmission phase adjustment circuit of the transmission side circuit adjusts the phase of each of the plurality of transmission clocks according to the received phase adjustment amount. A system is provided.

  According to a third aspect of the invention, a first circuit having a first transmitter and a first receiver, a second circuit having a second transmitter and a second receiver, A transmission system including a first transmission line from a transmission unit to a second reception unit and a second transmission line from the second transmission unit to the first reception unit, wherein the first and second transmission units have a phase Multi-phase clock generation circuit that generates multiple transmission clocks with different transmission phase, transmission phase adjustment circuit that adjusts the phase of each of the multiple transmission clocks, and parallel transmission data into serial transmission data using the adjusted multiple transmission clocks A multiplexer for converting and a driver for outputting serial transmission data, wherein the first and second receivers can generate a plurality of clocks having a predetermined number of phases different from each other, and are used for reception of a predetermined number or less. Receive polyphase corresponding to the number of phases Receive multi-phase clock generation circuit that generates locks, capture circuit that receives serial transmission data transmitted via the transmission line as a receive signal using the receive multi-phase clock, and phase difference between the receive signal and the receive multi-phase clock A phase detection circuit for detecting, and an evaluation circuit for extracting a phase adjustment amount of a reception multiphase clock suitable for capturing a reception signal based on the detected phase difference. At the time of initialization, the first transmission unit The second phase adjustment amount extracted by the first receiving unit is transmitted to the second receiving unit via the one transmission line, and the second transmitting unit transmits the second receiving amount to the first receiving unit via the second transmission line. The transmission phase adjustment circuit of the first transmission unit adjusts the phase of the transmission multiphase clock according to the received first phase adjustment amount, and the second transmission unit The transmission phase adjustment circuit of the received first Depending on the amount of phase adjustment, the transmission system for adjusting receive multiphase clock phase, respectively, are provided.

  According to a fourth aspect of the invention, a multiphase clock corresponding to the number of clock phases used for reception of a predetermined number or less is generated and selected from a plurality of clocks having a predetermined number of phases that can be generated. Captures the received signal using the multiphase clock, detects the phase difference between the received signal and the multiphase clock, and extracts and extracts the phase adjustment amount of the multiphase clock suitable for capturing the received signal based on the detected phase difference. A receiving method for adjusting the phase of the multiphase clock according to the phase adjustment amount is provided.

  According to the above viewpoint, when receiving using a multi-phase clock, the receiving operation can be performed with the number of phases suitable for the received signal, so that the received signal can be captured while the received signal is stable, and signal transmission is performed. Reduce bit errorator in

FIG. 1 is a diagram showing a schematic configuration of a general high-speed signal transmission system. FIG. 2 is a diagram showing the configuration of the high-speed signal transmission system of FIG. 1 in more detail. FIG. 3 is a diagram illustrating a state of skew between clocks and deterioration of an eye pattern when the number of phases of the multiphase clock of the transmission circuit is four. FIG. 4 is a diagram showing a general configuration and sampling timing of a receiving circuit having a phase adjustment function. FIG. 5 is a waveform diagram for explaining the basic configuration of the phase interpolator (PI) and the operation of the PI. FIG. 6 is a diagram illustrating an actual circuit example of the phase interpolator (PI). FIG. 7 is a diagram showing how to assign weights (offsets) in the PI of FIG. 6 and rotation of the order of the phases of the input clocks according to the weights. FIG. 8 is a diagram for explaining skew correction of a multiphase clock by correcting the duty of the clock when the data center clock has four phases. FIG. 9 is a diagram showing a configuration of a clock duty correction (DCC) circuit for correcting the duty of the clock. FIG. 10 is a diagram illustrating a configuration of a receiving circuit that has two phase interpolators (PI) and reduces waveform deterioration due to skew of a multiphase clock, and an adjustment operation. FIG. 11 is a diagram for explaining that when the number of phases of the multiphase clock in the receiving circuit is insufficient, the rise of the multiphase clock cannot be matched with the boundary. FIG. 12 is a diagram illustrating a configuration of the receiving circuit according to the first embodiment. FIG. 13 is a diagram for explaining the operation of the phase detection circuit (PD). FIG. 14 is a diagram illustrating a configuration of the evaluation circuit. FIG. 15 is a diagram illustrating an output example of the average value detector. FIG. 16 is a flowchart showing the initialization operation of the receiving circuit of the first embodiment. FIG. 17 is a diagram illustrating a configuration of a receiving circuit according to the second embodiment. FIG. 18 is a diagram illustrating a configuration of the evaluation circuit of the second embodiment. FIG. 19 is a diagram illustrating a configuration of a receiving circuit according to the third embodiment. FIG. 20 is a diagram illustrating a configuration of a receiving circuit according to the fourth embodiment. FIG. 21 is a diagram illustrating a configuration of a receiving circuit according to the fifth embodiment. FIG. 22 is a diagram for explaining the influence of the skew of the multiphase clock generated in the transmission circuit in the high-speed signal transmission system. FIG. 23 is a diagram illustrating a configuration of a high-speed signal transmission system according to the sixth embodiment. FIG. 24 is a diagram illustrating a configuration of the first transmission circuit.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. Before describing the embodiments, a configuration of a general high-speed signal transmission system applied to the embodiments will be described.

  FIG. 1 is a diagram showing a schematic configuration of a general high-speed signal transmission system.

  This system includes a transmission circuit (Tx) 10, a transmission line 18, and a reception circuit (Rx) 20. The transmission circuit 10 includes a driver 11 that outputs a transmission signal. The reception circuit 20 includes an analog equalizer (Analog Equlizer) circuit 21, a capture (Decision Latch) circuit 22, and a clock data recovery (CDR) circuit 23.

  Data transmitted from the transmission circuit 10 is input to the reception circuit 20 through the transmission line 18. Due to the frequency characteristics of the transmission line 18, the high frequency component of the transmission signal waveform is lost, and the reception waveform of the reception circuit 20 deteriorates. Examples of signal states at various parts of the system are shown on the lower side of FIG. If the deterioration is so large that data cannot be received correctly, the transmission circuit 10 or the analog equalization circuit 21 of the reception circuit 20 performs equalization processing to correct the signal waveform deterioration, and then the acquisition circuit 22 determines the data. Do. Based on the output of the acquisition circuit 2, the clock data recovery circuit 23 performs timing extraction, samples at an appropriate timing, and performs data determination. Note that when the degree of waveform deterioration due to the transmission line 18 is small, the analog equalization circuit 21 is not necessarily essential. In the following description, a case where the analog equalization circuit 21 is not provided will be described as an example.

  FIG. 2 is a diagram showing the configuration of the high-speed signal transmission system of FIG. 1 in more detail. As described above, no analog equalization circuit is provided.

  The transmission circuit 10 includes a driver 11, a multiphase clock generation circuit 12, and a multiplexer 13. The reception circuit 20 includes a multiphase clock generation circuit 24, a plurality of latch circuits 25A-25M forming a capture circuit, a demultiplexer 26, and a CDR circuit 23.

  As described above, when a multiphase clock is used, waveform deterioration due to the transmission circuit 10 may occur separately from waveform deterioration due to the transmission line 18. The reason will be described below. The internal circuit of the transmission circuit 10 is generally difficult to operate with a clock having the same speed as the transmission data (baud rate frequency, for example, 10 GHz if the data rate is 10 Gbps), and the power consumption increases. A lower frequency multi-phase clock is used. Since the signal generated from the multiphase clock is used as the selector signal of the multiplexer (selector), when there is a skew error between the multiphase clocks (for example, generated by the multiphase clock generation circuit 12), the output waveform eye pattern Deterioration occurs.

  FIG. 3 is a diagram illustrating a state of skew between clocks and deterioration of an eye pattern when the number of phases of the multiphase clock of the transmission circuit 10 is 4, that is, when CLK0 to CLK3 are used. As the selector signal of the transmission circuit 10, a signal (for example, CLK0 · / CLK1) (/ means an inverted signal) obtained by performing a logical operation on adjacent clocks is used. Therefore, in the case of an ideal clock, as shown in FIG. 3A, it is expected that the opening degree of the eye pattern, that is, the time width 1 UI of the eye pattern is equal. However, when there is a skew, as shown in FIG. Regarding the eye pattern opening degree, that is, the timing margin, the performance of the transmission / reception system is determined by the narrowest eye pattern opening degree.

  Even in the reception circuit 20, for the same reason as the transmission circuit 10, a multiphase clock having a frequency lower than the baud rate frequency is generally used, and the multiphase clock is used as a sampling clock for each of the plurality of latch circuits 25A-25M. Generally, it is input to.

  4A shows a general configuration of the receiving circuit 20 having a phase adjustment function, and FIG. 4B shows a sampling timing. In the example shown in FIG. 4, a four-phase clock is used, and the phase of the four-phase clock is shifted by π / 2, which are represented by phases 0, π / 2, π, and 3π / 2, respectively. Phase 0 and π clocks are located at the changing edge (data boundary) of the input signal (data). The clocks of phase π / 2 and 3π / 2 are located at the center (data center) of the change edge of the input data, and usually the clocks of phase π / 2 and 3π / 2 are supplied as sampling clocks.

  The reception circuit 20 includes a capture circuit 25 having four latches, a CDR circuit 23, and a phase interpolator (PI) 27. The four latch circuits are supplied with clocks having phases 0, π / 2, π, and 3π / 2 as sampling clocks. Hereinafter, a group of latches to which the data boundary clock is supplied is represented by 28A, and a group of latches to which the data center clock is supplied is represented by 28B.

  The input data is sampled by the latch circuit 25 twice in one UI. In other words, the data is sampled at the data center and the data boundary C. The output data (D and B) of the four latch circuits 25 are reduced in speed and parallelized by a demultiplexer (not shown) and output to the CDR 23. The CDR 23 detects the transition timing (boundary) of the received waveform from the data values of the data center D and the data boundary B, generates a control signal (phase adjustment code), and generates a phase interpolator (PI) 27. To supply. At this time, the values of the data center and the data boundary in the plurality of UIs are calculated as a whole, and the calculated phase output value is output to the PI 27. The PI 27 is a kind of digitally controlled delay device, and uniformly adjusts the phase of the reference clocks θ0 to θ3 supplied from the PLL or the like according to the supplied phase output value.

  5A shows the basic configuration of the phase interpolator (PI) 27, and FIG. 5B is a waveform diagram for explaining the operation of the PI 27.

  The PI 27 includes a first V-I circuit 28A, a second V-I circuit 28B, capacitors CAH, CAL, CBH, and CBL, a first weighting circuit 29A, a second weighting circuit 29B, and a comparator 30. Have. The first V-I circuit 28A converts the differential voltage between the reference clocks θ0 and θ2 into a differential current signal. The second V-I circuit 28B converts the difference voltage between the reference clocks θ1 and θ3 into a differential current signal. Capacitors CAH, CAL, CBH, and CBL operate as low-pass filters that cut high-frequency components of the differential current signals output from the first and second VI circuits 28A and 28B. The first weighting circuit 29A gives (multiplies) a weight w to the differential current signal output from the first VI circuit 28A from which the high-frequency component has been cut. The second weighting circuit 29B gives (multiplies) the weight 1-w to the differential current signal output from the second VI circuit 28B from which the high-frequency component has been cut. The differential outputs of the first weighting circuit 29A and the second weighting circuit 29B are connected, and the differential outputs are added. The comparator 30 compares the added differential outputs and binarizes them.

  In FIG. 5B, sn (t) is a voltage signal corresponding to a signal obtained by cutting the high-frequency component after converting the differential voltage between the reference clocks θ0 and θ2 into a differential current signal. Further, cs (t) is a voltage signal corresponding to a signal obtained by converting a differential voltage between the reference clocks θ1 and θ3 into a differential current signal and then cutting a high frequency component. cs (t) is a signal obtained by changing the phase of sn (t) by 90 ° (π / 2). V (t) is an addition signal of sn (t) weighted by w and cs (t) weighted by 1-w, and V (t) = w * sn (t) + (1-w) * cs (T). By changing the value of w between 1 and 0, V (t) changes between sn (t) and cs (t). That is, sn (t) when w = 1, cs (t) when w = 0, and FIG. 5 (B) shows an example of a value between w and 1 and 0. Yes. The comparator 30 binarizes the signal V (t) to obtain a rectangular waveform clock φ0 and its inverted signal φ2.

  As described above, by setting the value of w, the phase of the clock can be shifted (shifted) between 0 and π / 2.

  FIG. 6 is a diagram illustrating an actual circuit example of the phase interpolator (PI) 27. As shown in FIG. 6A, a data boundary group B clock PI 31B and a data center group D clock PI 31D are provided. PI 31B and PI 31D have the same circuit configuration, and different reference signals are input as θ0−θ3. FIG. 6B shows a circuit configuration of PI 31B and PI 31D.

  The circuit in FIG. 6B operates on the same principle as the PI described in FIG. 5, but four V-I circuits are provided, and w0, w1, w2 are output to the outputs of the four VI circuits. , W3 are weighted and then added to rotate the phase order of the input clock.

  In FIG. 6B, reference numerals 32A to 32D correspond to the VI conversion circuit, 33 corresponds to the capacitor forming the low-pass filter, 36A to 36D correspond to the weighting circuit, and 34 represents the comparator. Correspondingly, 35A to 35D indicate a current DAC for converting the phase adjustment code into a current signal. Since PI and each circuit element are widely known, detailed description is omitted.

  FIG. 7 is a diagram showing how to assign weights (offsets) in the PI of FIG. 6 and rotation of the order of the phases of the input clocks according to the weights.

  The voltage V (t) generated at the input of the comparator 34 is represented by V (t) = (w0−w1) sn + (w2−w3) cn as shown in FIG. FIG. 7B shows changes in the rotation angle θ with respect to w0, w1, w2, and w3. The lower side shows (w0-w1) sn and the upper side shows (w2-w3) cn. To change θ between 0 and π / 2, w0 is decreased from 1 to 0, w2 is increased from 0 to 1, and w1 and w3 are maintained at 0. To change θ between π / 2 and π, w1 is increased from 0 to 1, w2 is decreased from 1 to 0, and w0 and w3 are maintained at 0. To change θ between π and 3π / 2, increase w3 from 0 to 1, decrease w1 from 1 to 0, and maintain w0 and w2 at 0. To change θ between 3π / 2 and 2π, increase w0 from 0 to 1, decrease w3 from 1 to 0, and maintain w1 and w2 at 0.

  (C) of FIG. 7 is a figure which shows the relationship between the code | symbol of (w0-w1) and (w2-w3), and rotation angle (theta). As shown in FIG. 7B, when θ is between 0 and π / 2, w0> w1 and w2> w3, (w0−w1) is positive (+), and (w2−w3) is positive. (+), Which matches sn = + and cn = + in the first quadrant of FIG.

  As described above, the phase of the clock can be changed by using the phase interpolator (PI).

  In general, when multiphase clocks are used in the transmission circuit 10 and the reception circuit, it is assumed that the phase difference between the multiphase clocks is accurate. Therefore, in the receiving circuit, a method of uniformly adjusting the phase of the multiphase reference clock (θ0−θ3) using a phase adjusting mechanism such as PI has been performed. However, actually, skew also occurs between the clocks of the multiphase clock.

  Until now, waveform deterioration due to skew of the multiphase clock has been reduced by a method of correcting the duty of the clock or a method of using PI in two stages.

  FIG. 8 is a diagram for explaining multi-phase clock skew correction by correcting the clock duty when the data center clock has four phases. FIG. 8A shows the received signal (data) and FIG. ) Indicates a multiphase clock. As described above, since the boundary clock has four phases, the number of phases of the multi-layer clock is eight.

  Consider a case where a skew occurs in the multiphase clock in the transmission circuit and the boundary of the received signal changes as shown in FIG. In FIG. 8, the broken line indicates an ideal case where there is no skew in the multiphase clock, and the solid line indicates a case where skew occurs. When the multiphase clock is not adjusted, as shown in FIG. 8B, the received signal is captured at the position of the broken arrow. There is no problem with the widened eye pattern, but it is predicted that when the received signal is captured at the position of the dashed arrow, correct capture cannot be performed for the second narrowed eye pattern.

  Therefore, the duty of the “high (H)” portions of φ0 and φ1 of the multiphase clock is increased so that the received signal is captured at the solid arrow position. Due to this duty correction, the reception timing of the reception signal is near the center of the narrow eye pattern, so that the occurrence of reception errors can be reduced. If φ2 and φ3 are inverted signals of φ0 and φ1, the duty of the “high (H)” portion is reduced.

  FIG. 9 is a diagram showing the configuration of a clock duty correction (DCC) circuit that corrects the clock duty. FIG. 9A is an overall configuration, and FIG. 9B is a circuit diagram of an offset adjustment circuit. Show. As shown in FIG. 9A, the DCC circuit includes an offset adjustment circuit 37 and a DAC 38. By applying the voltage signal generated by the DAC 38 in accordance with the phase adjustment data to the VOS and / VOS terminals of the offset adjustment circuit 37, the clock duty can be adjusted, thereby effectively correcting the skew of the differential clock. Since the configuration of the offset adjustment circuit is known, detailed description is omitted.

  FIG. 10 is a diagram illustrating a configuration of a receiving circuit that has two phase interpolators (PI) and reduces waveform deterioration due to skew of a multiphase clock, and an adjustment operation.

  The receiving circuit 20 includes a PLL 41, a first phase interpolator (PI) 42, a pair of second phase interpolators (PI) 43B and 43D, and a plurality of latch circuits forming an acquisition circuit. 25A-25M, a demultiplexer (DEMUX) 26, and a CDR circuit 23. The CDR circuit 23 includes a plurality of phase detection circuits 44A to 44N, an addition circuit 45, a phase difference calculation circuit 46, and a selection circuit (Sel) 47. The plurality of phase detection circuits 44 </ b> A to 44 </ b> N detect a phase shift of each reception data (eye pattern) from the parallel reception data output from the DEMUX 26. The adder circuit 45 outputs the result of adding the outputs of the plurality of phase detection circuits 44A-44P for a predetermined period. The phase difference calculation circuit 46 detects the phase difference from the result output from the addition circuit 45.

  The PLL 41 generates multiphase clocks In0-In3 from a reference clock Ref.Clk supplied from the outside of the receiving circuit. Here, it is assumed that the generated multiphase clocks In0-In3 are 90 ° (π / 2) out of phase as shown in FIG. The first PI 42 adjusts so that one output set Out0 and Out2 has an intermediate phase between In0 and In1, and In2 and In3. Then, the second PI 43B or 43D adjusts so that the other output set Out1 and Out3 has an intermediate phase between In1 and In2, and In3 and In0. As described above, according to the circuit configuration of FIG. 10, the skew of the differential clock can be effectively corrected. Since the circuit configuration of FIG. 10 is known, detailed description thereof is omitted.

  Since both the method for correcting the duty of the clock and the method using PI in two stages are feedforward timing corrections, a large bit error rate improvement cannot be realized.

  Although the transmission system using the multiphase clock has been described above, as described above, the number of phases of the multiphase clock of the transmission circuit and the number of phases of the multiphase clock of the reception circuit are arbitrarily set. Therefore, there may occur a case where the number of phases of the multiphase clock of the transmission circuit is different from the number of phases of the multiphase clock of the reception circuit. When the number of phases of the multiphase clock for boundary detection of the receiving circuit is not an integer multiple of the number of phases of the multiphase clock of the transmitting circuit, it rises at the waveform transition time (eye pattern edge) of the received signal It is not possible to generate a multi-phase clock having

  FIG. 11 is a diagram for explaining that the rise of the multiphase clock cannot be matched with the boundary when the relationship is not as described above. FIG. 11 shows a case where the number of phases of the clock of the transmission circuit is 4, whereas FIG. 11A shows a case where the number of phases of the boundary detection clock of the reception circuit is 2.

  Assume that the multiphase clock of the transmission circuit is shifted and the received signal has an eye pattern as shown in the figure. It is assumed that a shift occurs between multiphase clocks whose phases are shifted by π in the receiving circuit. When the number of phases of the clock for detecting the boundary of the receiving circuit is 2, it is impossible to match the rising time of all clocks with the transition time of the received waveform. When a random shift occurs in the multiphase clock of the transmission circuit, the same eye pattern is repeated with four phases as one period in the received signal, but the edge (boundary) of the eye pattern within one period is not a constant interval. Since the multi-phase clock of the receiving circuit has two phases, even if adjustment is made so as to match the first two-phase boundary within one period of the reception signal, the same adjustment amount is repeated for the remaining two phases. The rising edge of the clock does not coincide with the eye pattern boundary. The same applies to the case where the number of phases of the clock of the transmitting circuit is 8 and the number of phases of the clock for detecting the boundary of the receiving circuit is 2 or 4. The same applies to the case where the number of phases of the clock of the transmission circuit is 8 and the number of phases of the boundary detection clock of the reception circuit is 3 or 6, and conversely, the number of phases of the clock of the transmission circuit is 3 or 6. The same applies to the case where the number of phases of the boundary detection clock of the receiving circuit is 4 or 8.

  In such a case, the phase adjustment code output from the CDR 23 has a temporal variation due to the temporal fluctuation of the data transition, and therefore the temporal variation also occurs in the phase adjustment code of the data center. Will occur. This means that jitter is added to the sampling clock of the data center, which causes deterioration of the bit error rate.

  When the number of phases of the multi-phase clock for detecting the boundary of the receiving circuit is an integer multiple of the number of phases of the multi-phase clock of the transmitting circuit, all the multi-phase clock rising and receiving are received in the receiving circuit. It is possible to adjust the waveform transition time. However, for this purpose, it is necessary that all multiphase clocks can be adjusted independently in the receiving circuit.

  For example, as shown in FIG. 11B, consider a case where the number of phases of the clock for detecting the boundary of the receiving circuit is 4 while the number of phases of the clock for the transmitting circuit is 4. In this case, the rising edge of the clock can be matched with all the boundaries of the received signal.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 12 is a diagram illustrating a configuration of the receiving circuit according to the first embodiment. The receiving circuit of the first embodiment is used as the receiving circuit 20 of the high-speed signal transmission system shown in FIG. 2, the transmitting circuit converts parallel data into serial data with a multi-phase clock, and transmits the data. Operates without receiving data regarding the number of phases of the phase clock.

  The receiving circuit of the first embodiment includes a PLL circuit 41, a multiphase clock generation circuit 51, two phase interpolators (PI) 52B and 52D, a skew adjustment circuit 53, and two sets of latch circuit groups 25B. 25D, a demultiplexer (DEMUX) 54, a clock data recovery circuit 23, an evaluation circuit 56, and a multiplier 57.

  The PLL circuit 41 generates an internal clock that is the basis of the receiving operation from the reference clock Ref. CLK. The reference clock Ref. CLK uses a clock generated by a crystal oscillator or the like. Here, it is assumed that the internal clock has a period tp that is ½ of the average value of the eye pattern width of the received signal.

  The multiphase clock generation circuit 51 generates 2N multiphase clocks (reception clocks) whose phases are shifted from the internal clock generated by the PLL circuit 41 by the period tp of the internal clock. Therefore, the multiphase clock is a group of clocks whose phase is shifted by tp with 2N × tp as one cycle. The number of phases 2N of the multiphase clock is supplied to the multiphase clock generation circuit 51 by multiplying the number N of phases evaluated by the evaluation circuit 56 by a multiplier 57.

  The multiphase clocks are divided into two groups every other one, and one group is a boundary multiphase clock B and the other group is a data center multiphase clock D. Therefore, ideally, the boundary multiphase clock B is N clocks whose phases are shifted by 2 tp, and the data center multiphase clock D is N clocks obtained by shifting each clock of the boundary multiphase clock B by tp. It is a clock.

  The PI 52B uniformly adjusts the phase so that the N clocks of the boundary multiphase clock B are synchronized with the received signal. The PI 52D uniformly adjusts the phase so that the N clocks of the data center multiphase clock D are synchronized with the received signal. The PI 52B and the PI 52D are realized by the PI described with reference to FIGS. Although not shown, PI 52B and PI 52D may perform phase adjustment using one output of phase detection circuit PD included in clock data recovery circuit 23.

  The skew adjustment circuit 53 independently determines the phases of 2N multiphase clocks included in the boundary multiphase clock B and the data center multiphase clock D in accordance with the phase errors of the multiphase clocks output from the evaluation circuit 56. Adjust to. The skew adjustment circuit 53 can adjust the phase of a predetermined number M (M ≧ 2N) of multiphase clocks, but only the number 2N corresponding to the number N of phases evaluated by the evaluation circuit 56 is operated. The rest has a function of stopping operation and reducing power consumption.

  Each of the latch circuit groups 25B and 25D has M / 2 latch circuits, and forms a capture circuit that captures the reception signal Data In. Each latch circuit of the latch circuit group 25B latches the received signal in accordance with each multiphase clock of the boundary multiphase clock B, and outputs M / 2 pieces of latch data Bi (i = 0 to M / 2-1). To do. Each latch circuit of the latch circuit group 25D latches the reception signal in accordance with each multiphase clock of the data center multiphase clock D, and receives M / 2 pieces of latch data Di (i = 0 to M / 2-1). Output. Each of the latch circuit groups 25B and 25D has a function of operating only N out of M / 2 and stopping the operation of the rest to reduce power consumption.

  The DEMUX 54 converts the data output from the latch circuit groups 25B and 25D into parallel data. The DEMUX 54 can generate parallel data of maximum M bits, but performs an operation of generating 2N bits of parallel data corresponding to the number N of phases output from the evaluation circuit. The DEMUX 54 can generate M + 1-bit parallel data by adding the last bit of the previous parallel data (output of the latch circuit group 25D) to the first bit of the next parallel data. Similarly, when generating 2N-bit parallel data, the DEMUX 54 can generate 2N + 1-bit parallel data by adding the last bit of the immediately preceding parallel data to the first bit of the next parallel data.

  The CDR circuit 23 includes a plurality of phase detection circuits (PD) 44A to 44P, an addition circuit 45, a phase difference calculation circuit 46, and a selection circuit (Sel) 47. Here, P = M / 2. The plurality of PDs 44 </ b> A- 44 </ b> P detect the phase shift of each received data (eye pattern) from the parallel data output from the DEMUX 26. The adder circuit 45 outputs the result of adding the outputs of the plurality of PDs 44A-44P for a predetermined period. The phase difference calculation circuit 46 detects the phase difference from the result output from the addition circuit 45. The selection circuit (Sel) 47 selects data to be output as output data Data Out from the parallel data.

  The plurality of PDs 44 </ b> A- 44 </ b> P have the same configuration and can be configured by a general phase detection circuit.

  FIG. 13 is a diagram for explaining the operation of the phase detection circuit (PD). FIG. 13 shows a case where the sampling clock is the boundary frequency of the input signal (data). For example, this is a case of 10 GHz sampling clock (including H state and L state) for 10 Gbps data. The PD is based on the data Di-1 and Di sampled near the eye center of the input data and the data Bi sampled at the transition time (boundary) of the input data between them, and the phase of the sampling clock is relative to the phase of the input data. The judgment value “CODE” indicating whether it is early or late is output. The determination rule is shown in the table of FIG. For example, in the case of FIG. 13A, Di-1 = 0, Bi = 1, Di = 1 or Di-1 = 1, Bi = 0, Di = 0, so CODE = -1.

  Here, the output of the PD is ternary (-1 / 0 / + 1 output), but a binary code may be generated in order to avoid an increase in circuit scale.

  The phase detection circuits 44A-44P perform the operations as described above. The phase detection circuits 44A-44P output M + 1 bit parallel data output from the DEMUX 54, that is, M / 2 bit data Bi (i = 0 to M / 2-1) and data Di (i = 0) on both sides of each Bi. CODE is calculated and output from ~ M / 2). M / 2 phase detection circuits 44A-44P are provided as described above. When the number N of phases is determined by the evaluation circuit 56, the DEMUS 54 outputs N-bit parallel data. Accordingly, it is desirable that only N units are operated and the rest are stopped in order to reduce power consumption.

  The adder circuit 45 outputs the result of adding the outputs of the plurality of phase detection circuits 44A-44P for a predetermined period. The phase difference calculation circuit 46 detects the phase difference from the result output from the adder circuit 45 and outputs it to the PIs 52B and 52D.

  The evaluation circuit 56 determines the optimum number of phases for reproducing the input signal (data) in the receiving circuit from the data (CODE) related to the phase difference detected by the phase detection circuits 44A-44P, and the data center multiphase clock D. Calculates and outputs the phase adjustment amount necessary for positioning at the center of the eye pattern.

  FIG. 14 is a diagram illustrating a configuration of the evaluation circuit 56.

  The evaluation circuit 56 integrates data relating to the phase difference detected by the phase detection circuits 44A-44P for a predetermined period, and an average value detector 62A for detecting an average value of the integrators 61A-61P for a predetermined period. -62P and an arithmetic circuit 63. The arithmetic circuit 63 includes a period detector 64 for detecting the period of eye pattern distortion, that is, the number N of phases of the multiphase clock in the received signal (data), from the outputs of the average detectors 62A-62P, and an average detector 62A-. And an intensity detector 65 for detecting the output intensity of 62P. The period detection unit 64 outputs the number N of phases to the multiplication circuit 57, the skew adjustment circuit 53, the latch circuit groups 25B and 25D, the DEMUX 54, and the like.

  FIG. 15 is a diagram illustrating an output example of the average value detectors 62A to 62P. In pattern 1, since the output of the average value detector repeats changes of 1 and −1 and the number of repetitions is 2, it can be seen that the number of phases of the multiphase clock in the transmission circuit is 2. In pattern 2, the output of the average value detector repeats changes of 1, 2, -3, 0, and the number of repetitions is 4. Therefore, the number of phases of the multiphase clock in the transmission circuit may be 4. I understand. In this way, the evaluation circuit 56 detects the eye pattern distortion period, that is, the number N of phases of the multiphase clock in the received signal (data).

  Further, the evaluation circuit 56 detects the output intensity of the average value detectors 62A to 62P, positions the data center multiphase clock D at the center of each eye pattern, and sets the boundary multiphase clock B to the waveform transition time of the received signal. Is fed back to the skew adjustment circuit 53 as a phase adjustment amount necessary for positioning at the position. The skew adjustment circuit 53 shifts each of the data center multiphase clock D and the boundary multiphase clock B by the fed back phase adjustment amount, and thereafter maintains the shift amount.

  The integration period of integrators 61A-61P and the average value calculation period of average value detectors 62A-62P in evaluation circuit 56 are sufficiently long because the purpose of the evaluation circuit is to detect a direct current (DC) phase shift. What is necessary is just a time interval. If it is too short, an error occurs due to the influence of high frequency noise superimposed on the phase of the input data or the phase of the sampling clock. When the circuit size is increased by a frequency divider or the like in a circuit for generating a reset signal having a long period, the period may be set to a period corresponding to the feedback loop band of the CDR 23.

  FIG. 16 is a flowchart showing the initialization operation of the receiving circuit of the first embodiment. After completing the initialization operation of the receiving circuit of the first embodiment, it enters a normal operation state.

  In step S1, the operation of the receiving circuit is started. In accordance with this, it is desirable that the transmission circuit forming the transmission system outputs a signal suitable for initialization of the reception circuit.

  In step S2, the CDR is initialized.

  In step S3, the evaluation circuit 56 calculates the number N of phases of the multiphase clock suitable for the reproduction of the received signal (data), and outputs it to the multiplication circuit 57, the skew adjustment circuit 53, the latch circuit groups 25B and 25D, the DEMUX 54, and the like. To do.

  In step S4, the multiplier circuit 57, the skew adjustment circuit 53, the latch circuit groups 25B and 25D, the DEMUX 54, and the like make settings according to the notified number of phases N.

  In step S <b> 5, the evaluation circuit 56 calculates each phase difference of the multiphase clock and outputs the calculation result to the skew adjustment circuit 53.

  In step S6, the skew adjustment circuit 53 adjusts each of the multiphase clocks so as to shift by the instructed phase amount.

  Steps S5 and S6 may be repeated until the respective phase differences of the multiphase clocks are equal to or less than a predetermined threshold.

  As described above, in the receiving circuit of the first embodiment, the number of phases of the multiphase clock of the receiving circuit is used to cope with the deterioration of the eye pattern due to the timing error (skew) of the multiphase clock of the transmitting circuit and the receiving circuit. Is optimized for the number of phases of the multiphase clock of the transmission circuit. Therefore, the reception circuit detects the number of phases of the reception signal from the repetition of the eye pattern error in the reception signal, and matches the number of clock phases of the reception circuit with the number of clock phases of the transmission circuit or the number of clock phases of the transmission circuit. Set to an even multiple. Then, the receiving circuit adjusts the data center multiphase clock so that it is positioned at the center of each eye pattern, and the boundary multiphase clock is positioned at the transition time of the waveform of the received signal.

  FIG. 17 is a diagram illustrating a configuration of a receiving circuit according to the second embodiment. The receiving circuit of the second embodiment is also used as the receiving circuit 20 of the high-speed signal transmission system, the transmitting circuit converts parallel data into serial data with a multiphase clock and transmits the data, and the receiving circuit has the number of phases of the multiphase clock. Operates without receiving data about.

  As shown in FIG. 17, the receiving circuit of the second embodiment has a configuration similar to that of the receiving circuit of the first embodiment, and sets the number of phases of the multiphase clock and the phase of the multiphase clock having the set number of phases. Adjustment is different from the first embodiment.

  In the first embodiment, the evaluation circuit 56 determines the number of phases of the multiphase clock from the received signal. In the second embodiment, the number of phases is changed while changing the number of phases of the multiphase clock. Adjustment by the skew adjustment circuit 53 is performed to determine whether the phase error (relative phase) is less than or equal to an allowable value. For the change of the number of phases of the multiphase clock, all the number of phases are tried, and if a relative phase error less than the allowable value is obtained, the number of clock phases is set. As shown in FIG. 17, a switching signal for selecting whether or not the above-mentioned calculation is performed in the evaluation circuit 56 and an allowable (relative phase) threshold value are given to the evaluation circuit 56 from the outside.

  FIG. 18 is a diagram illustrating a configuration of the evaluation circuit 56 of the second embodiment.

  The evaluation circuit 56 of the second embodiment has a configuration similar to that of the evaluation circuit of the first embodiment shown in FIG. 14, but further includes a selector 66, a control unit 67, a maximum value detection circuit 68, and a table data memory 69. It is different.

  The maximum value detection circuit 68 detects the maximum value of the outputs of the average value detectors 62A-62P. The table data memory 69 sequentially stores the maximum value detected by the maximum value detection circuit 68 when the number of phases is set in correspondence with the number of phases. The control unit 67 detects the smallest value stored in the table data memory 69 and sends the corresponding number of phases to the selector 66. The selector 66 selects and outputs the number of phases determined in this way when the switching signal indicates a calculation, and outputs the same number of phases as in the first embodiment otherwise.

  Note that the number of phases may be adopted when a number of phases below the allowable threshold is found during the search for the number of phases as a whole. In this case, the table data memory 69 is not necessary. In addition, in the method for finding the minimum value, it is not necessary to set an allowable threshold value.

  FIG. 19 is a diagram illustrating a configuration of a receiving circuit according to the third embodiment. The receiving circuit of the third embodiment is also used as the receiving circuit 20 of the high-speed signal transmission system, and the transmitting circuit converts parallel data into serial data and transmits it with a multiphase clock. The number of phases of the multiphase clock of the transmission circuit 10 is known, and the reception circuit receives data related to the number of phases of the multiphase clock from the outside.

  The skew adjustment circuit 53, the latch circuit groups 25B and 25D, and the DEMUX 54 can be operated with a multiphase clock equal to or greater than the number of phases designated from the outside, and each is set in a state corresponding to the designated number of phases. Other parts operate in the same manner as in the first embodiment.

  FIG. 20 is a diagram illustrating a configuration of a receiving circuit according to the fourth embodiment. The receiving circuit of the fourth embodiment is also used as the receiving circuit 20 of the high-speed signal transmission system, and the transmitting circuit converts parallel data into serial data and transmits it with a multiphase clock. The receiving circuit of the fourth embodiment includes a PLL circuit 41, a frequency dividing circuit 72, two phase interpolators (PI) 52B and 52D, two sets of latch circuit groups 25B and 25D, a demultiplexer (DEMUX). ) 54, a clock data recovery circuit 23, an evaluation circuit 56, and a subtractor 71.

  The number of phases of the multi-phase clock of the transmission circuit 10 is known, and the number of phases is one or two. On the other hand, the latch circuit groups 25B and 25D and the DEMUX 54 are more than the number of phases designated from the outside. It is possible to operate with.

  Here, the reception circuit 10 is instructed from the outside to operate with a multi-phase clock having the number of phases = 4. Thus, the PI 52B and 52D can perform the role without providing a skew adjustment circuit. The subtracter 71 subtracts the output of the evaluation circuit 56 from the output of the DF 23 and supplies the result to the PI 52B. On the other hand, the output of the DF 23 is supplied to the PI 52D. Thereby, the PI 52B is adjusted to coincide with the eye pattern transition time (change edge). In the fourth embodiment, since the oscillation frequency of the PLL 41 is higher than the clock frequency of the received signal (eye pattern change frequency), the divider circuit 72 can generate the boundary multiphase clock and the data center multiphase clock. It is. In this case, the oscillation frequency Fpll, the frequency division ratio Ndiv, and the reception clock frequency Frx of the PLL 41 need to satisfy the following relationship.

Fpll = Frx × Ndiv
If the oscillation frequency of the PLL 41 is lower than the reception clock frequency, a multiplier is provided in place of the frequency dividing circuit 72 to multiply the oscillation frequency of the PLL 41 and then supply it to the PIs 52B and 52D.

  FIG. 21 is a diagram illustrating a configuration of a receiving circuit according to the fifth embodiment. The receiving circuit of the fifth embodiment is also used as the receiving circuit 20 of the high-speed signal transmission system, and the transmitting circuit converts parallel data into serial data and transmits it with a multiphase clock. The receiving circuit of the fifth embodiment includes a PLL circuit 41, a frequency dividing circuit 72, two phase interpolators (PI) 52B and 52D, a duty adjustment (DCC) circuit 75, and two sets of latch circuit groups. 25B and 25D, a demultiplexer (DEMUX) 54, a clock data recovery circuit 23, an evaluation circuit 56, and an inverter 76.

  The fifth embodiment is applied when it is known that the number of phases of the multiphase clock of the transmission circuit 10 is one. The latch circuit groups 25B and 25D and the DEMUX 54 can be operated with a multi-phase clock that is equal to or more than the number of phases designated from the outside.

  Here, the reception circuit 10 is instructed from the outside to operate with a multi-phase clock having the number of phases = 4. Thus, the DCC 75 can perform the role without providing a skew adjustment circuit. The DCC 75 adjusts the duty of the boundary clock from the PI 52B.

  FIG. 22 is a diagram for explaining the influence of the skew of the multiphase clock generated in the transmission circuit in the high-speed signal transmission system.

  Consider a case where a skew occurs in the multiphase clock in the transmission driver 11A and a phase error occurs in the output signal. The transmission signal is transmitted to the reception circuit via the transmission line 18A, but the signal reaching the reception circuit 20 is deteriorated according to the characteristics of the transmission line 18A, and distortion occurs. When there is a phase error in the transmission signal, the distortion of the signal reaching the reception circuit 20 is enlarged. The latch (slicer) circuit 22B of the reception circuit 20 captures the transmitted signal. When the transmission signal has a phase error, the phase error is generally expanded and captured. In the first to fifth embodiments described so far, the CDR and evaluation circuit 80B detects the phase error from the received signal (data) in which the phase error is enlarged, and the latch (slicer) circuit 22B detects the phase error. The sampling (sampling) timing was adjusted.

  As described above, the phase error caused by the skew of the multiphase clock generated in the transmission circuit is enlarged and transmitted to the reception circuit. The correction of a large phase error increases power consumption accordingly. Therefore, it is possible to reduce the power consumption by transmitting the phase error information detected by the receiving circuit to the transmitting circuit and correcting the phase error by the transmitting circuit. However, in order to reduce the phase distortion generated by the transmission line, it is desirable to perform correction only in the receiving circuit.

  FIG. 23 is a diagram illustrating a configuration of a high-speed signal transmission system according to the sixth embodiment. In the transmission system of the sixth embodiment, a first transmission line 18A and a second transmission line 18B are provided between a first device (chip) 1A and a second device (chip) 1B, and signals are transmitted to each other. It is a system that transmits.

  The first device 1A includes a first transmission circuit, a first reception circuit, and a memory 81A, and the second device 1B includes a second transmission circuit, a second reception circuit, And a memory 81B. The first receiving circuit includes a latch (slicer) circuit 22A and a CDR and evaluation circuit 80A. The second receiving circuit includes a latch (slicer) circuit 22B and a CDR and evaluation circuit 80B. The transmission signal from the first transmission circuit is transmitted to the second reception circuit via the first transmission line 18A, and the transmission signal from the second transmission circuit is transmitted to the first transmission line 18B via the first transmission line 18B. It is transmitted to the receiving circuit.

  In the sixth embodiment, the first and second receiving circuits can have the configuration described in the first to fifth embodiments, and information such as the number of phases and the phase adjustment amount calculated by the evaluation circuit 56 can be obtained. The data is stored in the memories 81A and 81B.

  FIG. 24 is a diagram showing the configuration of the first transmission circuit, and the second transmission circuit has the same configuration. The first transmission circuit includes a multiphase clock generation circuit 12A, a skew adjustment circuit 83A, a multiplexer (MUX) 12A, and a driver 11A. Since these elements are similar to a transmission circuit using a general multiphase clock, description thereof is omitted. As described above, the memory 81A stores information such as the number of phases and the phase adjustment amount calculated by the first receiving circuit, and also detects the phase detected on the opposite side transmitted from the opposite side (second device 1B). The number and phase adjustment amount are stored. The number of phases and the amount of phase adjustment detected on the opposite side stored in the memory 81A are supplied to the skew adjustment circuit 83A, and after confirming whether the number of phases of the multiphase clock matches, the skew adjustment circuit 83A Used to adjust the phase of each clock.

  During the initial sequence, the transmission circuits 1A and 1B of the respective devices 1A and 1B transmit test patterns, and the respective reception circuits detect transmission data timing and reception timing deviation information in the respective transmission systems, and the memories 81A and 81B. To remember. Next, the data stored in the memories 81A and 81B are transmitted to the opposite side using the respective transmission systems, and are corrected during actual operation.

  In the sixth embodiment, only two pairs of transmission / reception circuits adjacent to each other are described. However, even when there are a plurality of pairs, correction can be performed by applying the same configuration. Furthermore, although the case where correction data is directly exchanged between the first apparatus and the second apparatus has been described, the correction data can also be exchanged via another apparatus.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Hereinafter, the following additional notes will be disclosed with respect to the embodiment.
(Appendix 1)
A multi-phase clock generation circuit capable of generating a plurality of clocks having a predetermined number of different phases and generating a multi-phase clock corresponding to the number of clock phases used for reception of the predetermined number or less;
A capture circuit that captures a received signal with the multiphase clock;
A phase detection circuit for detecting a phase difference between the received signal and the multiphase clock;
An evaluation circuit that extracts a phase adjustment amount of the multiphase clock suitable for capturing the received signal based on the detected phase difference;
A reception circuit comprising: a phase adjustment circuit that adjusts a phase of the multiphase reception clock according to the extracted phase adjustment amount.
(Appendix 2)
The receiving circuit according to claim 1, wherein the multiphase clock generation circuit generates the multiphase clock according to the number of clock phases input from the outside.
(Appendix 3)
The evaluation circuit determines a clock phase number suitable for capturing the reception signal based on the phase difference between the reception signal detected by the phase detection circuit and the multiphase clock, and determines the determined clock phase number. The receiving circuit according to appendix 1, which is output to the multiphase clock generating circuit.
(Appendix 4)
The phase detection circuit includes a plurality of phase detectors corresponding to the number of phases of the plurality of clocks having different predetermined numbers that can be generated by the multiphase clock generation circuit,
The receiving circuit according to supplementary note 3, wherein the evaluation circuit detects periodicity of each of the received signals with respect to each clock from detection results of the plurality of phase detectors.
(Appendix 5)
The plurality of phase detectors detect an error between the received signal and each of the plurality of clocks having different phases.
The receiving circuit according to claim 4, wherein the evaluation circuit detects a group in which a phase difference detected by the plurality of phase detectors is equal to or less than a predetermined value, and calculates the periodicity from the number of elements included in the detected group.
(Appendix 6)
The capture circuit is:
A plurality of latch circuits for capturing the received signals in response to the plurality of clocks;
A demultiplexer that converts the outputs of the plurality of latch circuits into parallel data, and
The plurality of latch circuits and the plurality of phase detectors change the number of operating according to the number of clock phases used for reception,
The receiving circuit according to appendix 4, wherein the demultiplexer changes the number of stages according to the number of clock phases used for reception.
(Appendix 7)
A transmission system comprising a transmission side circuit, a transmission line, and a reception side circuit,
The transmitting circuit is
A transmission multiphase clock generation circuit for generating a plurality of transmission clocks having different phases;
A transmission phase adjustment circuit for adjusting the phase of each of the plurality of transmission clocks;
A multiplexer for converting parallel transmission data into serial transmission data with the adjusted plurality of transmission clocks;
A driver for outputting the serial transmission data,
The receiving circuit is
A reception multiphase clock generation circuit capable of generating a plurality of clocks having a predetermined number of different phases and generating a reception multiphase clock corresponding to the number of clock phases used for reception of the predetermined number or less;
A capture circuit that captures the serial transmission data transmitted through the transmission line as a reception signal with the reception multiphase clock; and
A phase detection circuit for detecting a phase difference between the received signal and the received multiphase clock;
An evaluation circuit that extracts a phase adjustment amount of the reception multiphase clock suitable for capturing the reception signal based on the detected phase difference;
A transmission circuit that transmits the extracted phase adjustment amount to the transmission side circuit via the transmission line; and
The transmission phase adjustment circuit of the transmission side circuit adjusts the phases of the plurality of transmission clocks according to the received phase adjustment amount, respectively.
(Appendix 8)
A first circuit comprising a first transmitter and a first receiver;
A second circuit comprising a second transmitter and a second receiver;
A first transmission line from the first transmitter to the second receiver;
A second transmission line from the second transmitter to the first receiver, and a transmission system comprising:
The first and second transmission units are
A transmission multiphase clock generation circuit for generating a plurality of transmission clocks having different phases;
A transmission phase adjustment circuit for adjusting the phase of each of the plurality of transmission clocks;
A multiplexer for converting parallel transmission data into serial transmission data with the adjusted plurality of transmission clocks;
A driver for outputting the serial transmission data,
The first and second receiving units are
A reception multiphase clock generation circuit capable of generating a plurality of clocks having a predetermined number of different phases and generating a reception multiphase clock corresponding to the number of clock phases used for reception of the predetermined number or less;
A capture circuit that captures the serial transmission data transmitted through the transmission line as a reception signal with the reception multiphase clock; and
A phase detection circuit for detecting a phase difference between the received signal and the received multiphase clock;
An evaluation circuit that extracts a phase adjustment amount of the reception multiphase clock suitable for capturing the reception signal based on the detected phase difference; and
At the time of initialization, the first transmitter transmits the second phase adjustment amount extracted by the first receiver to the second receiver via the first transmission line, and the second transmitter Transmitting the first phase adjustment amount extracted by the second receiver to the first receiver via a transmission line;
The transmission phase adjustment circuit of the first transmission unit adjusts the phase of the transmission multiphase clock according to the received first phase adjustment amount, respectively.
The transmission phase adjustment circuit of the second transmission unit adjusts the phase of the transmission multiphase clock according to the received second phase adjustment amount, respectively.
(Appendix 9)
Among a plurality of clocks having different phases that can be generated, a multi-phase clock corresponding to the number of clock phases used for reception of the predetermined number or less is generated,
Capture the received signal with the selected multi-phase clock,
Detect the phase difference between the received signal and the multi-phase clock,
Based on the detected phase difference, extract the phase adjustment amount of the multiphase clock suitable for capturing the received signal,
A receiving method, wherein the phase of the multiphase clock is adjusted according to the extracted phase adjustment amount.
(Appendix 10)
Determining the number of clock phases suitable for capturing the received signal based on the detected phase difference between the received signal and the multiphase clock; and
The receiving method according to appendix 9, wherein the multiphase clock is generated based on the determined number of clock phases.

DESCRIPTION OF SYMBOLS 10 Transmission circuit 18 Transmission line 20 Reception circuit 23 Clock data reproduction circuit (CDR)
25B, 25D Latch circuit group (take-in circuit)
41 PLL
44A-44P Phase detection circuit 51 Multiphase clock generation circuit 52B, 52D Interpolator (PI)
53 Skew adjustment circuit 54 Demultiplexer (DEMUX)
56 Evaluation circuit

Claims (4)

A multi-phase clock generation circuit capable of generating a plurality of clocks having a predetermined number of different phases and generating a multi-phase clock corresponding to the number of clock phases used for reception of the predetermined number or less;
A capture circuit that captures a received signal with the multiphase clock;
A phase detection circuit for detecting a phase difference between the received signal and the multiphase clock;
An evaluation circuit that extracts a phase adjustment amount of the multiphase clock suitable for capturing the received signal based on the detected phase difference;
A phase adjustment circuit that adjusts the phase of the multiphase reception clock according to the extracted phase adjustment amount ;
The evaluation circuit determines a clock phase number suitable for capturing the reception signal based on the phase difference between the reception signal detected by the phase detection circuit and the multiphase reception clock, and determines the determined clock phase number Is output to the multiphase clock generation circuit. A transmission system comprising a transmission side circuit, a transmission line, and a reception side circuit,
The transmitting circuit is
A transmission multiphase clock generation circuit for generating a plurality of transmission clocks having different phases;
A transmission phase adjustment circuit for adjusting the phase of each of the plurality of transmission clocks;
A multiplexer for converting parallel transmission data into serial transmission data with the adjusted plurality of transmission clocks;
A driver for outputting the serial transmission data,
The receiving circuit is
A reception multiphase clock generation circuit capable of generating a plurality of clocks having a predetermined number of different phases and generating a reception multiphase clock corresponding to the number of clock phases used for reception of the predetermined number or less;
A capture circuit that captures the serial transmission data transmitted through the transmission line as a reception signal with the reception multiphase clock; and
A phase detection circuit for detecting a phase difference between the received signal and the received multiphase clock;
An evaluation circuit that extracts a phase adjustment amount of the reception multiphase clock suitable for capturing the reception signal based on the detected phase difference;
A transmission circuit that transmits the extracted phase adjustment amount to the transmission side circuit via the transmission line; and
The transmission phase adjustment circuit of the transmission side circuit adjusts the phases of the plurality of transmission clocks according to the received phase adjustment amount, respectively. A first circuit comprising a first transmitter and a first receiver;
A second circuit comprising a second transmitter and a second receiver;
A first transmission line from the first transmitter to the second receiver;
A second transmission line from the second transmitter to the first receiver, and a transmission system comprising:
The first and second transmission units are
A transmission multiphase clock generation circuit for generating a plurality of transmission clocks having different phases;
A transmission phase adjustment circuit for adjusting the phase of each of the plurality of transmission clocks;
A multiplexer for converting parallel transmission data into serial transmission data with the adjusted plurality of transmission clocks;
A driver for outputting the serial transmission data,
The first and second receiving units are
A reception multiphase clock generation circuit capable of generating a plurality of clocks having a predetermined number of different phases and generating a reception multiphase clock corresponding to the number of clock phases used for reception of the predetermined number or less;
A capture circuit that captures the serial transmission data transmitted through the transmission line as a reception signal with the reception multiphase clock; and
A phase detection circuit for detecting a phase difference between the received signal and the received multiphase clock;
An evaluation circuit that extracts a phase adjustment amount of the reception multiphase clock suitable for capturing the reception signal based on the detected phase difference; and
At the time of initialization, the first transmitter transmits the second phase adjustment amount extracted by the first receiver to the second receiver via the first transmission line, and the second transmitter Transmitting the first phase adjustment amount extracted by the second receiver to the first receiver via a transmission line;
The transmission phase adjustment circuit of the first transmission unit adjusts the phase of the transmission multiphase clock according to the received first phase adjustment amount, respectively.
The transmission phase adjustment circuit of the second transmission unit adjusts the phase of the transmission multiphase clock according to the received second phase adjustment amount, respectively. Among a plurality of clocks having different phases that can be generated, a multi-phase clock corresponding to the number of clock phases used for reception of the predetermined number or less is generated,
Capture the received signal with the selected multi-phase clock,
Detect the phase difference between the received signal and the multi-phase clock,
Based on the detected phase difference between the received signal and the multiphase clock, determine the number of clock phases suitable for capturing the received signal;
Generating the multi-phase clock based on the determined number of clock phases;
Capture the received signal with the multi-phase clock,
Detect the phase difference between the received signal and the multi-phase clock,
Based on the detected phase difference, extract the phase adjustment amount of the multiphase clock suitable for capturing the received signal,
A receiving method, wherein the phase of the multiphase clock is adjusted according to the extracted phase adjustment amount.

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