JP5338631B2 - Signal multiplexing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal multiplexing circuit adaptively controlling a phase relationship between a data signal and a clock signal. <P>SOLUTION: This signal multiplexing circuit includes: a selector circuit 15 configured to receive a first data signal D<SB>1</SB>performing data transition synchronized with a first phase position of a first clock signal and a second data signal D<SB>2</SB>performing data transition synchronized with a second phase position shifted in phase by 180&deg; from the first phase position of the first clock signal C<SB>1</SB>to sequentially select and output the first and second data signals in response to a second clock signal C<SB>2</SB>; a phase detector 17 configured to output a phase control signal showing a phase relationship between the second clock signal and the data transition based on the first and second data signals and the first and second clock signals; and a phase interpolator 16 configured to function as a phase controller for controlling the phase relationship in response to the phase control signal. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present disclosure relates generally to electronic circuits, and more particularly to signal multiplexing circuits.

  With the recent increase in operation speed due to the miniaturization of CMOS process, the application fields of CMOS-IC are wire communication such as optical transmission system exceeding 10 Gbps, wireless communication and radar using millimeter wave band (60-100 GHz). And so on. In such a high-speed application, in the signal multiplexing circuit used in the signal transmission unit, the phase relationship between the data signal and the clock signal that are affected by process variations and fluctuations in usage environment conditions such as temperature and power supply is adaptively applied. It is desirable to be able to control.

  In the signal transmission unit, in order to serially transmit data through the transmission line, the data signal subjected to signal processing at a low speed is multiplexed. Normally, N: 1 multiplexing processing is performed by a tree structure in which a plurality of 2: 1 multiplexing circuits are connected. In the 2: 1 multiplexing circuit, two input data signals D1 and D2 are synchronized with a first clock signal by a latch circuit. At this time, the data signal D1 is synchronized with the 0 degree phase of the clock signal, and the data signal D2 is synchronized with the 180 degree phase of the first clock signal. By this synchronization operation, the data signal D1 becomes a signal having a unit length from the 0 degree phase to the 360 degree phase, and the data signal D2 becomes a signal having a unit length from the -180 degree phase to the 180 degree phase. These data signals D1 and D2 are input to the signal selector circuit, and are alternately selected and output according to HIGH and LOW of the second clock signal that is 90 degrees out of phase with the first clock signal. That is, the data signal D1 is selected from the 90 degree phase to the 270 degree phase, and the data signal D2 is selected from the -90 degree phase to the 90 degree phase. As a result, it is possible to select and output the respective data center portions of the waveforms of the data signals D1 and D2. An example of such a 2: 1 multiplexing circuit is disclosed in FIG.

  The second clock signal is a signal that is 90 degrees out of phase with respect to the data signals D1 and D2 of the signal selector circuit input portion, that is, a signal that is 90 degrees out of phase with respect to the first clock signal. It is desirable from the viewpoint of the margin of the signal switching operation. Therefore, the multiplexing circuit is designed so that these two clock signals have a phase difference of 90 degrees by delay matching of the internal circuit. However, in a miniaturized ultra-high speed CMOS process, a delay difference that cannot be ignored occurs due to relative variations in transistor thresholds. In addition, the delay difference fluctuates due to temperature and power supply fluctuations during circuit operation. Therefore, the phase relationship between the second clock signal and the two data signals will change according to the operating conditions, making it difficult to ensure sufficient quality for the multiplexed output waveform.

JP-A-11-17636 JP 2005-316879 A JP 2004-40378 A JP-A-8-79210 JP-A-9-55667 JP 2005-316879 A

  In view of the above, a signal multiplexing circuit that can adaptively control the phase relationship between the data signal and the clock signal is desired.

  The signal multiplexing circuit is 180 degrees out of phase from the first phase of the first clock signal and the first data signal that makes a data transition synchronized with the first phase of the first clock signal. A selector circuit that receives a second data signal that makes a data transition in synchronization with a second phase position, and sequentially selects and outputs the first and second data signals according to a second clock signal; A phase detector that outputs a phase control signal indicating a phase relationship between the second clock signal and the data transition based on the first and second data signals and the first and second clock signals; And a phase controller that controls the phase relationship according to the phase control signal.

  According to at least one embodiment of the present disclosure, it is possible to adaptively control the phase relationship between the data signal and the clock signal. As a result, stable signal multiplexing can be realized against process variations and temperature and power supply fluctuations during circuit operation.

It is a figure which shows an example of a structure of a signal multiplexing circuit. It is a time chart which shows an example of operation | movement of a signal multiplexing circuit. It is a figure which shows an example of a structure of a phase detector. It is a time chart which shows an example of operation | movement of a phase detector. It is a flowchart which shows the flow of the phase control by a phase detector. It is a figure which shows the input / output relationship of a code converter. It is a figure which shows typically the relationship between the upper 2 bits and lower 9 bits of a thermometer code, and a phase. It is a figure which shows an example of the circuit structure of a phase interpolation circuit. It is a figure which shows the function structure of a phase interpolation circuit. It is a figure explaining operation | movement of a phase interpolation circuit. It is a figure which shows the modification of a structure of a signal multiplexing circuit. It is a figure which shows the modification of a structure of a signal multiplexing circuit. It is a figure which shows the modification of a structure of a signal multiplexing circuit. It is a figure which shows an example of a structure of a signal transmission system.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram illustrating an example of a configuration of a signal multiplexing circuit. 1 includes a four-phase clock generation circuit 11, latch circuits (L) 12 to 14, a selector circuit (SEL) 15, a phase interpolator (PI) 16, a phase detector 17, a buffer 18, and a buffer. 19 is included. The signal multiplexing circuit described in each embodiment below including the signal multiplexing circuit of FIG. 1 may be a differential configuration circuit or a single phase configuration circuit. In the following description, the signal multiplexing circuit is assumed to have a differential configuration. However, for convenience of explanation, by focusing attention on one signal as appropriate, a single-phase configuration circuit that inputs and outputs a single-phase signal is used. The same explanation as in the case will be given. In the following description, the signal multiplexing circuit is described as being configured to multiplex two signals, but it may be configured to multiplex more signals.

The four-phase clock generation circuit 11 generates a four-phase clock signal whose phases are 0 degrees, 90 degrees, 180 degrees, and 270 degrees. A pair of clock signals with 0 ° of the clock signal and the 180 degree clock signal have opposite phases to each other, via the buffer 18 is supplied to the first latch circuit 12 to 14 as a clock signal C _1. The latch circuit 12 takes in the data signal D ₁ in synchronization with the 180 ° phase position of the _first clock signal C ₁ (the rising edge of the 180 ° clock signal). Similarly latch circuit 14 takes in the data signal D ₂ in synchronism with a first 180-degree phase positions of the clock signal C ₁ (rising edge of the 180-degree clock signal). The latch circuit 13 takes in the data signal D ₂ in synchronism with the first 0-degree phase positions of the clock signal C ₁ (rising edge of the 0 degree clock signals). Thus the selector circuit 15, the data signal D ₃ that the data transitions synchronized with the first 0-degree phase positions of the clock signals C _1, the first clock signal C ₁ of 0 degree 180 degree phase from the phase position deviation and receiving the data signal D ₄ for the synchronized data transitions to 180 ° phase position. The selector circuit 15 sequentially selects and outputs the data signal D ₃ and D ₄ in accordance with the second clock signal C _2. If the number of signals to be selected (multiplexing target) is 3 or more, the signals are selected and output in order. However, if the number of signals to be selected is 2 as in this example, two signals are output. The output is selected alternately.

The phase detector 17, based on the data signal D ₃ and D ₄ and the first and second clock signals C ₁ and C _2, the phase control showing the phase relationship between the second clock signal C ₂ and the data transitions Output a signal. Phase control signal is supplied to the phase interpolator 16 which functions as a phase controller for controlling the second clock signal C ₂ phase.

The phase interpolator 16 receives four-phase clock signals of 0 degrees, 90 degrees, 180 degrees, and 270 degrees generated by the four-phase clock generation circuit 11, and outputs these four-phase clock signals according to the phase control signal. by superposing, for generating a second clock signal C _2. The second clock signal C ₂ generated by the phase interpolator 16 is supplied to the selector circuit 15 via the buffer 19. Phase interpolator 16, by controlling the second clock signal C ₂ phase according to the phase control signal to control the second phase relation between the clock signal C ₂ and the data transition.

FIG. 2 is a time chart showing an example of the operation of the signal multiplexing circuit. As shown in FIG. 2, by synchronization with the latch to 0 ° phase position of the data signal D ₁ a first clock signal C ₁ (rising edge shown), a first 0-degree clock signal C ₁ data signals D ₃ to the synchronized data transitions in the phase position are generated. Also by latching in synchronization with the data signal D ₂ to the first 180-degree phase positions of the clock signal C ₁ (falling edge illustrated), data synchronized with the first 180-degree phase positions of the clock signal C ₁ data signals D ₄ to the transition is generated.

Data signal D ₃ is a signal to the 0-degree increments length from the phase to 360 degrees phase, the data signal D ₄ is a signal to unit length to 180 degree phase from -180 degree phase. These data signals D ₃ and D ₄ are input to the selector circuit 15 and are alternately selected and output according to the HIGH and LOW of the _second clock signal C ₂ out of phase with the _first clock signal C _1. Is done. In this example, the second data signal _{D 3} at the HIGH period of the clock signal _{C 2} is selected and output, the data signal _{D 4} is selectively outputted by the second LOW period of the clock signal _{C 2.} In the initial state, as indicated by “C ₂ (initial)”, the phase relationship of the data transition of the data signals D ₃ and D ₄ with respect to the second clock signal C ₂ is not optimal. That is, the center of the HIGH period of the second clock signal C ₂ is not located at the center position of the data unit of the data signal D ₃ (intermediate point between adjacent data transition points), and the data unit of the data signal D ₄ the center of the center position of the second clock signal C ₂ of LOW period is not located. In this state, as described above, the phase interpolator 16 controls the phase of the second clock signal C ₂ in accordance with the phase control signal, so that the phase relationship between the second clock signal C ₂ and the data transition is obtained. Control. The result of this feedback control, the center position of each data unit of the data signals D ₃ and D _4, a state where the center of the central and LOW period of the second clock signal C ₂ of the HIGH period coincide respectively. The second clock signal C _{2 in} this state is indicated as “C ₂ (after FB)”. Therefore, it is possible to select and output the data center portion of each of the waveforms of the data signals D ₃ and D ₄ , and to secure the maximum margin in the signal selection switching operation.

FIG. 3 is a diagram illustrating an example of the configuration of the phase detector. FIG. 4 is a time chart showing an example of the operation of the phase detector. The phase detector 17 in FIG. 3 includes latch circuits (L) 21 and 22, EXOR (exclusive OR) circuits 23 and 24, AND circuits 25 and 26, low-pass filters (LPF) 27 and 28, a comparison circuit 29, and an up circuit. A down counter 30 and a code conversion circuit 31 are included. Based on the data signal D ₃ , the latch circuit 21 generates a data signal that makes a data transition synchronized with the 180 ° phase position of the first clock signal C ₁ . This generated data signal is shown in FIG. 4 as a data signal D ₃ ′. The EXOR circuit 23 generates a first timing signal indicating the timing of data transition by taking an exclusive OR of the data signal D ₃ and the data signal D ₃ ′. This first timing signal is shown in FIG. Period subjects taking the exclusive OR of the data signal D ₃ and the data signal D _{3 'is} the same data value in (period such as a0 to both data sharing), the value of the first timing signal A without exception LOW. Also for the period subjects taking the exclusive OR of the data signal D ₃ and the data signal D _{3 'is} a data value adjacent (e.g. one period other hand a0 is a1), in response to the actual data values The value of exclusive OR is different. However, since the signal to be transmitted is generally scrambled so that the mark rate becomes 1/2 (that is, the appearance probability of HIGH becomes 1/2), the value of the exclusive OR becomes HIGH. The probability of becoming is high. In FIG. 4, the first timing signal A that is the output of the EXOR circuit 23 is shown as a signal that becomes HIGH in the portion corresponding to the exclusive OR value of the adjacent data values for convenience.

Latch circuit 22 generates a data signal for the synchronized data changes to the first 0-degree phase positions of the clock signal C ₁ based on the data signal D _4. This generated data signal is shown in FIG. 4 as a data signal D ₄ ′. The EXOR circuit 24 generates a second timing signal indicating the timing of data transition by taking an exclusive OR of the data signal D ₄ and the data signal D ₄ ′. This second timing signal is shown in FIG. When the exclusive OR of the data signal D ₄ and the data signal D ₄ ′ is taken, the value of the second timing signal B is without exception in the period of the same data value (for example, the period in which both data are b0). LOW. Also for the period subjects taking the exclusive OR of the data signal D ₄ and the data signal D _{4 'is} the data values adjacent (e.g. period one of which is on the other hand b0 is b1), in response to the actual data values The value of exclusive OR is different. In FIG. 4, the second timing signal B that is the output of the EXOR circuit 24 is shown as a signal that becomes HIGH in a portion corresponding to the exclusive OR value of adjacent data values for convenience.

AND circuit 25 generates a first detection signal ( "detection signal 1") by taking the first timing signal A logical sum of the second clock signal C _2. AND circuit 26 generates by taking a second timing signal B the logical sum of the second clock signal C ₂ second detection signal ( "detection signal 2"). In the initial state, as indicated by “C ₂ (initial)”, the phase relationship of the data transition of the data signals D ₃ and D ₄ with respect to the second clock signal C ₂ is not optimal. In this case, the first detection signal and second detection signal corresponding to a second identical HIGH pulse of the clock signal C _2, and hatch hatched "detection signal 1" and the "detection signal 2" pulses As shown in FIG. 4, the signals have different pulse lengths. On the other hand, in the above-described phase control completion state, as shown as “C ₂ (after FB)”, the phase relationship of the data transition of the data signals D ₃ and D _{4 to} the _second clock signal C ₂ is optimal. It becomes. In this state, as shown as pulses hatched in a portion surrounded by a frame at the bottom of FIG. 4, the first detection signal and the second detection corresponding to a second identical HIGH pulse of the clock signal C ₂ The signals are signals having substantially the same pulse length. Therefore, in the phase control, the time average value of the signal value of the first detection signal is compared with the time average value of the signal value of the second detection signal, and feedback control is performed so that both are substantially the same. Good.

FIG. 5 is a flowchart showing the flow of phase control by the phase detector. In step S1, the first detection signal and the second detection signal described above are generated. In step S2, time average values of the first detection signal and the second detection signal are obtained. In step S3, the time average value of the signal value of the first detection signal is compared with the time average value of the signal value of the second detection signal. If the time average value of the signal value of the first detection signal is smaller than the time average value of the signal value of the second detection signal, it is determined in step S4 that the phase is in the delayed phase (second clock signal). phase is slower than the appropriate value state of C _2). If the time average value of the signal value of the first detection signal is larger than the time average value of the signal value of the second detection signal, it is determined in step S5 that the phase is in the advanced phase (second clock). phase is earlier than the proper value state of the signal C _2). In step S6, the phase is variably adjusted according to the determination result of the phase state.

  The low-pass filters 27 and 28 in FIG. 3 and circuit elements downstream thereof are parts for realizing the above-described phase control. The low pass filter 27 in FIG. 3 obtains a time average value of the first detection signal that is the output of the AND circuit 25. The low-pass filter 28 obtains a time average value of the second detection signal that is the output of the AND circuit 26. The comparison circuit 29 compares the time average value of the signal value of the first detection signal and the time average value of the signal value of the second detection signal, and generates a phase control signal indicating which is greater. For example, if the time average value of the signal value of the first detection signal is larger than the time average value of the signal value of the second detection signal, the phase control signal becomes HIGH. In this case, if the time average value of the signal value of the first detection signal is smaller than the time average value of the signal value of the second detection signal, the phase control signal becomes LOW.

The up / down counter 30 counts up or down in synchronization with a predetermined clock signal. For example, the up / down counter 30 counts up in synchronization with the clock signal when the phase control signal is HIGH (for example, the counter value is increased by +1 in response to the rise of each pulse of the clock signal). Further, for example, the up / down counter 30 counts down in synchronization with the clock signal when the phase control signal is LOW (for example, the counter value is decreased by −1 in response to the rise of each pulse of the clock signal). If in the example of FIG. 4, "C _{2 (initial)"} second timing clock signal C ₂ as shown as too early, for example, the phase control signal becomes HIGH, the count value of the up-down counter 30 increases I will do it. Also when the second timing of the clock signal C ₂ is too late to reverse the phase control signal goes LOW, the count value of the up-down counter 30 decreases. If in relation to the counter value of the up-down counter 30 is decreased and the second clock signal C timing ₂ is accelerated (the phase is advanced) phase and the counter value so, so that the appropriate phase states second it is possible to adjust the timing of the clock signal C _2. When the second clock signal C ₂ becomes appropriate phase state, the output of the comparator circuit 29 becomes HIGH and LOW and appear randomly in substantially the same probability data, the counter value of the up-down counter 30 is substantially even with detailed vertical It becomes a constant value. Thus, the second timing of the clock signal C ₂ is settled at a certain timing.

As described above, the data signal D ₃ and the data signal D ₄ is a signal to be transmitted is generally scrambled as for example the mark ratio is 1/2. In addition, in the signal to be transmitted, the maximum time of a period in which one of 0 and 1 continues is specified. Therefore, by the second clock signal C ₂ is feedback controlled based on the averaging processing and comparison processing described above, it is possible to adjust the second clock signal C ₂ to the appropriate phase states. The mark ratio does not have to be ½, and if the mark ratios of the data signal D ₃ and the data signal D ₄ are equal and the 0/1 distribution characteristics are equal, an appropriate phase state is realized by feedback control. can do.

  FIG. 6 is a diagram showing the input / output relationship of the code converter. As shown in FIG. 3, the count value output from the up / down counter 30 is subjected to code conversion by the code conversion circuit 31 and supplied to the phase interpolator 16. The table shown in FIG. 6 shows the upper 2 bits and lower 9 bits of the thermometer code output from the code conversion circuit 31 with the count value output from the up / down counter 30 as an input (Code No.). Thermometer codes are assigned to each count value so that the number of bit changes between two codes corresponding to two adjacent count values is at most 2 bits. By using the thermometer code assigned in this way, signal processing in the phase interpolator 16 at the next stage can be executed stably and easily.

  FIG. 7 is a diagram schematically showing the relationship between the upper 2 bits and lower 9 bits of the thermometer code and the phase. As shown in FIG. 7, the upper 2 bits of the thermometer code represent the position of the quadrant in the phase plane. The lower 9 bits of the thermometer code represent the position (phase) on the unit circle in the phase plane. As the count value (Code No.) increases to 0, 1, 2,..., The phases are −360 °, −360 ° + (90/16) °, −360 ° + 2 × (90/16) °. , ... and gradually proceed.

  FIG. 8 is a diagram illustrating an example of a circuit configuration of the phase interpolation circuit. The phase interpolator 16 shown in FIG. 8 includes differential amplifier circuits 41-1 to 41-4, current setting circuits 42-1 to 42-4, a DAC (digital-analog converter) 43, an offset adjustment circuit 44, and an output. A buffer 45 is included. The DAC 43 receives the upper 2 bits and the lower 9 bits of the thermometer code output from the code conversion circuit 31, and generates four analog current signals corresponding to the count value by digital-analog conversion of the thermometer code. . Specifically, a control voltage corresponding to the thermometer code is applied to the gates of a plurality of PMOS transistors connected in parallel included in the DAC 43, and four currents having different current amounts corresponding to the thermometer code are generated. . These four currents are supplied to current setting circuits 42-1 to 42-4, respectively. The current values of these four analog current signals are values representing weights when the multiphase clock signals having different phases are weighted and superimposed.

  The current setting circuits 42-1 to 42-4 have the same circuit configuration, and the circuit configuration of the current setting circuit 42-1 is shown as a representative. The current setting circuit 42-1 includes a current mirror circuit composed of two NMOS transistors whose gates are connected to each other and a PMOS transistor. The current setting circuit 42-1 generates a gate voltage of the NMOS transistor so that a current amount equal to the current signal supplied from the DAC 43 flows through the NMOS transistor, and supplies the gate voltage to the differential amplifier circuit 41-1. Further, the current setting circuit 42-1 generates a gate voltage of the PMOS transistor at the node w0 so that a current amount equal to the current signal supplied from the DAC 43 is supplied to the PMOS transistor, and the gate voltage is generated at the differential amplifier circuit 41-. 1 is supplied. Similarly, the current setting circuits 42-2 to 42-4 generate gate voltages that cause the current amount equal to the current signal supplied from the DAC 43 to flow through the NMOS transistor and the PMOS transistor, and differentially amplify the gate voltages. The signals are supplied to the circuits 41-2 to 41-4, respectively. As a result, a bias current having a specific amount of current corresponding to the thermometer code from the code conversion circuit 31 flows through the differential amplifier circuits 41-1 to 41-4.

  The differential amplifier circuits 41-1 to 41-4 have the same circuit configuration, and the circuit configuration of the differential amplifier circuit 41-1 is shown as a representative. The differential amplifier circuit 41-1 includes an NMOS transistor pair and a PMOS transistor pair having a differential configuration. Clock signals θ0 and θ2 whose phases are reversed from each other are applied to the gates of the NMOS transistor pair. Similarly, clock signals θ0 and θ2 whose phases are inverted from each other are also applied to the gates of the PMOS transistor pair. The clock signals θ0 and θ2 are clock signals having a 0 degree phase and a 180 degree phase, respectively. The amount of current flowing through the NMOS transistor pair and the PMOS transistor pair is controlled to be the amount set by the current setting circuit 42-1. Thus, the phase component of 0 ° included in the output clock signals φ0 and φ2 output from the output buffer 45 is adjusted. Similarly, clock signals θ1 and θ3 whose phases are mutually inverted are supplied to the differential amplifier circuit 41-2. The clock signals θ1 and θ3 are clock signals having a phase of 90 degrees and a phase of 270 degrees, respectively. The amount of current flowing through the differential amplifier circuit 41-2 is controlled to be the amount set by the current setting circuit 42-2. Thus, the 90 ° phase component included in the output clock signals φ0 and φ2 output from the output buffer 45 is adjusted. The differential amplification circuit 41-3 is supplied with clock signals θ2 and θ0 whose phases are inverted from each other. The amount of current flowing through the differential amplifier circuit 41-3 is controlled so as to be the amount set by the current setting circuit 42-3. Thus, the 180 ° phase component included in the output clock signals φ0 and φ2 output from the output buffer 45 is adjusted. The differential amplifier circuit 41-4 is supplied with clock signals θ3 and θ1 whose phases are reversed. The amount of current flowing through the differential amplifier circuit 41-4 is controlled to be the amount set by the current setting circuit 42-4. Thereby, the phase component of 270 ° included in the output clock signals φ0 and φ2 output from the output buffer 45 is adjusted.

  The offset adjustment circuit 44 adjusts so that the average voltage of the input signal of the output buffer 45 becomes a predetermined offset voltage. Specifically, the average voltage of the signal voltage that changes at the input portion of the output buffer 45 is detected by a capacitive element, and the average voltage and a predetermined threshold voltage are compared by a comparator, whereby the input signal of the output buffer 45 is Adjust the average voltage. As a result, the average voltage of the two inputs of the output buffer 45 is adjusted to a desired offset voltage equal to each other.

  FIG. 9 is a diagram illustrating a functional configuration of the phase interpolation circuit. The functional configuration of the phase interpolator 16 in FIG. 8 can be shown as in FIG. The weighting circuit 51 weights the clock signals θ0 and θ2 having a phase of 0 degrees and a phase of 180 degrees by x times and outputs them. The weighting circuit 52 weights the clock signals θ1 and θ3 having a phase of 90 degrees and a phase of 270 degrees, respectively, by 1-x times and outputs the result. The output buffer 53 outputs clock signals φ0 and φ2 obtained by adding the clock signals θ0 and θ2 weighted x times and the clock signals θ1 and θ3 weighted 1-x times.

FIG. 10 is a diagram for explaining the operation of the phase interpolation circuit. In FIG. 10, clock signals θ0 and θ2 weighted x times are shown as cs (t), and clock signals θ1 and θ3 weighted 1-x times are shown as sn (t). By adding the waveform of x · cs (t) and the waveform of (1-x) · sn (t), a waveform indicated by a dotted line is obtained. The waveform indicated by the dotted line corresponds to clock signals φ0 and φ2 obtained by addition. By adjusting the value of the weighting x, the phases of the clock signals φ0 and φ2 can be adjusted. That is, in FIG. 3, the second clock signal C ₂ output from the phase interpolator 16 is adjusted by adjusting the value of the weighting x in accordance with the thermometer code supplied from the code conversion circuit 31 of the phase detector 17. Can be adjusted.

FIG. 11 is a diagram illustrating a modification of the configuration of the signal multiplexing circuit. In FIG. 11, the same components as those of FIG. 1 are referred to by the same numerals, and a description thereof will be omitted. The signal multiplexing circuit shown in FIG. 11 differs from the signal multiplexing circuit shown in FIG. 1 in that a four-phase voltage controlled oscillator (QuadVCO) 11A is provided as a specific example of the four-phase clock generation circuit 11. . The four-phase voltage controlled oscillator 11A is, for example, a VCO of a PLL circuit that generates a clock signal of a system provided with a signal multiplexing circuit, and generates a four-phase clock signal having a frequency corresponding to an applied control voltage. The phases of these four-phase clock signals are 0 degree, 90 degrees, 180 degrees, and 270 degrees. A pair of clock signals with 0 ° of the clock signal and the 180 degree clock signal have opposite phases to each other, via the buffer 18 is supplied to the first latch circuit 12 to 14 as a clock signal C _1. The four-phase clock signals of 0 degrees, 90 degrees, 180 degrees, and 270 degrees are supplied to the phase interpolator 16. The phase interpolator 16 generates the _second clock signal C2 having a desired phase by the feedback control described above.

FIG. 12 is a diagram illustrating a modification of the configuration of the signal multiplexing circuit. 12, the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted. The signal multiplexing circuit shown in FIG. 12 is different from the signal multiplexing circuit shown in FIG. 1 in that a phase interpolator 16A is provided instead of the phase interpolator 16. While controlling the second clock signal C ₂ of the phase by the phase interpolator 16 on the basis of the feedback control by the signal multiplexing circuit shown in FIG. 1, the phase interpolator 16A based on the feedback control in the multiplexer circuit shown in FIG. 12 controlling the first clock signal C ₁ of phase by. By controlling the phase of the first clock signal C ₁ in this way, the second clock signal and the data signals D ₃ and D ₃ are controlled in the same manner as in the case of controlling the phase of the _second clock signal C ₂ . The phase relationship with the data transition can be adjusted to an appropriate relationship.

  FIG. 13 is a diagram illustrating a modification of the configuration of the signal multiplexing circuit. In FIG. 13, the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted. Compared with the signal multiplexing circuit shown in FIG. 1, the signal multiplexing circuit shown in FIG. 13 is a frequency divider (Div) 11B-1 and a voltage controlled oscillator (VCO) 11B as a specific example of the four-phase clock generation circuit 11. -2 is different. The voltage controlled oscillator 11B-2 is, for example, a VCO of a PLL circuit that generates a clock signal of a system provided with a signal multiplexing circuit, and generates a clock signal having a frequency corresponding to an applied control voltage. The frequency divider 11B-1 divides the clock signal oscillated by the voltage controlled oscillator 11B-2, so that, for example, the frequency is 1/4 and the phase is 0, 90, 180, and 270 degrees. Generate a clock signal.

  FIG. 14 is a diagram illustrating an example of the configuration of the signal transmission system. The signal transmission system of FIG. 14 includes an optical transmitter 61, an optical receiver 62, an optical amplifier 63, and an optical amplifier 64. The optical signal transmitted from the optical transmitter 61 is amplified by the optical amplifier 63 and transmitted through the optical fiber. The optical signal transmitted through the optical fiber is amplified by the optical amplifier 64 and received by the optical receiver 62.

  The optical transmitter 61 includes an x: 1 multiplexer (MUX) 71, a clock amplifier 72, a D-flip flop (DF / F) 73, a driver 74, and an optical modulator 75. A serial transmission signal obtained by multiplexing signals in a x-to-one manner by the multiplexer 71 is latched in the D-flip flop 73 in synchronization with the clock signal generated by the clock amplifier 72. In response to the data signal latched by the D-flip flop 73, the driver 74 drives the optical modulator 75 to modulate the optical signal. The multiplexer 71 performs x: 1 multiplexing processing by a tree structure in which a plurality of 2: 1 multiplexing circuits are connected. As the 2: 1 multiplexing circuit, for example, the multiplexing circuit shown in FIG. 1 or FIGS. 11 to 14 can be used.

  The optical receiver 62 includes an amplifier 81, a timing extractor 82, a clock amplifier 83, an identification circuit 84, and a 1: x demultiplexer (DEMUX) 85. The amplifier 81 converts the received optical signal into an electrical signal and amplifies it. The timing extractor 82 extracts the timing of the clock signal based on the data transition of the received signal and regenerates the clock signal. The clock amplifier 83 amplifies the regenerated clock signal and supplies it to the identification circuit 84 and the demultiplexer 85. The identification circuit 84 identifies 0 and 1 of the data signal in synchronization with the clock signal. The demultiplexer 85 generates individual signals by separating (demultiplexing) the serial reception data after identification.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

11 Four-phase clock generation circuit 12, 13, 14 Latch circuit 15 Selector circuit 16 Phase interpolator 17 Phase detector 18, 19 Buffer

Claims (5)

A first data signal that makes a data transition synchronized with a first phase position of the first clock signal and a second phase position that is 180 degrees out of phase with the first phase position of the first clock signal. A selector circuit that receives a second data signal that performs synchronized data transition, and sequentially selects and outputs the first and second data signals according to a second clock signal;
A phase detector for outputting a phase control signal indicating a phase relationship between the second clock signal and the data transition based on the first and second data signals and the first and second clock signals; ,
And a phase controller that controls the phase relationship in accordance with the phase control signal.   The phase detector generates a third data signal that performs data transition in synchronization with the second phase position of the first clock signal based on the first data signal, and generates the first data signal. And the third data signal to generate a first timing signal indicating the timing of the data transition, and based on the second data signal, the first clock signal of the first clock signal A second timing signal indicating a timing of the data transition by generating a fourth data signal having a data transition synchronized with a phase position and exclusive OR of the second data signal and the fourth data signal; 2. The signal multiplexing according to claim 1, wherein the phase control signal is generated according to the first timing signal, the second timing signal, and the second clock signal. Circuit.   The phase detector calculates a logical sum of a time average value of a signal obtained by logically summing the first timing signal and the second clock signal, and the second timing signal and the second clock signal. 3. The signal multiplexing circuit according to claim 1, wherein the phase control signal is generated by comparing a time average value of the taken signal.   4. The signal multiplexing circuit according to claim 1, wherein the phase controller adjusts a phase of the second clock signal in accordance with the phase control signal. 5.   4. The signal multiplexing circuit according to claim 1, wherein the phase controller adjusts a phase of the first clock signal in accordance with the phase control signal. 5.

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