JP5637795B2 - 装置 - Google Patents
装置 Download PDFInfo
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- JP5637795B2 JP5637795B2 JP2010226017A JP2010226017A JP5637795B2 JP 5637795 B2 JP5637795 B2 JP 5637795B2 JP 2010226017 A JP2010226017 A JP 2010226017A JP 2010226017 A JP2010226017 A JP 2010226017A JP 5637795 B2 JP5637795 B2 JP 5637795B2
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- Prior art keywords
- layer
- damascene wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Nanotechnology (AREA)
- Chemical & Material Sciences (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Description
Claims (7)
- 第1の溝を有する絶縁層と、
前記第1の溝内に形成され、第1の領域における上部に凹部を有する銅を含む第1のダマシン配線層と、
前記第1のダマシン配線層の前記凹部の内面上に形成される少なくとも1つのグラフェンシートと
を具備し、
前記第1のダマシン配線層と前記少なくとも1つのグラフェンシートとで複合配線を構成する配線構造を有する装置。 - 第1の溝を有する絶縁層と、
前記第1の溝内に形成され、第1の領域における上部に凹部を有する銅を含む第1のダマシン配線層と、
前記第1のダマシン配線層の前記凹部の内面上及び前記凹部以外の前記第1のダマシン配線層上に形成され、前記凹部を満たさない少なくとも1つのグラフェンシートと、
前記少なくとも1つのグラフェンシート上に形成され、前記凹部を満たす絶縁層と、
前記少なくとも1つのグラフェンシートの上方に位置し、前記少なくとも1つのグラフェンシートのシート面内方向の端部に接触するコンタクトプラグと
を具備し、
前記第1のダマシン配線層と前記少なくとも1つのグラフェンシートとで複合配線を構成する配線構造を有する装置。 - 第1の溝を有する絶縁層と、
前記第1の溝内に形成され、第1の領域における上部に凹部を有する銅を含む第1のダマシン配線層と、
前記第1のダマシン配線層の前記凹部の内面上及び前記凹部以外の前記第1のダマシン配線層上に形成され、前記凹部を満たす少なくとも1つのグラフェンシートと、
前記少なくとも1つのグラフェンシートの上方に位置し、前記少なくとも1つのグラフェンシートのシート面内方向の端部に接触するコンタクトプラグと
を具備し、
前記第1のダマシン配線層と前記少なくとも1つのグラフェンシートとで複合配線を構成する配線構造を有する装置。 - 第1の溝を有する絶縁層と、
前記第1の溝の内面上に形成され、前記第1の溝を満たさないコバルトを含むバリアメタル層と、
前記バリアメタル層上に形成され、第1の領域における上部に凹部を有し、前記凹部内の一部で前記バリアメタル層を被覆しない銅を含む第1のダマシン配線層と、
前記第1のダマシン配線層の前記凹部の内面上に形成される少なくとも1つのグラフェンシートと
を具備し、
前記第1のダマシン配線層と前記少なくとも1つのグラフェンシートとで複合配線を構成する配線構造を有する装置。 - 請求項1乃至4のいずれか1項に記載の装置において、さらに、前記絶縁層の第2の溝内に形成される銅を含む第2のダマシン配線層と、前記第2のダマシン配線層上に形成され、下端が前記第2の溝の上端よりも上にある少なくとも1つのグラフェンシートとを具備することを特徴とする装置。
- 請求項1乃至4のいずれか1項に記載の装置において、前記第1のダマシン配線層は、第2の領域における上部に凹部を有さず、前記第1の領域において前記第2の領域よりも狭い幅を有することを特徴とする装置。
- 請求項2及び3のいずれか1項に記載の装置において、前記コンタクトプラグの下端の幅は、前記第1の溝の上端の幅と同じ又はそれよりも大きいことを特徴とする装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010226017A JP5637795B2 (ja) | 2010-10-05 | 2010-10-05 | 装置 |
TW100132869A TWI501299B (zh) | 2010-10-05 | 2011-09-13 | 半導體裝置 |
KR1020110092992A KR101311032B1 (ko) | 2010-10-05 | 2011-09-15 | 반도체 장치 |
US13/233,312 US8410608B2 (en) | 2010-10-05 | 2011-09-15 | Interconnect structure device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010226017A JP5637795B2 (ja) | 2010-10-05 | 2010-10-05 | 装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012080014A JP2012080014A (ja) | 2012-04-19 |
JP5637795B2 true JP5637795B2 (ja) | 2014-12-10 |
Family
ID=45889096
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010226017A Expired - Fee Related JP5637795B2 (ja) | 2010-10-05 | 2010-10-05 | 装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8410608B2 (ja) |
JP (1) | JP5637795B2 (ja) |
KR (1) | KR101311032B1 (ja) |
TW (1) | TWI501299B (ja) |
Families Citing this family (37)
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JP2012199520A (ja) * | 2011-03-10 | 2012-10-18 | Toshiba Corp | 半導体装置およびその製造方法 |
US8482126B2 (en) | 2011-09-02 | 2013-07-09 | Kabushiki Kaisha Toshiba | Semiconductor device |
WO2013096273A1 (en) * | 2011-12-20 | 2013-06-27 | University Of Florida Research Foundation, Inc. | Graphene-based metal diffusion barrier |
US9472450B2 (en) * | 2012-05-10 | 2016-10-18 | Samsung Electronics Co., Ltd. | Graphene cap for copper interconnect structures |
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US8952258B2 (en) | 2012-09-21 | 2015-02-10 | International Business Machines Corporation | Implementing graphene interconnect for high conductivity applications |
US9202743B2 (en) * | 2012-12-17 | 2015-12-01 | International Business Machines Corporation | Graphene and metal interconnects |
US9293412B2 (en) | 2012-12-17 | 2016-03-22 | International Business Machines Corporation | Graphene and metal interconnects with reduced contact resistance |
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JP5813678B2 (ja) * | 2013-02-15 | 2015-11-17 | 株式会社東芝 | 半導体装置 |
JP5583236B1 (ja) * | 2013-03-19 | 2014-09-03 | 株式会社東芝 | グラフェン配線 |
JP5826783B2 (ja) * | 2013-03-25 | 2015-12-02 | 株式会社東芝 | 半導体装置 |
US9209136B2 (en) * | 2013-04-01 | 2015-12-08 | Intel Corporation | Hybrid carbon-metal interconnect structures |
US9431346B2 (en) | 2013-04-30 | 2016-08-30 | GlobalFoundries, Inc. | Graphene-metal E-fuse |
US9257391B2 (en) * | 2013-04-30 | 2016-02-09 | GlobalFoundries, Inc. | Hybrid graphene-metal interconnect structures |
US9305879B2 (en) | 2013-05-09 | 2016-04-05 | Globalfoundries Inc. | E-fuse with hybrid metallization |
US9171801B2 (en) | 2013-05-09 | 2015-10-27 | Globalfoundries U.S. 2 Llc | E-fuse with hybrid metallization |
US9536830B2 (en) | 2013-05-09 | 2017-01-03 | Globalfoundries Inc. | High performance refractory metal / copper interconnects to eliminate electromigration |
JP2015138901A (ja) * | 2014-01-23 | 2015-07-30 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP6353308B2 (ja) * | 2014-07-24 | 2018-07-04 | 株式会社カネカ | 配線材料、配線材料の製造方法、および配線材料を用いた配線板の製造方法 |
KR20160020870A (ko) * | 2014-08-14 | 2016-02-24 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
JP2016063095A (ja) | 2014-09-18 | 2016-04-25 | 株式会社東芝 | 配線及びその製造方法 |
JP2016063096A (ja) | 2014-09-18 | 2016-04-25 | 株式会社東芝 | グラフェン配線とその製造方法 |
US9252080B1 (en) * | 2014-10-15 | 2016-02-02 | Globalfoundries Inc. | Dielectric cover for a through silicon via |
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JP2017050419A (ja) | 2015-09-02 | 2017-03-09 | 株式会社東芝 | 半導体装置とその製造方法 |
JP6077076B1 (ja) | 2015-09-11 | 2017-02-08 | 株式会社東芝 | グラフェン配線構造及びグラフェン配線構造の作製方法 |
KR102310404B1 (ko) | 2015-11-05 | 2021-10-07 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
CN107564888B (zh) | 2016-07-01 | 2020-09-15 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其制造方法 |
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JP2023531617A (ja) * | 2020-06-23 | 2023-07-25 | ラム リサーチ コーポレーション | 阻害剤としてグラフェンを使用する選択的堆積 |
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US20230090280A1 (en) * | 2021-09-23 | 2023-03-23 | Applied Materials, Inc. | Selective graphene deposition |
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JP5395542B2 (ja) | 2009-07-13 | 2014-01-22 | 株式会社東芝 | 半導体装置 |
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JP5242643B2 (ja) | 2010-08-31 | 2013-07-24 | 株式会社東芝 | 半導体装置 |
JP5550515B2 (ja) | 2010-10-05 | 2014-07-16 | 株式会社東芝 | グラフェン配線およびその製造方法 |
JP2012080005A (ja) | 2010-10-05 | 2012-04-19 | Toshiba Corp | グラフェン配線およびその製造方法 |
-
2010
- 2010-10-05 JP JP2010226017A patent/JP5637795B2/ja not_active Expired - Fee Related
-
2011
- 2011-09-13 TW TW100132869A patent/TWI501299B/zh not_active IP Right Cessation
- 2011-09-15 US US13/233,312 patent/US8410608B2/en not_active Expired - Fee Related
- 2011-09-15 KR KR1020110092992A patent/KR101311032B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TWI501299B (zh) | 2015-09-21 |
US20120080796A1 (en) | 2012-04-05 |
KR20120035855A (ko) | 2012-04-16 |
KR101311032B1 (ko) | 2013-09-24 |
JP2012080014A (ja) | 2012-04-19 |
US8410608B2 (en) | 2013-04-02 |
TW201232637A (en) | 2012-08-01 |
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