JP5504428B2 - Field effect transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly, a high electron mobility transistor which is a kind of field effect transistor suitable as a transmission / reception amplifying element or a high-speed data transfer element of a cellular phone or wireless LAN And a manufacturing method thereof.

2. Description of the Related Art Generally, a high electron mobility transistor (HEMT) is known as a high-frequency element in the GHz band typified by a cellular phone or a wireless LAN transmission / reception amplifying element. Typical examples include those in which a GaAs layer on a GaAs substrate or an In _0.53 Ga _0.47 As layer on an InP substrate is used as an electron transit layer, all of which are heterogeneous of GaAs and AlGaAs, InGaAs and InAlAs. It utilizes a two-dimensional electron gas layer that accumulates at the structure interface.

  That is, in order to obtain an element capable of transmitting and receiving radio waves in the tens of GHz band using these elements, a HEMT having an extremely short gate length of 0.2 μm or less is required. In order to form a gate electrode having such a length, optical lithography or electron beam lithography may be used, but advanced techniques are required, and stable production is not easy. In addition, if the gate length is shortened, there is a problem in transistor characteristics such as an increase in noise due to an increase in gate resistance and a decrease in gain. Therefore, there is a demand for a high-frequency device having a new structure that can be easily miniaturized, is mass-productive, and can handle a higher frequency band than before.

  By the way, in the case of a field effect transistor, a parasitic resistance component is mentioned as one of the causes which degrade a high frequency characteristic. In an actual transistor, various resistance components are added in addition to the intrinsic transistor, but especially the increase in the contact resistance of the source and drain electrodes not only deteriorates the overall conductance Gm of the transistor, but also accompanies it. Degrading the maximum available current gain frequency fT and the like. Therefore, various attempts have been made to lower the contact resistance by doping the outermost cap layer in contact with the electrode to increase the electron density in order to reduce the contact resistance of the electrode.

  On the other hand, various methods have been implemented as a method for forming a multilayer film for a field effect transistor having an InGaAs channel. In particular, MBE (molecular beam epitaxy) can be grown at a relatively low temperature. It has many advantages such as fewer generation of defects due to the difference in thermal expansion coefficient, and can be suitably used for forming a multilayer film according to the present invention.

  When forming a multilayer film for a field effect transistor having an InGaAs channel on a GaAs substrate or InP substrate using MBE, it is possible to use various materials as a cap layer for protecting the outermost surface from oxidation. However, InGaAs is often adopted because it has few mismatches in lattice constant and it is easy to form a relatively low resistance electrode contact. In order to reduce the contact resistance between the InGaAs cap layer and the electrode, conventionally, Si (silicon) has been used as an n-type doping material. When attempting to increase the doping concentration using MBE, the crucible temperature is increased in order to increase the vapor pressure of the doping material.

However, when trying to dope Si with MBE at a high concentration, the heater temperature of the Si crucible becomes very high, and the substrate is heated by the radiant heat from the heater and the crucible, making it difficult to form a film at a desired temperature. An electron density of about 10 ¹⁸ / cm ³ is the upper limit. For this reason, there is a limit to the Si doping concentration of the InGaAs cap layer, and there is a limit to reducing the contact resistance between the source electrode and the drain electrode.

Further, as disclosed in Patent Document 1, a method of forming a magnetoresistive element having low temperature dependency by using Sn as a doping material in In _x Ga _1-x As _y Sb _1-y is disclosed. However, a method for reducing the contact resistance of the electrode of the field effect transistor has not been disclosed so far.

Re-publication WO00 / 008695

  However, with conventional doping materials, there is a limit to high-concentration doping, and it has been difficult to achieve a lower metal-semiconductor contact resistance. Therefore, it has been difficult to produce a field effect transistor having more excellent high frequency characteristics.

  The present invention has been made in view of such problems, and an object of the present invention relates to a field effect transistor having good high-frequency characteristics and a method for manufacturing the same, which is intended to reduce the contact resistance of an electrode.

  As a result of intensive research in order to solve the above problems, the present inventor found that a field effect transistor was produced using a specific manufacturing method, and found that the above object was met. Invented the invention.

The present invention has been made to achieve such an object, and the invention according to claim 1 is a field effect transistor having a multilayer semiconductor structure obtained by epitaxially growing a III-V compound semiconductor thin film. The multilayer semiconductor structure includes a substrate, a buffer layer formed on the substrate, an electron transit layer formed on the buffer layer, a spacer layer formed on the electron transit layer, An electron supply layer formed on the spacer layer, a barrier layer formed on the electron supply layer, and a high electron concentration cap layer formed on the barrier layer, and further on the multilayer semiconductor structure And selectively removing the ohmic-connected source electrode and drain electrode formed on the high electron concentration cap layer, and the high electron concentration cap layer between the source electrode and the drain electrode. Forming a Seth structure comprises a gate electrode formed so as to face to the Schottky connection of the barrier layer exposed in the recess structure, the high electron concentration cap layer, 5 × 10 18 ^/ cm ³ or more It is characterized by being doped with Sn having a concentration of 1 × 10 ²⁰ / cm ³ or less .

The invention according to claim 2 is the invention according to claim 1 , wherein the thickness of the high electron concentration cap layer is 5 nm or more and 100 nm or less.

The invention according to claim 3 is the invention according to claim 1 or 2 , wherein the substrate is GaAs, the electron transit layer is InGaAs, the spacer layer is InAlAs, and the barrier layer is InAlAs. The high electron concentration cap layer is InGaAs.

The invention according to claim 4 is the invention according to claim 1 or 2 , wherein the substrate is GaAs, the electron transit layer is InGaAs, the spacer layer is AlGaAsSb, and the barrier layer is AlGaAsSb. The high electron concentration cap layer is InGaAs.

The invention according to claim 5 is the invention according to claim 1 or 2 , wherein the substrate is InP, the electron transit layer is InGaAs, the spacer layer is InAlAs, and the barrier layer is InAlAs. The high electron concentration cap layer is InGaAs.

The invention according to claim 6 is a method of manufacturing a field effect transistor for forming a multilayer semiconductor structure formed by epitaxially growing a group III-V compound semiconductor thin film, wherein the manufacturing process of the multilayer semiconductor structure comprises: Forming a buffer layer on the substrate; forming an electron transit layer on the buffer layer; forming a spacer layer on the electron transit layer; and forming an electron supply layer on the spacer layer. A source that has a step, a step of forming a barrier layer on the electron supply layer, and a step of forming a high electron concentration cap layer on the barrier layer, and further ohmic-connecting on the high electron concentration cap layer Forming a metal for forming an electrode and a drain electrode, and selectively removing the high electron concentration cap layer between the source electrode and the drain electrode to form a recess structure A step of, on the surface of the barrier layer exposed in the recess structure has the step of forming a Schottky connection gate electrode, 5 × 10 18 ^/ cm ³ or more doping of the high electron concentration cap layer 1 It is characterized by using Sn having a concentration of × 10 ²⁰ / cm ³ or less .

The invention according to claim 7 is the invention according to claim 6 , wherein the thickness of the high electron concentration cap layer is 5 nm or more and 100 nm or less.

The invention according to claim 8 is the invention according to claim 6 or 7 , wherein the substrate is GaAs, the electron transit layer is InGaAs, the spacer layer is InAlAs, and the barrier layer is InAlAs. The high electron concentration cap layer is InGaAs.

The invention according to claim 9 is the invention according to claim 6 or 7 , wherein the substrate is GaAs, the electron transit layer is InGaAs, the spacer layer is AlGaAsSb, and the barrier layer is AlGaAsSb. The high electron concentration cap layer is InGaAs.

The invention according to claim 10 is the invention according to claim 6 or 7 , wherein the substrate is InP, the electron transit layer is InGaAs, the spacer layer is InAlAs, and the barrier layer is InAlAs. The high electron concentration cap layer is InGaAs.

  According to the present invention, it is possible to further reduce the contact resistance of the source and drain electrodes, which has conventionally been difficult to lower, and based on this, a field effect transistor with good high frequency characteristics can be manufactured. can do.

It is sectional drawing of the multilayer semiconductor structure used for manufacture of the field effect transistor which concerns on this invention. FIG. 2 is a cross-sectional configuration diagram for explaining a field effect transistor according to the present invention using the multilayer semiconductor structure shown in FIG. 1. FIG. 6 is a cross-sectional process diagram (No. 1) for describing the method for producing the field effect transistor according to the invention. It is sectional process drawing (2) for demonstrating the manufacturing method of the field effect transistor which concerns on this invention. It is sectional process drawing (the 3) for demonstrating the manufacturing method of the field effect transistor which concerns on this invention. FIG. 6 is a sectional process view (No. 4) for explaining the method for producing the field effect transistor according to the invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view of a multilayer semiconductor structure used for manufacturing a field effect transistor according to the present invention. The substrate 1 may be anything as long as it is a substrate, but a GaAs substrate, an InP substrate, a Si substrate with a single crystal GaAs grown on its surface, a sapphire substrate, or the like is preferable. Among these, a GaAs substrate or InP substrate that can obtain a semi-insulating and high-quality single crystal substrate is particularly preferable.

Here, the semi-insulating property means a material having a resistivity of 10 ⁷ Ω · cm or more. When a single crystal substrate is used, the surface orientation of the substrate is preferably (100), (111), (110), or the like. A plane orientation shifted from 1 ° to 5 ° from these plane orientations may be used. Among these, (100) is optimal for growing a high-quality thin film.

  As is usually done, for the purpose of flattening and cleaning the surface of the substrate, a grown semiconductor of the same material as the substrate may be used as the substrate of the present invention. The most typical example is the growth of GaAs on a GaAs substrate.

  As the buffer layer 2, (a) the lattice constant is close to that of the InGaAs electron transit layer 3, (b) the resistivity is sufficiently higher than that of the InGaAs electron transit layer 3, and (c) the lattice constant is larger than that of the InGaAs electron transit layer 3. Even when directly stacked on different substrates such as GaAs, it is preferable to have a flat surface with few defects. For this purpose, AlGaAs, InAlAs, AlGaAs / InAlAs graded layer, AlGaAsSb, etc. are preferably used.

  The InGaAs electron transit layer 3 may be formed directly on the buffer layer 2, but a layer closest to the lattice constant of the InGaAs electron transit layer 3 can also be provided on the buffer layer 2. By this method, the InGaAs electron transit layer 3 with few lattice defects can be formed. The flatness of the surface of the buffer layer 2 is better as the film thickness is larger, but it is desirable to make it as thin as possible in the industry. That is, the thickness of the buffer layer 2 is preferably in the range of 5 nm to 3000 nm, more preferably 10 nm to 1000 nm.

  In addition, it is one of preferred embodiments that the buffer layer 2 is used as the electron supply layer 5 to the InGaAs electron transit layer 3. In that case, the dopant may be uniformly doped in the thickness direction, may be distributed, or may be locally delta-doped. Here, delta doping is a doping technique performed by simultaneously irradiating a dopant and a group V element in the thin film growth of a group III-V compound semiconductor using MBE. As the dopant of the electron supply layer 5, Sn or Si is preferably used in the present invention.

The InGaAs electron transit layer 3 changes the electron density by the voltage applied to the control electrode such as the gate electrode 102 and controls the electric conduction. The In _x Ga _1-x As (0 ≦ x ≦ 1) electron transit layer 3 is preferable because the higher the In composition x, the higher the electron mobility. In particular, the In composition x is 0.53 or more and 1 or less. It is preferable.

  If the thickness of the InGaAs electron transit layer 3 is too thin, it is likely to be affected by the flatness of the interface and defects, and if it is too thick, the controllability by the control electrode is affected. Therefore, the film thickness is preferably 2000 nm or less. More preferably 2 nm to 100 nm, and still more preferably 5 nm to 60 nm.

The electron concentration of the In _x Ga _1-x As electron transit layer 3 is preferably 3 × 10 ¹⁷ cm ⁻³ or more and 2 × 10 ¹⁸ cm ⁻³ or less because of high electron mobility. However, the electron concentration is not limited to this concentration because it is appropriately determined in view of device characteristics such as sheet resistance and high-speed response of the semiconductor device.

  The spacer layer 4 preferably has a lattice constant close to (a) the InGaAs electron transit layer 3 and (b) has a sufficiently high resistivity as compared to the InGaAs electron transit layer 3. The lattice constants of the spacer layer 4 and the InGaAs electron transit layer 3 should be close to the extent that the thickness of the InGaAs electron transit layer 3 does not exceed the critical thickness. For this purpose, AlGaAs, InAlAs, and AlGaAsSb are preferably used.

  If the spacer layer 4 is too thin, it is affected by interface scattering, and if it is too thick, the controllability from the gate electrode 102 is affected. More preferably, it is 3 nm or more and 10 nm or less.

  Next, the electron supply layer 5 used in the present invention has (a) a lattice constant close to that of the InGaAs electron transit layer 3, and (b) gives electrons of a desired concentration to the InGaAs electron transit layer 3. For this purpose, AlGaAs, InAlAs, and AlGaAsSb, which are the same materials as the spacer layer 4, are preferably used, and doping is performed to supply electrons of a desired concentration. Doping may be uniform or distributed in the thickness direction of the electron supply layer 5, or delta doping may be performed at a desired thickness. As the dopant of the electron supply layer 5, Sn or Si is preferably used in the present invention.

  The film thickness of the electron supply layer 5 is preferably 1 nm or more and 10 nm or less, more preferably 2 nm or more and 5 nm or less. Further, when the electron supply layer 5 is only the delta doped layer, the film thickness is as close to zero as possible, strictly speaking, the film thickness is about several atomic layers.

  The barrier layer 6 is for (a) a lattice constant close to that of the electron supply layer 5 and (b) for ensuring insulation between the control electrode such as a gate and the electron supply layer 5. The material is not particularly limited. In addition, when the high electron concentration cap layer 7 to be formed later meets the above-mentioned purpose and has a high resistance to oxidation, the barrier layer 6 and the high electron concentration cap layer 7 are combined to form one layer. It doesn't matter.

That is, usually, In _1-y Al _y As can be used to have the same elemental composition as the spacer layer 4 and the electron supply layer 5, or In _1-y Al _y As having a higher Al concentration than that. . However, the Al concentration y is preferably 0.5 to 0.85 because there is a concern that the spacer layer 4 is likely to be oxidized during the device fabrication process as in the case of the spacer layer 4.

  If the thickness of the barrier layer 6 is too thin, there is a problem in insulation, and if it is too thick, it affects the control of the InGaAs electron transit layer 3 by the gate electrode 102, so that it is preferably 1 nm or more and 50 nm or less, more preferably 2 nm or more. 20 nm or less.

  The high electron concentration cap layer 7 is formed on the barrier layer 6, and its purpose is (a) a lattice constant close to that of the barrier layer 6, and (b) suppression of alteration due to oxidation of the layer below it. And (c) reduce damage caused by plasma processing during device creation, (d) reduce contact resistance between metal and semiconductor, and (e) contribute to reduction of source resistance, which is a problem in high frequency characteristics It is. Any material can be selected as long as it fits these purposes. However, a semiconductor film is usually used because film deposition in the same film deposition apparatus as the electron supply layer 5 and the barrier layer 6 can prevent exposure of the underlying layer to oxygen.

  Further, in the subsequent step of forming the gate electrode 102, it is necessary to selectively remove the high electron concentration cap layer 7 only in the region where the gate electrode 102 is to be formed. As the semiconductor film that can be formed, InGaAs is suitable. Further, as described above, since the high electron concentration cap layer 7 itself is required to have a function of reducing the contact resistance between the metal and the semiconductor and reducing the source resistance, n-type doping is usually performed. To do.

As the n-type dopant, Si is usually often used, but Sn is used in the present invention. The reason for this is that when Si is used as a dopant in the MBE method, the temperature of the Si crucible must be increased in order to ensure the necessary vapor pressure. However, the temperature of the crucible heater exceeds 1300 ° C. Is propagated to the growth substrate, affecting the target film formation temperature, and an electron concentration of substantially 5 × 10 ¹⁸ / cm ³ becomes the upper limit of the doping concentration by Si.

On the other hand, since Sn has a high vapor pressure, the upper limit due to the heater temperature is relaxed. However, in order to ensure the soundness of the InGaAs crystal as the high electron concentration cap layer 7, there is an upper limit of the doping concentration. For this reason, the electron density in doping using Sn of the present invention is preferably 5 × 10 ¹⁸ / cm ³ or more and 1 × 10 ²⁰ / cm ³ or less. More preferably, it is 1 × 10 ¹⁹ / cm ³ or more and 4 × 10 ¹⁹ / cm ³ or less.

  Moreover, when the film thickness of the high electron concentration cap layer 7 of the present invention is too thin, it is insufficient to suppress oxidation of the semiconductor layer under the high electron concentration cap layer 7 and plasma damage during processing. On the other hand, if it is too thick, the distance between the metal and the InGaAs electron transit layer 3 increases, resulting in an increase in contact resistance, or wide removal in the lateral direction when removing the high electron concentration cap layer 7 in the gate process. Since the region where the InGaAs electron transit layer 3 extending in the lateral direction from the source electrode 101 and the drain electrode 103 to the gate electrode 102 overlaps is reduced, the source resistance is undesirably increased. Therefore, the high electron concentration cap layer 7 of the present invention is preferably 5 nm or more and 100 nm or less. More preferably, it is 7 nm or more and 30 nm or less.

Through the above procedure, the multilayer semiconductor structure used in the present invention is formed.
FIG. 2 is a cross-sectional configuration diagram for explaining a field effect transistor according to the present invention using the multilayer semiconductor structure shown in FIG.

  The field effect transistor of the present invention has a multilayer semiconductor structure formed by epitaxially growing a III-V compound semiconductor thin film. The multilayer semiconductor structure includes a substrate 1, a buffer layer 2 formed on the substrate 1, an electron transit layer 3 formed on the buffer layer 2, and a spacer layer 4 formed on the electron transit layer 3. , An electron supply layer 5 formed on the spacer layer 4, a barrier layer 6 formed on the electron supply layer 5, and a high electron concentration cap layer 7 formed on the barrier layer 6.

  Further, the source electrode 101 and the drain electrode 103 that are formed on the high electron concentration cap layer 7 and are ohmic-connected and the high electron concentration cap layer 7 between the source electrode 101 and the drain electrode 103 are selected on the multilayer semiconductor structure. A recess structure is formed by removing the gate electrode 102, and a gate electrode 102 is formed so as to be Schottky connected to the exposed surface of the barrier layer 6 of the recess structure.

The high electron concentration cap layer 7 is doped with Sn. The electron density of the high electron concentration cap layer 7 is preferably 5 × 10 ¹⁸ / cm ³ or more and 1 × 10 ²⁰ / cm ³ or less. The thickness of the high electron concentration cap layer 7 is preferably 5 nm or more and 100 nm or less.

  The substrate 1 is GaAs, the electron transit layer 3 is InGaAs, the spacer layer 4 is InAlAs, the barrier layer 6 is InAlAs, and the high electron concentration cap layer 7 is InGaAs.

  The substrate 1 may be GaAs, the electron transit layer 3 may be InGaAs, the spacer layer 4 may be AlGaAsSb, the barrier layer 6 may be AlGaAsSb, and the high electron concentration cap layer 7 may be InGaAs.

  The substrate 1 may be InP, the electron transit layer 3 may be InGaAs, the spacer layer 4 may be InAlAs, the barrier layer 6 may be InAlAs, and the high electron concentration cap layer 7 may be InGaAs.

  Next, a method for manufacturing a field effect transistor according to the present invention using the multilayer semiconductor structure described above will be described. 3 to 6 are cross-sectional process diagrams for explaining a method of manufacturing a field effect transistor according to the present invention.

  First, as shown in FIG. 3, a high electron concentration cap layer 7, a buffer layer 6, an electron supply layer 5, and a spacer layer of a multilayer semiconductor structure are formed by wet etching to electrically isolate each field effect transistor element. Etching is performed until the side surfaces of 4 and the electron transit layer 3 are exposed. In particular, etching is performed until the buffer layer 6 is exposed or a part of the buffer layer 6 is removed.

  Next, as shown in FIG. 4, a metal is deposited on the surface of the high electron concentration cap layer 7 in the element-isolated region by a deposition method, and a source electrode 101 and a drain electrode 103 for ohmic connection are respectively formed. Form. Thereafter, in order to realize a lower contact resistance, annealing is performed to diffuse the metal to the electron transit layer 3. Subsequently, a groove using a resist is formed between the source electrode 101 and the drain electrode 103 in order to form the gate electrode 102.

  An etching solution is supplied through this groove, and the InGaAs cap layer 7 is selectively etched as shown in FIG. 5 to form a recess structure in which the underlying barrier layer 6 is exposed. In this state, metal is vapor-deposited by an evaporation method, and only a desired gate electrode 102 as shown in FIG. 6 is left by a lift-off method in which the metal adhering to the resist is removed together with the resist. Through the above manufacturing process, the field effect transistor as shown in FIG. 2 is formed.

  The above manufacturing method is an example of the manufacturing method of the field effect transistor of the present invention, and it is possible to manufacture the field effect transistor using other methods and procedures.

  Example 1 of the present invention will be described using a high electron mobility transistor (HEMT), which is a kind of field effect transistor, as an example.

A multilayer semiconductor substrate for manufacturing the field effect transistor of Example 1 is shown in FIG. Using an MBE apparatus, an AlGaAs / InAlAs graded layer and an In _0.52 Al _0.48 As buffer layer 2 are lattice-matched with the In _0.53 Ga _0.47 As electron transit layer 3 on the GaAs substrate 1. Are sequentially formed. Next, an In _0.53 Ga _0.47 As electron transit layer 3 is formed to a thickness of 20 nm, and an In _0.52 Al _0.48 As spacer layer 4 having a thickness of 4 nm is formed thereon. After forming a film and forming a delta doping layer using Si as a dopant, an In _0.52 Al _0.48 As barrier layer 6 having a film thickness of 12 nm is formed, and finally, In _0.53 having a film thickness of 10 nm. The Ga _0.47 As cap layer 7 was formed while doping Sn so that the electron density was 2 × 10 ¹⁹ / cm ³ .

Using this multilayer semiconductor substrate, element isolation was performed by wet etching, and then a three-layer metal of Au / Ge / Au was deposited to form a source electrode 101 and a drain electrode 103, and annealing was performed at 8 × 10 − A contact resistance of 7 Ω · cm 2 was obtained. Further, a recess structure was formed by selective etching between the source electrode and the drain electrode, and a four-layer metal of Pt / Ti / Pt / Au was deposited to form a gate electrode 102 with Lg = 0.1 μm. Current gain _cut-off frequency _{f T} of the transistor of this structure was 250 GHz.

A multilayer semiconductor substrate for manufacturing the field effect transistor of Example 2 is shown in FIG. The AlGaAsSb buffer layer 2 is formed on the GaAs substrate 1 using the MBE apparatus so as to lattice match with the In _0.53 Ga _0.47 As electron transit layer 3. Next, the In _0.53 Ga _0.47 As electron transit layer 3 is formed so as to have a thickness of 20 nm, the AlGaAsSb spacer layer 4 having a thickness of 4 nm is formed thereon, and Sn is used as a dopant. After forming the delta doping layer, an AlGaAsSb barrier layer 6 having a film thickness of 12 nm is formed, and finally an In _0.53 Ga _0.47 As cap layer 7 having a film thickness of 10 nm is formed. Film formation was performed while doping Sn so as to be ¹⁹ / cm ³ .

Using this multilayer semiconductor substrate, element isolation was performed by wet etching, and then a three-layer metal of Au / Ge / Au was deposited to form the source electrode 101 and the drain electrode 103, and annealing was performed at 9 × 10 ⁻ A contact resistance of ⁷ Ω · cm ² was obtained. Further, a recess structure was formed by selective etching between the source electrode and the drain electrode, and a four-layer metal of Pt / Ti / Pt / Au was deposited to form a gate electrode 102 with Lg = 0.1 μm. Current gain _cut-off frequency _{f T} of the transistor of this structure was 250 GHz.

A multilayer semiconductor substrate for manufacturing the field effect transistor of Example 3 is shown in FIG. An InP buffer layer 2 is homo-deposited on the InP substrate 1 using an MBE apparatus. Next, an In _0.53 Ga _0.47 As electron transit layer 3 is formed to a thickness of 20 nm, and an In _0.52 Al _0.48 As spacer layer 4 having a thickness of 4 nm is formed thereon. After forming a film and forming a delta doping layer using Si as a dopant, an In _0.52 Al _0.48 As barrier layer 6 having a film thickness of 12 nm is formed, and finally, In _0.53 having a film thickness of 10 nm. The Ga _0.47 As cap layer 7 was formed while doping Sn so that the electron density was 2 × 10 ¹⁹ / cm ³ .

Using this multilayer semiconductor substrate, element isolation was performed by a wet etching method, and then an Au / Ge / Au three-layer metal was deposited to form a source electrode 101 and a drain electrode 103, and annealing was performed at 8 × 10 ⁻ A contact resistance of ⁷ Ω · cm ² was obtained. Further, a recess structure was formed by selective etching between the source electrode and the drain electrode, and a four-layer metal of Pt / Ti / Pt / Au was deposited to form a gate electrode 102 with Lg = 0.1 μm. Current gain _cut-off frequency _{f T} of the transistor of this structure was 250 GHz.

1 Substrate 2 Buffer layer 3 Electron travel layer (InGaAs)
4 Spacer Layer 5 Electron Supply Layer 6 Barrier Layer 7 High Electron Concentration Cap Layer 101 Source Electrode 102 Gate Electrode 103 Drain Electrode

Claims (10)

In a field effect transistor having a multilayer semiconductor structure obtained by epitaxially growing a group III-V compound semiconductor thin film, the multilayer semiconductor structure includes:
A substrate,
A buffer layer formed on the substrate;
An electron transit layer formed on the buffer layer;
A spacer layer formed on the electron transit layer;
An electron supply layer formed on the spacer layer;
A barrier layer formed on the electron supply layer;
A high electron concentration cap layer formed on the barrier layer, and further on the multilayer semiconductor structure,
A source electrode and a drain electrode which are ohmic-connected and formed on the high electron concentration cap layer;
A recess structure is formed by selectively removing the high electron concentration cap layer between the source electrode and the drain electrode, and a Schottky connection is formed to the surface of the barrier layer where the recess structure is exposed. A field effect transistor comprising a gate electrode, wherein the high electron concentration cap layer is doped with Sn having a concentration of 5 × 10 ¹⁸ / cm ³ or more and 1 × 10 ²⁰ / cm ³ or less . The field effect transistor according to claim 1 , wherein the thickness of the high electron concentration cap layer is 5 nm or more and 100 nm or less. In the substrate GaAs, in the electron transit layer is InGaAs, in the spacer layer is InAlAs, in the barrier layer is InAlAs, according to claim 1 or 2 wherein the high electron density capping layer is characterized in that it is a InGaAs Field effect transistor. In the substrate GaAs, in the electron transit layer is InGaAs, in the spacer layer is AlGaAsSb, in the barrier layer is AlGaAsSb, according to claim 1 or 2 wherein the high electron density capping layer is characterized in that it is a InGaAs Field effect transistor. In the substrate InP, in the electron transit layer is InGaAs, in the spacer layer is InAlAs, in the barrier layer is InAlAs, according to claim 1 or 2 wherein the high electron density capping layer is characterized in that it is a InGaAs Field effect transistor. In the method of manufacturing a field effect transistor for forming a multilayer semiconductor structure obtained by epitaxially growing a III-V compound semiconductor thin film, the manufacturing process of the multilayer semiconductor structure includes:
Forming a buffer layer on the substrate;
Forming an electron transit layer on the buffer layer;
Forming a spacer layer on the electron transit layer;
Forming an electron supply layer on the spacer layer;
Forming a barrier layer on the electron supply layer;
Forming a high electron concentration cap layer on the barrier layer, and
Forming a metal for forming a source electrode and a drain electrode in ohmic contact on the high electron concentration cap layer;
Selectively removing the high electron concentration cap layer between the source electrode and the drain electrode to form a recess structure;
Forming a gate electrode for Schottky connection on the surface of the exposed barrier layer of the recess structure, and doping the high electron concentration cap layer to 5 × 10 ¹⁸ / cm ³ or more 1 × 10 ²⁰ / A method of manufacturing a field effect transistor, characterized by using Sn having a concentration of cm ³ or less . 7. The method of manufacturing a field effect transistor according to claim 6 , wherein the thickness of the high electron concentration cap layer is 5 nm or more and 100 nm or less. 8. The substrate according to claim 6 , wherein the substrate is GaAs, the electron transit layer is InGaAs, the spacer layer is InAlAs, the barrier layer is InAlAs, and the high electron concentration cap layer is InGaAs. Manufacturing method of the field effect transistor. 8. The substrate according to claim 6 , wherein the substrate is GaAs, the electron transit layer is InGaAs, the spacer layer is AlGaAsSb, the barrier layer is AlGaAsSb, and the high electron concentration cap layer is InGaAs. Manufacturing method of the field effect transistor. 8. The substrate according to claim 6 , wherein the substrate is InP, the electron transit layer is InGaAs, the spacer layer is InAlAs, the barrier layer is InAlAs, and the high electron concentration cap layer is InGaAs. Manufacturing method of the field effect transistor.

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